Patent Grant
10713198
The present application is the national stage of International Pat. App. No. PCT/EP2017/053901 filed Feb. 21, 2017, and claims priority under 35 U.S.C. § 119 to DE 10 2016 203 307.7, filed in the Federal Republic of Germany on Mar. 1, 2016, the content of each of which are incorporated herein by reference in their entireties.
The present invention relates to a direct memory access control unit and a method for operation thereof.
Processing units, for example, processors that include one or multiple processor cores and that are able to access a working memory are known on the market. Processing systems that include one or multiple processing units generally also include a plurality of additional units that cooperate with the processing unit, for example, input components and output components (“IO”) and the like. At least some of the aforementioned elements of the processing system are able to exchange data with one another via a shared, preferably parallel bus. In addition, methods for a so-called direct memory access, DMA, are known, through which the exchange of data can be improved via the shared bus. One example of such a processing unit is the MPC5777M of NXP.
Features important for the present invention are found in the following description and in the drawings, whereby the features both by themselves as well as in different combinations can be important for the present invention, without explicit reference being made again thereto.
The present invention relates to a direct memory access control unit for a processing unit that includes a working memory, the direct memory access control unit including a terminal for connecting the direct memory access control unit to a bus system that connects the processing unit to the working memory. The direct memory access control unit is designed to carry out the following steps:
The transmission of the information blocks described in such a way characterizes in the present case a so-called “Tx-operation,” i.e., from the working memory to the communication module.
The aforementioned information blocks can include “payload data” and/or pieces of control information and, for example, can also form complete data packets, as they can be exchanged with other units by the communication module via a bus system and/or a data network. The processing unit can include one or multiple processor cores, the processor cores also being referred to below as processing units. The processor cores or processing units can be situated in a shared component (integrated circuitry) or in separate components, respectively.
The working memory can be designed as a central working memory, which is usable jointly by the processor cores and/or a respectively associated working memory unit can also be provided for each of the processor cores. This working memory unit, together with the respective processor core, can be situated in a shared component (“internal”) or can be separated physically therefrom (“external”).
The direct memory access control unit is preferably designed with the aid of hardware, i.e., with the aid of one or multiple discrete and/or integrated electronic components.
In one embodiment, the direct memory access control unit is a separate unit, which is used in addition to a direct memory access control unit already known from the related art.
In one embodiment, the communication module is designed to couple a CAN bus system functionally with the processing unit or with the processing units, as well as with the working memory or with the working memory units. In one embodiment, the communication module includes a so-called “MCAN module,” which is able to communicate with a CAN bus, to which a plurality of CAN bus users referred to here as “logical units” are connected. The abbreviation “CAN” means “controller area network.” The letter “M” characterizes a manufacturer-specific name affix.
In one preferred embodiment, the working memory is designed in each case as a memory with random access, RAM, as in “random access memory.” Other types of memory are also possible, however.
In one embodiment, the direct memory access control unit is designed to ascertain which information block in each case has the highest priority. Accordingly, a transmission of the information block having the highest priority takes place using a direct memory access from the working memory to the communication module.
Simply put, the direct memory access control unit carries out the transmission of the information blocks as a function of information contents or data contents, in particular, of the information blocks and automatically decides in each case which transmission is carried out next. The present invention has the advantage that in a processing system, which includes at least one processing unit or at least one processor core, as well as one working memory or multiple working memories and at least one communication module, a transmission of information blocks carried out with the aid of a direct memory access can be further improved.
A further advantage is that the direct memory access control unit increases the performance of communication modules that have not been expressly designed for operating with a so-called “multicore system” (i.e., a processing unit that includes multiple processor cores), but were only developed with the design goal of communicating with one processor core. Compare, for example, the “MCAN module” described above. In this way, the principle according to the present invention enables a simple connection of a MCAN module based on direct memory accesses also to processing units that include multiple processor cores. Thus, the potential applications are expanded accordingly.
Even if the aforementioned communication modules are not present as a physical component, but are merely emulated with the aid of hardware and/or of software, an operation also with multicore systems is advantageously possible thanks to the direct memory access control unit.
In one embodiment, the direct memory access control unit is designed to carry out at least one of the following additional steps:
In one embodiment, the acknowledgement signal is the ACK-bit described above, which can be set by the processing unit, as a result of which the direct memory access control unit can be prompted to subsequently carry out the reading-in of the control information. The sending of the acknowledgement signal then corresponds to a resetting of the ACK-bit by the direct memory access control unit. In another embodiment, the ACK-bit or a bit position of the ACK-bit is different from the flag or from a bit position of the flag.
In one advantageous example embodiment, the acknowledgement signal can be provided to indicate that data have been successfully delivered to the communication module, for example, a MCAN module, for sending (including Tx request). For this purpose, the direct memory access control unit can set a bit in the message for the CPU (for example, intern_TransSuccess).
In another advantageous example embodiment, the direct memory access control unit transmits the message to the communication module, for example, a MCAN module, and sets in addition, for example, a Tx request. After a successful sending by the MCAN module, the MCAN module sets the corresponding unique bit in the MCAN module, and only then does the direct access memory control unit transmit an acknowledgement signal to the CPU, according to which the transmission is successfully completed. This can take place via the ACK-bit previously described above.
The aforementioned additional steps can advantageously improve the communication between the processing unit or processing units, the working memory or working memory units, the direct access memory control unit and/or the communication module.
The aforementioned first pieces of configuration information can advantageously control the optional use of the first priorities and/or of the second priorities. The second priority can be defined, for example, with the aid of one or of multiple bit positions (“bit field”) in a respective information block, for example in a header of the information block. However, these bits are particularly preferably provided as additional pieces of information to a CAN message, and are not included in the CAN message itself—i.e., pure control information.
The first priority and/or the second priority is/are preferably transmitted in the pieces of control information of the respective information block. In one embodiment, the sequence is ascertained as a function of the first pieces of configuration information solely with the aid of the first priority. In another embodiment, the sequence is ascertained as a function of the first pieces of configuration information solely with the aid of the second priority.
In another embodiment, the direct memory access control unit is designed to carry out the following steps:
In another use, in which, for example, only one Rx buffer (receive buffer) is configured in a MCAN module, one trigger is sufficient for transmitting from the MCAN module to the RAM. This can be, for example, a NEWDATA flag in the MCAN module. In these cases, a priority control can also be dispensed with.
The transmission of the information blocks described in this way characterizes in the present case a so-called “Rx-operation,” i.e., from the communication module to the working memory. Comparable advantages result, as was described further above for the “Tx-operation.”
In another embodiment, the direct memory access control unit is designed to carry out at least one of the following additional steps:
The local interrupt to the processing unit enables the processing unit to be able to respond immediately if a respective information block to be sent by the communication module is to be transmitted preferably rapidly into the working memory. As a result of the interrupt, the processing unit is able to advantageously process preferably rapidly the previously copied data and, in the process, no longer requires any accesses to a remote memory.
The aforementioned steps can advantageously improve the communication between the processing unit or processing units, the working memory or the working memory units, the direct memory access control unit and/or the communication module. The use of the (optional) second priority likewise allows for an additional improvement when ascertaining the sequence.
In one embodiment, the aforementioned “first” pieces of configuration information for the Rx operation can include a different content than the “first” pieces of configuration information for the Tx operation described above. In another embodiment, the sequence is ascertained as a function of the first pieces of configuration information solely with the aid of the first priority. In another embodiment, the sequence is ascertained as a function of the first pieces of configuration information solely with the aid of the second priority.
In another embodiment, the direct access memory control unit is designed to carry out the following steps:
The transmission of the information blocks described in this way characterizes in the present case a mixed “Tx-operation” and “Rx-operation,” i.e., on the one hand, from the working memory to the communication module, and on the other hand, from the communication module to the working memory. Because invariably only one information block can be transmitted at a respective time on the bus system with the aid of the direct memory access, a prioritization for both transmission directions is advantageously carried out by the steps described. A prioritization also takes place within a respective transmission direction, as was described further above for the Tx-operation and the Rx-operation.
Thus, the direct memory access control unit is designed to ascertain the sequence for the Tx-operation on the one hand and the sequence for the Rx-operation on the other hand, and consequently also to carry out a prioritization between the Tx-operation and the Rx-operation. In other words: the direct access memory control unit gives priority to the information block that on the whole is most urgent.
Corresponding advantages result, as was described further above for the Tx-operation and for the Rx-operation. It is understood here that for the mixed Tx-operation and Rx-operation as well, the “additional” steps described separately above for the mixed Tx-operation and Rx-operation, respectively, may, to the extent applicable, be advantageously supplemented for the direct memory access control unit.
In another embodiment, the direct memory access control unit includes second pieces of configuration information, the second pieces of configuration information characterizing respective logical units communicating with the communication module and/or pieces of control information to be sent and/or to be received by the respective logical units. As a result, the ascertainment of the sequence can be advantageously improved. In one embodiment, the communication module is designed to be coupled with a CAN bus system, the aforementioned second pieces of configuration information each including respective CAN-IDs or CAN object identifiers. In another embodiment, the second pieces of configuration information include only the CAN-IDs required for the Rx-operation.
In another embodiment, the direct memory access control unit includes third pieces of configuration information, the third pieces of configuration information including variables which characterize the processing unit (or the processing units or processor cores) and/or the working memory (or the working memory units), for example, a so-called “CPU number.” The ascertainment of the sequence can be advantageously improved in this way as well. In another embodiment, the third pieces of configuration information include only the CPU numbers required for the Rx-operation.
In another embodiment, the direct memory access control unit includes fourth pieces of configuration information, the fourth pieces of configuration information characterizing a respective source and/or a respective target for the transmission of the information blocks. As a result, the information blocks can be transmitted into an associated buffer memory (“dedicated buffer”) or into a ring buffer memory (“ring buffer”) in the working memory (“system RAM”) or into a respective working memory unit (“local CPU RAM”) assigned to the processing unit. With the aid of configuration it is possible in this case to advantageously predefine a respectively required transmission type or a respective transmission target. This can affect, in particular, the Rx-operation.
In one embodiment, the direct memory access control unit is designed, in particular only, to carry out the Tx-operation. In another embodiment, the direct memory access control unit is designed, in particularly only, to carry out the Rx-operation.
In another embodiment, a direct memory access control unit is provided for a processing unit that includes a working memory, the direct memory access control unit including a terminal for connecting the direct memory access control unit to a bus system that connects the processing unit to the working memory, wherein the direct memory access control unit is designed to carry out the following steps: —reading in pieces of control information from at least two information blocks supplied by the communication module, which are provided by the communication module for transmission to the working memory, which is connected to the bus system, these pieces of control information characterizing a priority of the respective information block for the transmission to the working memory, —ascertaining a sequence for the transmission of the information blocks to the working memory as a function of the respective priority, —transmitting the information blocks from the communication module to the working memory according to the ascertained sequence using a direct memory access from the communication module to the working memory. Thus, this embodiment defines a data transmission in the Rx direction (i.e., from the communication module to the working memory), in particular, independently of a data transmission in the Tx direction, which is optionally also conceivable in additional variants of this embodiment.
The present invention further relates to a method for operating a direct memory access control unit for a processing unit that includes a working memory, the direct memory access control unit including a terminal for connecting the direct memory access control unit to a bus system that connects the processing unit to the working memory. The method in this case includes the following steps:
Comparable advantages result, as was described further above for the direct memory access control unit for the Tx-operation.
In one embodiment, the method includes at least one of the following steps:
Comparable advantages result, as was described above for the additional steps of the direct memory access control unit for the Tx-operation.
In another embodiment, the method includes the following steps:
Comparable advantages result, as was described above for the direct memory access control unit for the Rx-operation.
In another embodiment, the method includes at least one of the following steps:
Comparable advantages result, as was described above for the additional steps of the direct memory access control unit for the Rx-operation.
In another embodiment, the method includes the following steps:
Comparable advantages result, as was described further above for the direct memory access control unit for the mixed Tx-operation and Rx-operation. It is understood here that for the mixed Tx-operation and Rx-operation as well, the “additional” steps described separately above for the mixed Tx-operation and Rx-operation, respectively, may, to the extent applicable, be advantageously supplemented by the method.
In a particularly preferred example embodiment, it is possible to feature a gateway functionality with the aid of the direct memory access control unit. After a message is received in the communication module, the corresponding data are transmitted by the direct memory access control unit, for example, to the memory of the processing unit and are available there for the processing unit. The same data can also be advantageously further used for a transmission to other communication modules. This means, the data initially transmitted (Rx direction) in a first step by the direct memory access unit to the memory of the processing unit can be transmitted (Tx direction) in a second step by the direct memory access control unit to the same communication module and/or to other communication modules, in particular, MCAN modules, for dispatching to other users. In this case, it is conceivable to collect the Rx data from various CAN nodes and to mark only particular messages for further sending. According to one example embodiment, there is advantageously also the further possibility of sending out the messages at specific time intervals. A particular advantage of this example embodiment is that the gateway functionality operates without a controlling processing unit or CPU and as a result requires no additional performance.
Exemplary example embodiments of the present invention are explained below with reference to the drawings, in all of which the same reference numerals are used for functionally equivalent elements and variables, even in the case of different example embodiments.
Processing system 10 further includes direct memory access control unit 40 and communication module 50.
In one example embodiment, communication module 50 is designed to be operated with a processing unit 20, which includes only one processor core. In another example embodiment, communication module 50 is designed to be operated with multiple processor cores. Both example embodiments of communication module 50 can be alternatively used in processing system 10 of
Working memory 30 or working memory units 30_1, 30_2 through 30_n may, for example, be an “external” RAM, memory with random access, as in “random access memory,” or an “internal” RAM associated with processing unit 20 or processing units 20_1, 20_2, 20_n.
Processing unit 20, working memory units 30_1 through 30_n, direct memory access control unit 40 and communication module 50 are connected to one another via shared bus system 12 (see
The bus system can be designed, for example, as a parallel bus system having an address bus that includes a first number of address lines and a data bus that includes a second number of data lines.
The double arrows plotted in
Also plotted to the left in
Communication module 50 is designed to send and receive a potential plurality of information blocks 60, each of information blocks 60 being characterized by a specific priority, as will be explained in greater detail below. Communication module 50 is preferably connected to a plurality of data sources and/or data sinks (not depicted), which are able to communicate, for example, with communication module 50 via discrete lines or via one or multiple busses (not depicted).
Communication module 50 in the present case includes a so-called “MCAN module,” which is able to communicate with a CAN bus not depicted, to which a plurality of CAN bus users, referred to here as “logical units” are connected. The abbreviation “CAN” means “Controller Area Network.” The letter “M” characterizes a manufacturer-specific name affix.
The MCAN module or communication module 50 includes, for example, the following partial circuits, among other things:
Thus,
In one example embodiment, processing unit 20 and/or working memory 30 and/or direct memory access control unit 40 and/or a respective information block 60 is/are characterized by, among other things, the following essentially self-explanatory variables, pieces of control information and/or pieces of configuration information:
For a so-called “Tx-configuration”: CAN_ID(1 . . . n) Data ACK.
For a so-called “Rx-configuration”: CAN_ID(1 . . . n) Data NEW.
In one example embodiment, processing unit 20 and/or working memory 30 and/or direct access memory control unit 40 and/or a respective information block 60 is/are characterized by, among other things, the following essentially self-explanatory variables, pieces of control information and/or pieces of configuration information:
For the “Tx-configuration”:
SrcAddr Len TargetAddr Prio ID(1 . . . n) ACK Intern_TransSuccess
For the “Rx-configuration”:
SrcAddr Len TargetAddr ID(1 . . . n) CPUx New Intr.
with the following meanings:
SrcAddr—source address as a configuration,
Len—length as a configuration—how many bytes must be transmitted,
TargetAddr—target address as a configuration,
ID(1 . . . n)—ID of an Rx message as a configuration—necessary for deciding whether an interrupt is to be subsequently triggered to the CPU,
CPUx—Once the message has been received, the interrupt is triggered to the CPUx—configuration bit,
NEW—means the new data have been received—is set by the DMA and reset by the CPU,
Intr—interrupt—configuration bit, means trigger interrupt once the message has been received.
In one example embodiment, a respective priority is ascertained with the aid of a comparison of bit values, the bit values being characterized by a segment of the respective pieces of control information. The three bit sequences depicted below show an example. In this case, the bit sequences are compared bit by bit from left to right, a respective “0” being dominant over a respective “1”.
According to this example, the information block associated with bit sequence 3 would be transmitted first, then the information block associated with bit sequence 2, and thereafter the information block associated with bit sequence 1.
In one example embodiment, an ascertainment 110 of the sequence for the transmission of information blocks 60 to communication module 50 takes place in this case as a function of the first pieces of configuration information and of the respective first priorities and/or of the respective second priorities, the sequence optionally being ascertained as a function of respective first priorities (block 110a) or of respective second priorities (block 110b) or of respective first priorities and respective second priorities (block 110c).
In one example embodiment, an ascertainment 110 of the sequence for the transmission of information blocks 60 to communication module 50 takes place in this case as a function of the respective first priority if the respective first priorities are different, or as a function of the respective second priority if the respective first priorities are the same.
In one example embodiment, the ACK-bit received in block 102 in direct memory access control unit 40 is comparable to the ACK-bit of the acknowledgement signal sent in block 114.
To the extent logically possible and meaningful, the method steps described in
In one example embodiment, the method described in
In one example embodiment, direct memory access control unit 40 includes “second” pieces of configuration information, the second pieces of configuration information characterizing respective logical units communicating with communication module 50 and/or pieces of control information to be sent and/or to be received by the respective logical units. The second pieces of configuration information, for example, include all CAN-IDs required for the Rx-operation.
In one example embodiment, direct memory access control unit 40 includes “third” pieces of configuration information, the third pieces of configuration information including variables characterizing processing unit 20, 20_1 through 20_n (“CPU number”) and/or working memory 30, 30_1 through 30_n.
The method further includes:
It is further ascertained to which processing units 20_1 through 20_n or to which associated working memory unit 30_1 through 30_n a respective information block 60 is to be transmitted. Specifically, in one example embodiment, direct memory access control unit 40 includes fourth pieces of configuration information, the fourth pieces of configuration information characterizing a respective source and/or a respective target for the transmission of information blocks 60, see following block 211a.
The method includes:
To the extent logically possible and meaningful, the method steps described in
In one example embodiment, only the first priority is used for the method, which in the present case is ascertained directly from the CAN-ID. In one example embodiment, only the second priority is used for the method.
In one example embodiment, the first priority and the second priority are used for the method, the following steps (1) and/or (2) being carried out:
(1) ascertaining 210 the sequence for the transmission of information blocks 60 to working memory 30 as a function of the first pieces of configuration information and of the respective first priorities and/or respective second priorities, the sequence optionally ascertained as a function of respective first priorities (block 210a) or of respective second priorities (block 210b) or of respective first priorities and respective second priorities (block 210c), and
(2) ascertaining the sequence for the transmission of information blocks 60 to working memory 30 as a function of the respective first priority if the respective first priorities are different, or as a function of the respective second priority if the respective first priorities are the same.
In one example embodiment, the method described in
The third example embodiment for the method according to
| Number | Date | Country | Kind |
|---|---|---|---|
| 10 2016 203 307 | Mar 2016 | DE | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/EP2017/053901 | 2/21/2017 | WO | 00 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2017/148743 | 9/8/2017 | WO | A |
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| Number | Date | Country | |
|---|---|---|---|
| 20190050355 A1 | Feb 2019 | US |
