1. Field of Invention
The present invention relates to the DC to DC converters. More particularly, the present invention relates to pulse width modulation (PWM) DC to DC converters.
2. Description of Related Art
DC to DC converters are well known in the field of electronics. Such circuitry or devices are typically employed to convert from one DC voltage level to another DC voltage level. They are used in a variety of environments. For instance, several kinds of such converters are used to supply microprocessor core voltage. One kind of such converters is referred to as a fixed frequency converter, also known as a pulse-width modulated (PWM) converter. PWM converters include voltage mode converters and current mode converters.
As illustrated in
SR flip-lop 106 is triggered by a clock with a fixed frequency (e.g. 500 kHz). SR flop-flop 106 is reset when Vramp (rising from 0V to 5V) exceeds the level of Vea. The tuned-on time (Ton) of the power switch Q1 is from T0 (at the beginning of a new clock pulse) to T1 (when Vramp exceeds Vea). The turned-on time of the power switch Q2 is from T1 to T2 (at the beginning of another new clock pulse). When power switch Q1 is turned on, the inductor current (IL) increases with a slope of (Vin-Vout)/L. After power switch Q1 is turned off, power switch Q2 is turned on, and the inductor current (IL) decreases with a slope of (−Vout)/L.
The voltage mode PWM converter 100 generally requires a complicated feedback compensation design due to the double poles present in its output filter (comprising the inductor L and the output capacitor 112). However, no inductor current or load current information is found in the foregoing control loop. Any change of the load current can only be indicated by a change of the output voltage Vout when a higher or lower load current discharges the output capacitor 112 at a different rate. Major disadvantage of voltage mode is its slow response to load transients, owing to the compensation needed on error amplifier 102 to stabilize the control loop. And due to the lack of inductor current information, the voltage mode PWM converter 100 is not suitable for parallel operation. For example, two voltage mode PWM converters operating in parallel may have exactly the same duty cycles, yet one converter may carry a much larger portion of load current than the other converter.
However, a good current sense scheme is necessary for the current mode PWM converter 200, such as that achieved by a current-sense resistor or by sensing the on-state drain-source voltage of the power switch (commonly known as Rds current sensing). A discrete sensing resistor is expensive and introduces additional conduction loss. A high-side Rds sensing (on power switch Q1) suffers from short duty cycle and heavy switching noise, whereas a low-side Rds sensing (on power switch Q2) is out of phase with the turned-on time (Ton) of power switch Q1. The low-side Rds sensing thus generally requires a sample and hold circuit to be useful.
In many cases, because of the device parameter spread (such as Rds) and the current-sense amplifier input offset voltage, the extraction of inductor current information is significantly inaccurate. The current mode PWM converter 200 still requires an error amplifier 202 to derive an error voltage. Moreover, its compensation network, although simpler than that of the voltage mode PWM converter 100, still demands careful and elaborate design. In addition, for a multi-phase (parallel operation) design, each converter needs a separate current sensor, causing proportionally higher implementation cost.
As illustrated in
The ripple mode converter is inherently stable since it basically incorporates a bang-bang control scheme. Whenever the output voltage (Vout) falls outside of the regulation band, an instant correction quickly brings the output voltage (Vout) back into regulation. Moreover, the ripple mode converter has fast transient response, in which any error of the output voltage is corrected immediately within one stroke.
However, the switching frequency of the ripple mode converter is not constant. Moreover, if its output capacitor has a low ESR, the ripple of the output voltage (Vout) is very small, it will lead to jittery switching frequency. Further no inductor current (IL) information, neither the load current information, is contained in the regulation loop of the ripple mode converter. Therefore, when two converters are operated in parallel, one converter may carry a much larger portion of load current than the other converter. Consequently, ripple mode converters are generally considered as not suitable for multi-phase applications difficult.
It is therefore an aspect of the present invention to provide a DC to DC converter, which has a simple control circuit, is inherently stable, and is of fast transient response.
According to one preferred embodiment of the present invention, the DC to DC converter comprises an inverter, an inductor, a voltage sensor, a comparator, a clock generator, a driver, and an output capacitor. The inverter converts an input voltage into a square-wave voltage. The inductor is electrically connected to the output of the inverter. The voltage sensor is electrically connected to the inductor and derives a sense voltage. The comparator compares the sense voltage and a reference voltage. The clock generator generates a reference clock pulse train of constant frequency. The driver is triggered by the reference clock pulse and switches the inverter according to the output of the comparator.
According to another preferred embodiment of the present invention, the DC to DC converter comprises an inverter, an inductor, a sense resistor, an output capacitor, a comparator, and a driver. The inverter receives an input voltage and outputs a square-wave voltage. A first end of the inductor is electrically connected to an output of the inverter, A first end of the sense resistor is electrically connected to a second end of the inductor. A second end of the sense resistor is electrically connected to an output capacitor. The comparator compares a voltage positioned between the inductor and the sense resistor. The driver is triggered by a reference clock pulse and switches the inverter according to an output of the comparator.
According to another preferred embodiment of the present invention, the DC to DC converter comprises an inverter, an inductor, a sense resistor, a sense capacitor, a comparator and a driver. The inverter receives an input voltage and outputs a square-wave voltage. A first end of the inductor is electrically connected to an output of the inverter. A first end of the sense resistor is electrically connected to the first end of the inductor. A first end of the sense capacitor is electrically connected to a second end of the inductor, and a second end of the sense capacitor is electrically connected to a second end of the sense resistor. The comparator compares a voltage positioned between the sense capacitor and the sense resistor. The driver is triggered by a reference clock pulse and switches the inverter according to an output of the comparator.
It is to be understood that both the foregoing general description and the following detailed description are examples and are intended to provide further explanation of the invention as claimed.
These and other features, aspects and advantages of the present invention will become better understood with regard to the following description, appended claims and accompanying drawings where:
Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.
The present invention feeds back the output voltage (Vout) by a voltage sensor, which contains the information of the output voltage (Vout) as well as the inductor DC current. The DC to DC converter of the present invention has a constant switching frequency and supports a low ESR output capacitor. The control circuit of the DC to DC converter is simple, inherently stable, and has fast transient response. Furthermore, the DC to DC converter has inherent current-sharing characteristics, ideal for multi-phase applications, such as several converters operating in parallel.
The inverter 402 converts an input voltage (Vin) into a square-wave voltage. The inductor 404 is electrically connected to the output of inverter 402. Voltage sensor 406 is electrically connected to inductor 404 and derives a sense voltage (Vsen). Comparator 408 compares the sense voltage (Vsen) and a reference voltage (VREF). Clock generator 412 generates a reference clock pulse. Driver 414 is triggered by the reference clock pulse and switches inverter 402 according to the output of comparator 408.
More precisely, inverter 402 receives the input voltage and then outputs a square-wave voltage. Voltage sensor 406 of the preferred embodiment contains a sense resistor 406a. The first end of inductor 404 is electrically connected to the output of inverter 402, The first end of sense resistor 406a is electrically connected to the second end of inductor 404. Therefore, the sense voltage (Vsen) is derived between sense resistor 406a and inductor 404.
Moreover, driver 414 can be an SR latch, a flip-flop or other suitable driving circuit. The direct mode DC to DC converter 400 further comprises an output capacitor (Cout) 416, which is electrically connected between a second end of sense resistor 406a and the ground. Inverter 402 comprises two switches, such as power switches Q1 and Q2, which are electrically connected in series between the input voltage (Vin) and the ground. The two switches Q1 and Q2 are alternately switched and the output of inverter 402 is positioned between the two switches Q1 and Q2.
As illustrated in
In the next two cycles, power switch Q1 remains fully turned on until the sense voltage (Vsen) reaches the reference voltage (VREF) at T7. After T7, the direct mode DC to DC converter 400 operates in a new steady state where the voltage (VCout) of the output capacitor 416 is 50 mV below the reference voltage (VREF). Accordingly, the direct mode DC to DC converter 400 can be naturally stable and with fast dynamic response, which recovers optimally to regulation in the event of a load step change.
In short, the feedback point of the output voltage (Vout) is connected to the inductor side of a sense resistor 406a. The voltage at this feedback point contains both the output voltage (Vout) information and the inductor DC current information. Moreover, the direct mode DC to DC converter 400 requires only one comparator 408 without the need for any error amplifier or compensation network. Therefore it achieves all of the above stated goals. The only matter needing attention is that the DC regulation error is proportional to the load current multiplied by the current-sense resistance, By a proper minimization of current-sense resistance, the load regulation error can be controlled such that it is less than 1%.
More precisely, inverter 502 receives the input voltage and then outputs a square-wave voltage. Voltage sensor 506 of the preferred embodiment contains a sense resistor 506a and a sense capacitor 506b. The first end of inductor 504 is electrically connected to the output of inverter 502. The first end of sense resistor 506a is electrically connected to the first end of inductor 504. The first end of sense capacitor 506b is electrically connected to the second end of inductor 504, and the second end of sense capacitor 506b is electrically connected to the second end of sense resistor 506a. The sense voltage is derived between sense capacitor 506b and sense resistor 506a.
Preferably, the resistance Rs of sense resistor 506a, the capacitance Cs of sense capacitor 506b, and the inductance L and the DC resistance DCR of inductor 504 follows an equation as:
Rs×Cs=L/DCR (1)
Equation (1) describes a loss-less inductor current sense scheme. The stray resistance of inductor 504 can be incorporated together as a single resistor, the DC resistance (DCR). By matching Rs×Cs with L/DCR, it can be shown that the voltage drop on the DCR (i.e. IL×DCR) is duplicated as the voltage across sense capacitor 506b.
Moreover, driver 514 can be an SR latch, a flip-flop or other suitable driving circuit. Direct mode DC to DC converter 500 further comprises an output capacitor 516, which is electrically connected between the first end of sense capacitor 506b and the ground. Inverter 502 comprises two switches, such as power switches Q1 and Q2, which are electrically connected in series between the input voltage (Vin) and the ground. The two switches Q1 and Q2 are alternately switched and the output of inverter 502 is positioned between the two switches Q1 and Q2.
An error amplifier 518 is used to provide a reference voltage (Vref2) for comparator 508. The inverse input of an error amplifier 518 is electrically connected to the second end of inductor 504 and the output of error amplifier 518. The non-inverse input of error amplifier 518 is electrically connected to another reference voltage (Vref1). As long as error amplifier 518 has sufficient low-frequency gain, the output voltage (Vout) is regulated to the reference voltage (Vref1) regardless of the magnitude of the load current.
If each channel uses an inductor of the same size, its inductance L and DCR are equal to those of other channels. Furthermore, since all channels commonly share an output capacitor 612, they have the same equivalent series resistance (ESR) from the output capacitor 612. Consequently, each channel equally shares the load current. Moreover, the preferred embodiment has an automatically thermal balancing effect. For example, if one channel carries more current (due to lower DCR), then its inductor heats up more, making its DCR higher, which in turn, decreases its current
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.