DISABLED MODE ERROR REDUCTION FOR HIGH-VOLTAGE BILATERAL OPERATIONAL AMPLIFIER CURRENT SOURCE

Abstract

Provided are embodiments that include a circuit configured to operate in a disabled mode error reduction for high-voltage bilateral operational amplifier current source. The circuit includes an operational amplifier, and a switching circuit coupled to the operation amplifier, wherein the switching circuit is operable in a normal mode and a disabled mode, wherein the disabled mode reduces error current at the output of the operational amplifier. Also provided are embodiments for a method for operating a circuit in a disabled mode for error reduction.

Description

BACKGROUND

The present disclosure generally relates to circuits and more specifically to operating a high-voltage bilateral operational amplifier current source in a disabled mode for error reduction.

Operational amplifiers are used in a variety of applications. The operational amplifier is configured to receive a differential input and provided an output based on the difference between the two inputs. For example, operational amplifiers can be used as comparators to determine an outcome between voltage states. In addition, operational amplifiers can be operated to amplify a signal to obtain a particular gain according to a transfer characteristic. Because operational amplifiers are used in many applications, there may be a need to minimize any error or unwanted effects produced by the operational amplifier.

BRIEF DESCRIPTION

According to an embodiment, a circuit configured to operate in a disabled mode error reduction for high-voltage bilateral operational amplifier current source is provided. The circuit an operational amplifier, and a switching circuit coupled to the operation amplifier, wherein the switching circuit is operable in a normal mode and a disabled mode, wherein the disabled mode reduces error current at the output of the operational amplifier.

In addition to one or more of the features described herein, or as an alternative, further embodiments include a two-channel analog switch.

In addition to one or more of the features described herein, or as an alternative, further embodiments include a first channel of the switching circuit that is controlled to be connected to an inverting input of the operational amplifier and a second channel of the switching circuit that is controlled to be connected to a non-inverting input of the operational amplifier.

In addition to one or more of the features described herein, or as an alternative, further embodiments include a first channel of the switching circuit that is configured to receive a command voltage and a second channel of the switching circuit that is configured to receive a reference voltage.

In addition to one or more of the features described herein, or as an alternative, further embodiments include a first channel and a second channel of the switching circuit that are configured to be operated in the normal mode and the disabled mode.

In addition to one or more of the features described herein, or as an alternative, further embodiments include when operating in a disabled mode the first channel of the switching circuit is disconnected from the command signal and the second channel is disconnected from the reference signal and connected to a ground.

In addition to one or more of the features described herein, or as an alternative, further embodiments include a switching circuit that is controlled by an enable signal.

In addition to one or more of the features described herein, or as an alternative, further embodiments include a switching circuit that is operated in the normal mode when the enable signal is received.

According to an embodiment, a method for operating a circuit in a disabled mode for error reduction is provided. The method includes controlling a mode of a switching circuit, wherein the mode includes a normal mode and disabled mode wherein the disabled mode reduces an error current at an output of the operational amplifier, operating the operational amplifier based at least in part on the mode, wherein the operational amplifier is connected to the switching circuit.

In addition to one or more of the features described herein, or as an alternative, further embodiments include controlling a mode of the switching circuit that is capable switching the mode of the switching circuit, wherein the switching circuit is a two-channel analog switch.

In addition to one or more of the features described herein, or as an alternative, further embodiments include a first channel of the switching circuit that is controlled to be connected to an inverting input of the operational amplifier and a second channel of the switching circuit that is controlled to be connected to a non-inverting input of the operational amplifier.

In addition to one or more of the features described herein, or as an alternative, further embodiments include receiving a command voltage at the first channel of the switching circuit and receiving a reference voltage signal at the second channel of the switching circuit.

In addition to one or more of the features described herein, or as an alternative, further embodiments include a first channel and a second channel of the switching circuit are configured to be operated in the normal mode and the disabled mode.

In addition to one or more of the features described herein, or as an alternative, further embodiments include when operating in a disabled mode the first channel of the switching circuit is disconnected from the command signal and the second channel is disconnected from the reference signal and connected to a ground.

In addition to one or more of the features described herein, or as an alternative, further embodiments include operating a switching circuit is controlled by an enable signal.

In addition to one or more of the features described herein, or as an alternative, further embodiments include operating in the normal mode responsive to receiving the enable signal.

Technical effects of embodiments of the present disclosure include reducing the generation of unwanted current when the circuit is not in use.

The foregoing features and elements may be combined in various combinations without exclusivity, unless expressly indicated otherwise. These features and elements as well as the operation thereof will become more apparent in light of the following description and the accompanying drawings. It should be understood, however, that the following description and drawings are intended to be illustrative and explanatory in nature and non-limiting.

BRIEF DESCRIPTION OF THE DRAWINGS

The following descriptions should not be considered limiting in any way. With reference to the accompanying drawings, like elements are numbered alike:

FIG. 1 depicts a conventional operational amplifier configuration;

FIG. 2 depicts an operational amplifier in accordance with one or more embodiments of the invention; and

FIG. 3 depicts a representative circuit for the operational amplifier of FIG. 2 in accordance with one or more embodiments of the invention.

DETAILED DESCRIPTION

Operational amplifiers can be configured to incorporate an open-loop or a closed-loop architecture. When configured in an open-loop, the operational amplifier will act as a comparator. When operated in a closed-loop architecture, the output of the operational amplifier is fed back to an input of the amplifier which can be used to help control the gain produced by the operational amplifier.

Oftentimes, the operational amplifiers remain connected to the reference voltage and a command voltage whose error can be amplified when commanded to be zero. That is, the unwanted error can be amplified when the operational amplifier is not in use. The techniques described herein provide an architecture and method for operating the operational amplifier to substantially reduce the amplified error through the amplifier due to offset voltage. The offset voltage is an effective error voltage internal to the operational amplifier causing the two input terminals to deviate from an ideal differential voltage of zero. The error parameter can be substantial and detrimental for the high-voltage variety of operational amplifiers.

Now referring to FIG. 1, an operational amplifier configuration 100 is shown. The operational amplifier 110 is a high-voltage bilateral operational amplifier current source circuit. The operational amplifier 110 includes a non-inverting input (“+” input) and an inverting input (“−” input). The non-inverting input is coupled to the reference signal Vref through a serial resistor Rser_pos and the inverting input is coupled to the command signal Vcmd through a serial resistor Rser_neg. The inverting input receives feedback from the output of the operational amplifier 110 which is fed back over the resistor Rfb_neg. The non-inverting input receives a feedback signal from the output over the resistor Rfb_pos.

An output of the operational amplifier 110 that is provided to the load is shown as having a voltage V_o and an output resistance and current that is represented by R_o and I_o, respectively. The operational amplifier 110 is also coupled to the high voltage positive power supply (V_hv_pos) and the high voltage negative power supply (V_hv_neg).

The voltage reference “Vref” is a DC voltage reference with an amplitude halfway between the logic level supply voltage and ground. The output current I_o is controlled by the command signal provided to the inverting input of the operational amplifier 110. In some embodiments, the command signal is a voltage signal. A command voltage of zero volts sets the output current to a maximum positive current, a command voltage equal to the reference voltage sets the output to zero current, and a command voltage equal to the logic level supply voltage sets the output to maximum negative current. The command values in between these ranges scale the output current proportionally.

The topology provided in FIG. 1 can be used for application in which bipolar output current and large output voltage are necessary in order to source adequate drive current under all conditions. However, this circuit is subject to a large offset voltage error in the operational amplifier which contributes to the case where the drive could source or sink unacceptably large output current when the drive is meant to output zero current.

The techniques described herein provide operating the circuit in a disabled mode which has been added to a high-voltage bilateral operation amplifier current source circuit for the purpose of output error current reduction when the output is desired to be OFF.

Now referring to FIG. 2, a circuit architecture 200 for operating the operational amplifier in a disabled mode in accordance with one or more embodiments of the invention is shown. The circuit 200 includes an operational amplifier 210 similar to that shown in FIG. 1. The circuit 200 includes a two-channel analog switch 220 (hereinafter referred to as “analog switch 220”) that is coupled to the differential inputs of the operational amplifier 210.

The analog switch 220 can be controlled to be operated in the normal mode or the disabled mode. The analog switch 220 includes a first channel that is configured to connect the command signal (Vcmd) with an input of the operational amplifier 210 and the second channel that is configured to connect the reference signal (Vref) to the other input of the operational amplifier 210.

When operated in the disable mode, the analog switch 220 serves to open the command signal to the inverting side of the amplifier stage and ground the reference signal to the non-inverting side of the amplifier stage. This reconfigures the circuit to reduce feed-forward gain and eliminates common-mode voltage from being transferred from the reference input to the output by disconnecting the signals provided to the inputs of the operational amplifier 210.

In one or more embodiments, an enable signal (Enable) is provided to the analog switch 220 to operate the switch is operated in the normal mode. That is, the command input and the reference input is switched ON and connected to the respective inputs of the operational amplifier 210 when the Enable signal is provided. Responsive to the “ENABLE” signal being removed or deactivated the mode is switched to operate in the disabled mode which reduces the error current that is produced by the operational amplifier.

FIG. 3 depicts a model of the analog switch 220 of FIG. 2 with the resistor Rdis and the internal error of the amplifier which is represented by Vos. When operating in a normal mode the parameter Rdis is at 0 ohms and when configured in a disabled mode the parameter Rdis is open or infinite resistance. The following Equations provide a derivation of the output current I_o when the output current is commanded to be zero:

Vp=Vm

where v_m is the voltage applied to the inverting input of the operational amplifier and v_p is the voltage applied to the non-inverting input. Equation 1 provides the following:

$\begin{array}{cc}{V}_{\mathrm{os}}+V_o\left(\frac{{\mathrm{Rser}}_{\mathrm{pos}}}{{\mathrm{Rser}}_{\mathrm{pos}}+{\mathrm{Rfb}}_{\mathrm{pos}}}\right)=V_{\mathrm{oamp}}*\left(\frac{{\mathrm{Rser}}_{\mathrm{neg}}+\mathrm{Rdis}}{{\mathrm{Rser}}_{\mathrm{neg}}+\mathrm{Rdis}+{\mathrm{Rfb}}_{\mathrm{neg}}}\right)& \left(\mathrm{Eq}.1\right)\end{array}$

The amplifier output node Vo_amp is related to the output voltage “Vo” as shown in the following set of Equations:

$\begin{array}{cc}{I}_0=\frac{V_0}{R_0}=\frac{V_{0\mathrm{amp}}-V_0}{\mathrm{Rcs}}V_o*\left(\frac{1}{R_0}+\frac{1}{\mathrm{Rcs}}\right)=V_{\mathrm{oamp}}\left(\frac{1}{\mathrm{Rcs}}\right)v_{\mathrm{oamp}}=V_o*\left(1+\frac{\mathrm{Rcs}}{R_o}\right)& \left(\mathrm{Eq}.2\right)\end{array}$

Substituting Equation 2 into Equation 1, the following Equations are derived:

$V_{\mathrm{os}}+V_o\left(\frac{{\mathrm{Rser}}_{\mathrm{pos}}}{{\mathrm{Rser}}_{\mathrm{pos}}+{\mathrm{Rfb}}_{\mathrm{pos}}}\right)=V_o*\left(1+\frac{\mathrm{Rcs}}{R_o}\right)*\left(\frac{{\mathrm{Rser}}_{\mathrm{neg}}+\mathrm{Rdis}}{{\mathrm{Rser}}_{\mathrm{neg}}+\mathrm{Rdis}+{\mathrm{Rfb}}_{\mathrm{neg}}}\right)$ $V_{\mathrm{os}}=\left[\left(1+\frac{\mathrm{Rcs}}{R_o}\right)*\left(\frac{{\mathrm{Rser}}_{\mathrm{neg}}+\mathrm{Rdis}}{{\mathrm{Rser}}_{\mathrm{neg}}+\mathrm{Rdis}+{\mathrm{Rfb}}_{\mathrm{neg}}}\right)-\left(\frac{{\mathrm{Rser}}_{\mathrm{pos}}}{{\mathrm{Rser}}_{\mathrm{pos}}+{\mathrm{Rfb}}_{\mathrm{pos}}}\right)\right]$ $V_o=\frac{\mathrm{Vos}}{\left[\left(1+\frac{\mathrm{Rcs}}{R_o}\right)*\left(\frac{{\mathrm{Rser}}_{\mathrm{neg}}+\mathrm{Rdis}}{{\mathrm{Rser}}_{\mathrm{neg}}+\mathrm{Rdis}+{\mathrm{Rfb}}_{\mathrm{neg}}}\right)-\left(\frac{{\mathrm{Rser}}_{\mathrm{pos}}}{{\mathrm{Rser}}_{\mathrm{pos}}+{\mathrm{Rfb}}_{\mathrm{pos}}}\right)\right]}$

The output error current Io_{error_original} is derived when operating in the normal mode and is provided by the following Equation:

${\mathrm{Io}}_{\mathrm{error}\_\mathrm{original}}=\frac{V_{\mathrm{os}}}{R_o\left[\left(1+\frac{\mathrm{Rcs}}{R_o}\right)*\left(\frac{{\mathrm{Rser}}_{\mathrm{neg}}+\mathrm{Rdis}}{{\mathrm{Rser}}_{\mathrm{neg}}+\mathrm{Rdis}+{\mathrm{Rfb}}_{\mathrm{neg}}}\right)-\left(\frac{{\mathrm{Rser}}_{\mathrm{pos}}}{{\mathrm{Rser}}_{\mathrm{pos}}+{\mathrm{Rfb}}_{\mathrm{pos}}}\right)\right]}$

When “Rdis” is changed to an open circuit, a denominator ratio changes from a value less than one to a value of unity, which significantly reduces the output current induced due to the operational amplifier offset voltage:

${\mathrm{Io}}_{\mathrm{error}\_\mathrm{disabled}}=\frac{V_{0s}}{R_o\left[\left(1+\frac{\mathrm{Rcs}}{R_o}\right)-\left(\frac{{\mathrm{Rser}}_{\mathrm{pos}}}{{\mathrm{Rser}}_{\mathrm{pos}}+{\mathrm{Rfb}}_{\mathrm{pos}}}\right)\right]}$

In the following non-limiting example, a design using a high-voltage operational amplifier with a maximum offset voltage of 50 mV using 5 V logic designed for a maximum output current drive capability of 250 mA and a 100 Ω load is provided. Using the following parameters, Vos=50 mV; R0 =100 Ω; Rcs 5 Ω; Rser 100 kΩ; Rfb=50 kΩ; Vref=2.5 V; V_cmdMin=0 V; and V_cmdMax=5 V; the maximum and minimum output current are calculated as provided in the following calculations:

${\mathrm{Io}}_{\mathrm{enable}\max }=-\frac{\left(0-2.5\right)*\left(\frac{50k}{100k}\right)}{5}=250\mathrm{mA}$ ${\mathrm{Io}}_{\mathrm{enable}\min }=-\frac{\left(5-2.5\right)*\left(\frac{50k}{100k}\right)}{5}=-250\mathrm{mA}$

In addition, the normal mode current and disabled mode current results in the following:

Io_{error_original}=15 mA

Io_{error_disabled}=15 mA

The example provided above demonstrates a practical example in which the output error current is reduced from 15 mA to 1.3 mA, which is 8.7% of the original output error current.

The technical effects and benefits provide an efficient design and integrated circuit solution to reduce the output current when the “drive” should be off when operating in a disabled mode. Using the configuration described herein the operational amplifier is not enabled during a disabled mode and is not amplifying as large of an error caused by the offset voltage.

In addition, by implementing the analog switch 220, there is no requirement to use a switch at the output coupled to the load which would require a high voltage switch that is expensive, heavy and bulky to accomplish the disconnection of the input. The techniques describe controls the voltage with a 5 V power supply instead of using a high voltage switch design.

A detailed description of one or more embodiments of the disclosed apparatus and method are presented herein by way of exemplification and not limitation with reference to the Figures.

The term “about” is intended to include the degree of error associated with measurement of the particular quantity based upon the equipment available at the time of filing the application.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, element components, and/or groups thereof.

While the present disclosure has been described with reference to an exemplary embodiment or embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the present disclosure. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the present disclosure without departing from the essential scope thereof. Therefore, it is intended that the present disclosure not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this present disclosure, but that the present disclosure will include all embodiments falling within the scope of the claims.

Claims

1. A circuit configured to operate in a disabled mode error reduction for high-voltage bilateral operational amplifier current source, the circuit comprising: an operational amplifier; anda switching circuit coupled to the operation amplifier, wherein the switching circuit is operable in a normal mode and a disabled mode, wherein the disabled mode reduces error current at the output of the operational amplifier.

2. The circuit of claim 1, wherein the switching circuit is a two-channel analog switch.

3. The circuit of claim 2, wherein a first channel of the switching circuit is controlled to be connected to an inverting input of the operational amplifier and a second channel of the switching circuit is controlled to be connected to a non-inverting input of the operational amplifier.

4. The circuit of claim 3, wherein the first channel of the switching circuit is configured to receive a command voltage and a second channel of the switching circuit is configured to receive a reference voltage.

5. The circuit of claim 4, wherein the first channel and the second channel of the switching circuit are configured to be operated in the normal mode and the disabled mode.

6. The circuit of claim 5, wherein when in the disabled mode the first channel of the switching circuit is disconnected from the command signal and the second channel is disconnected from the reference signal and connected to a ground.

7. The circuit of claim 6, wherein the switching circuit is controlled by an enable signal.

8. The circuit of claim 7, wherein the switching circuit is operated in the normal mode when the enable signal is received.

9. A method for operating a circuit in a disabled mode for error reduction, the method comprising: controlling a mode of a switching circuit, wherein the mode comprises a normal mode and disabled mode wherein the disabled mode reduces an error current at an output of the operational amplifier,operating the operational amplifier based at least in part on the mode, wherein the operational amplifier is connected to the switching circuit.

10. The method of claim 9, wherein controlling the mode of the switching circuit comprises switching the mode of the switching circuit, wherein the switching circuit is a two-channel analog switch.

11. The method of claim 10, wherein a first channel of the switching circuit is controlled to be connected to an inverting input of the operational amplifier and a second channel of the switching circuit is controlled to be connected to a non-inverting input of the operational amplifier.

12. The method of claim 11, further comprises receiving a command voltage at the first channel of the switching circuit and receiving a reference voltage signal at the second channel of the switching circuit.

13. The method of claim 12, wherein the first channel and the second channel of the switching circuit are configured to be operated in the normal mode and the disabled mode.

14. The method of claim 13, wherein when in the disabled mode the first channel of the switching circuit is disconnected from the command signal and the second channel is disconnected from the reference signal and connected to a ground.

15. The method of claim 14, wherein the switching circuit is controlled by an enable signal.

16. The method of claim 15, further comprising operating in the normal mode responsive to receiving the enable signal.