The present invention relates generally to peripheral controllers for data storage. More particularly, it relates to enhancing synchronous I/O operations to disk-array controllers.
There is very great demand for high-speed stable storage. Disks provide stable storage, but latency and transfer times can be high.
Non-volatile random-access memory (NVRAM) can be use to improve performance in a number of ways to improve response time and data reliability in server appliances. NVRAM may consist of random-access memory that does not require power to retain data or Dynamic Random-Access Memory (DRAM) or Synchronous DRAM (SDRAM) that has secondary power such as battery or an external universal power supply (UPS).
One such prior-art application is shown in
This application allows the host computer 11 to directly control the NVRAM device 12, but it does not allow the NVRAM 19 to be used together efficiently with the disks 17. Data moving from NVRAM to disk must pass through the primary bus 13. This can reduce performance because the bus must be shared with other device transactions. Another disadvantage of this scheme is that NVRAM device 12 requires its own location on the primary bus 13 rather than sharing one with the controller for the disks 17. Locations on the bus often are not easily made available.
The solutions in
There are other prior art applications that utilize bus bridges. These bus bridges often include local memory that is a subset of the bridge.
Accordingly, it is an object of the present invention to provide NVRAM that may be fully controlled by the host computer.
Another object of the present invention is to provide NVRAM and disk controllers connected by private data paths while allowing each to run on its bus at as high a speed as possible.
Another object of the present invention is to provide NVRAM and disk controllers that may share a single connection to the host computer's primary bus.
The present invention combines NVRAM under control of the host computer with disk array controllers close to the NVRAM. Unlike many disk/RAID controllers that have a processor that takes control of the NVRAM, the present invention leaves the NVRAM to be used by the host. A plurality of private buses is used in the present invention to allow the host computer to program the NVRAM and disk array controllers to transfer data directly between themselves. Either the disk array controllers or the NVRAM controller may act as DMA masters.
A plurality of PCI bridges 304A, 304B, through 304N connects the various buses. The bridges are used to meet load requirements on each bus that limit the number of devices that may be attached to the bus. The bridges also may be used to connect buses of different technologies or different speeds. For example, some devices on the controller 302 may use the PCI 2.2 specification while others use the PCI-X 2.0 specification.
A plurality of disk-array controllers 310A, 310B, through 310N are attached to the plurality of PCI buses 307. In the preferred embodiment these are SCSI controllers or multi-port Serial ATA (SATA) controllers.
The DMA memory controller 308 manages the NVRAM 309. The NVRAM may consist of memory that requires no power to maintain data (such as magnetic memory), battery-backed SDRAM, or other RAM that uses external power. The preferred embodiment shown uses either power from the host computer 301 or rechargeable batteries 312, with a power regulator 311 managing the delivery of power to the NVRAM and to the battery recharge circuit.
The memory controller 308 includes DMA master capabilities that allow direct memory transfers between NVRAM 309 and host memory 315 or between NVRAM 309 and the plurality of disk array controllers 310 via one or more of the plurality of buses 307. The host computer 301 controls the NVRAM 309 and may program the DMA memory controller 308.
The NVRAM 309 may also be accessed as a target by either the host computer 301 or the disk array controllers 310. This allows NVRAM to be used as ordinary memory. Unlike cache on a disk or disk controller, this allows it to be accessed one byte at a time rather than in large blocks. The entire NVRAM may be mapped into the address space of the bus, though in the preferred embodiment only a window into NVRAM is mapped. A register in the NVRAM controller 308 determines which window is visible.
The host can use any method for caching data to NVRAM. The advantage of the present invention is being able to keep the host's cache close to the disk controllers. Because the host controls the cache, it can determine what data is to be cached, when the cached data is to move to or from the disk controllers, and when it can be freed.
Because the NVRAM cache appears to the host as ordinary memory, the host can access individual bytes of data in the cache. On the other hand, prior art disk-based cache must generally be accessed in blocks of 512 bytes or larger.
The preferred embodiment will include storing file system journals to NVRAM that are never transferred to disk. It will include storing file system changes in NVRAM in which the same data is modified frequently such as access time on files or changes associated with creating or deleting large numbers of files. The host computer will send these changes to disk less frequently, but the changes will be preserved in stable storage in the NVRAM. The preferred embodiment will include saving transactions in NVRAM even before processing is complete on incorporating the transactions into complex databases or other files. It will also include using NVRAM to create a checkpoint of data on disk, with all updates going only to NVRAM while the disk contents are copied such as when creating a backup.
The methods above are not by themselves new. The advantage of the present invention is that the host computer 301 is better able to make each of the decisions involved than the disk or disk controller. The host retains control of these decisions while having the convenience of having the data stored close to the disk controllers. Applying these methods to a host-controlled cache rather than a disk-controlled cache provides advantages in performance.
Priority is claimed under 35 U.S.C. § 119(e) to U.S. Provisional Patent Application No. 60/494,696, filed on Aug. 13, 2003, entitled “Memory Card and Related Methods for Using It” by Mike Jadon, which is incorporated by reference herein.
Number | Date | Country | |
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60494696 | Aug 2003 | US |