Disk drives comprise a read channel for processing the read signal emanating from the head in order to demodulate the data recorded on the disk surface. The read channel typically comprises a sampling device for sampling the read signal to generate a sequence of read signal samples, an equalizer comprising a plurality of coefficients for equalizing the read signal samples to generate a sequence of equalized samples, and a sequence detector for detecting an estimated data sequence from the equalized samples according to a target response. Any suitable target response may be employed, such as a suitable partial response (e.g., PR4, EPR4, etc.), and any suitable sequence detector may be employed (e.g., Viterbi, Turbo Decoder, etc.).
The accuracy of the sequence detector is affected by how well the read channel of the disk drive can be equalized to match the target response. Since the equalizer will correlate the noise in the read signal, the preferred response requires minimal equalization by the equalizer. There is, therefore, a need to optimize the target response of a sequence detector employed in a disk drive.
In the embodiment of
Any suitable sequence detector 16 may be employed in the embodiments of the present invention, such as a suitable Viterbi detector. In addition, the sequence detector 16 may operate according any suitable target response, such as a partial response (e.g., PR4, EPR4, EEPR4, etc.). The target values of the target response may be characterized by a suitable polynomial (e.g., 1-D2 for a PR4 response), wherein the coefficients of the polynomial may comprise any suitable values, including fractional values. In one embodiment, the target response may be configured initially according to a conventional polynomial (e.g., PR4), and then the coefficients of the polynomial are adapted (i.e., the target values of the target response are adapted) in a manner that minimizes a bit error rate of the sequence detector 16 as described below.
In one embodiment when simultaneously adapting the target values of the target response and the coefficients of the equalizer 12, the expected samples 24 are generated by convolving the training data sequence 11 with an ideal polynomial representation of the channel. The training data sequence may be prerecorded on the disk (e.g., using an external servo writer or stamping technique) or it may be written to the disk by the control circuitry 20. In another embodiment when adapting only the coefficients of the equalizer 12, the expected samples 24 may be generated by convolving the estimated data sequence 18 with an ideal polynomial representation of the channel. For example, in one embodiment the target values of the target response and the coefficients of the equalizer 12 may be adapted simultaneously during a calibration procedure using a training data sequence. Once the target values of the target response have converged, the target values remain static during normal operation of the disk drive (i.e., while reading user data) and the coefficients of the equalizer 12 may continue to be adapted by generating the expected samples 24 in response to the estimated data sequence 18.
In one embodiment of the present invention, the coefficients of the equalizer 12 and the target values of the target response are adapted by computing a gradient that attempts to minimize the bit error rate of the sequence detector 16. For example, in the embodiment wherein the sequence detector comprises a Viterbi detector, an error event occurs when:
where yk represents a sequence of equalized sample values, dk represents the correct sequence of expected sample values, and dki represents an alternative sequence of expected sample values. Therefore, the probability of a Viterbi detector making an error in the presence of an error event eai can be represented as:
The above equation for representing an error event can be expanded into:
Letting yk=dk+zk where zk consists of statistical noise and residual intersymbol interference (ISI). Also let dki=(ai*g)k and dk=(a*g)k where a is a NRZ input sequence and g represents the target values of the target response. With aki−ak=2·eaki, the above equation for representing an error event can be represented as:
Letting eyki=(eai*g)k the above equation can be written as:
Observe zk is a statistic quantity consisting of residual ISI and statistical colored noise. Assume the summation in the above equation accounts for N consecutive samples during the error event observation window, then the error-making condition becomes:
Define column vectors:
eyi=[ey0iey1iLeyN-1i]T and z=[z0z1LzN-1]T
then the above equation becomes:
eyi
Observe that eyi
to write the error event probability equation as:
Defining Rz=E{zzT} and the Viterbi pre-detection effective signal-to-noise ratio as ρ=M2/V the error event probability equation can be written as:
where:
For error event eaki with number λi of error bits in the pattern, the bit error occurrence probability is:
Pr(eai)=21-λ
Consider κ+1 number of dominant error events of eaki, the error event probability equation can be approximated as
From the above equation, the higher ρi the lower the probability of error. For a specific error event eaki, maximizing ρi means minimizing:
E=eyi
In one embodiment, the coefficients of the equalizer 12 and the target values of the target response are adapted in response to a gradient that minimizes the above E. Consider an example embodiment wherein the read channel comprises the dominant error events +, +−, +−+ and +0+, and the target response comprises the target values g=[g0 g1 g2]T, then the error event contributor eyi to E can be represented in the following table:
The noise correlation matrix Rz can be written as:
Using the above equations, it is possible to compute the gradient for each error event that minimizes E. For example, for the ‘+’ error event, E is computed as:
Computing
as the adaptation gradient Δwm for the wm coefficient:
The above equation can be rewritten as:
Therefore, in one embodiment, the wm coefficient is updated according to:
where m=0, 1, 2, L, N−1 and μ is the update gain.
Computing
as the adaptation gradient Δgn for the gn target value of the target response:
Therefore, in one embodiment, the gn target value of the target response is updated according to:
where n=1, 2 and η is the update gain, and ak is a training data sequence.
In one embodiment, the sign of the error values are used to compute the gradient in order to simplify the circuitry. In the above example for updating the wm coefficient for the ‘+’ error event, the above equation can be written as:
or equivalently:
In one embodiment, both the equalizer coefficients wm and the target values gn of the target response are adapted simultaneously, and in one embodiment, at least one of the equalizer coefficients and/or at least one of the target values is not adapted in order to minimize interaction between the two, thereby helping ensure the equalizer coefficients and target values converge. For example, in one embodiment the middle or main coefficient of the equalizer 12 is not adapted and/or the first target value of the target response is not adapted.
Any suitable control circuitry may be employed to implement the embodiments of the present invention, such as any suitable integrated circuit or circuits. For example, the control circuitry may be implemented within a read channel integrated circuit, or in a component separate from the read channel, such as a disk controller, or certain steps described above may be performed by a read channel and others by a disk controller. In one embodiment, the read channel and disk controller are implemented as separate integrated circuits, and in an alternative embodiment they are fabricated into a single integrated circuit or system on a chip (SOC). In addition, the control circuitry may include a suitable preamp circuit implemented as a separate integrated circuit, integrated into the read channel or disk controller circuit, or integrated into an SOC.
In one embodiment, the control circuitry comprises a microprocessor executing instructions, the instructions being operable to cause the microprocessor to perform the steps of the flow diagrams described herein. The instructions may be stored in any computer-readable medium. In one embodiment, they may be stored on a non-volatile semiconductor memory external to the microprocessor, or integrated with the microprocessor in a SOC. In another embodiment, the instructions are stored on the disk and read into a volatile semiconductor memory when the disk drive is powered on. In yet another embodiment, the control circuitry comprises suitable logic circuitry, such as state machine circuitry.
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