BACKGROUND
Disk drives comprise a disk and a head connected to a distal end of an actuator arm which is rotated about a pivot by a voice coil motor (VCM) to position the head radially over the disk. The disk comprises a plurality of radially spaced, concentric tracks for recording user data sectors and servo sectors. The servo sectors comprise head positioning information (e.g., a track address) which is read by the head and processed by a servo control system to control the actuator arm as it seeks from track to track.
FIG. 1 shows a prior art disk format comprising a number of servo sectors 6O-6N recorded around the circumference of the disk 2 that define a plurality of servo tracks 4, wherein data tracks are defined relative to the servo tracks (at the same or different radial density). Each servo sector 6, may comprise a preamble 8 for storing a periodic pattern, which allows proper gain adjustment and timing synchronization of the read signal, and a sync mark 10 for storing a special pattern used to symbol synchronize to a servo data field 12. The servo data field 12 stores coarse head positioning information, such as a track address, used to position the head over a target data track during a seek operation. Each servo sector 6, may further comprise groups of servo bursts 14 (e.g., A, B, C and D bursts), which comprise a number of consecutive transitions recorded at precise intervals and offsets with respect to a servo track centerline. The groups of servo bursts 14 provide fine head position information used for centerline tracking while accessing a data track during write/read operations.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a prior art disk format comprising a plurality of servo tracks defined by embedded servo sectors.
FIG. 2A shows a disk drive according to an embodiment comprising a head actuated over a disk.
FIG. 2B shows an embodiment of a sector comprising a periodic pattern (a preamble and/or postamble) and sector data.
FIG. 2C is a flow diagram according to an embodiment wherein the signal samples representing the periodic pattern are processed to measure a frequency induced phase error.
FIG. 3A shows control circuitry according to an embodiment including a timing recovery circuit for controlling a signal sampler.
FIG. 3B shows details of a timing recovery circuit according to an embodiment comprising a digital phase-locked loop (DPLL) adjusted by an integrated phase error and by the frequency induced phase error.
FIG. 3C shows control circuitry according to an embodiment for generating the frequency induced phase error.
FIG. 3D shows control circuitry according to an embodiment for measuring a phase estimate of a signal sample of the periodic pattern at signal sample index k.
DETAILED DESCRIPTION
FIG. 2A shows a disk drive according to an embodiment comprising a head 16 actuated over a disk 18 comprising a sector (FIG. 2B) including a periodic pattern (e.g., a preamble 20) and sector data 22. The disk drive further comprises control circuitry 24 operable to execute the flow diagram of FIG. 2C, wherein the sector is read with the head to generate a read signal (block 26) which is sampled at a sampling frequency with a signal sampler to generate signal samples (block 28). The signal samples representing the periodic pattern are processed to measure a frequency induced phase error based on kδ (block 30) where k represents a signal sample index and δ is a fraction of 2π. The signal samples representing the sector data are processed to generate a data phase error (block 32). The data phase error is adjusted in response to the frequency induced phase error to generate an adjusted data phase error (block 34), and the signal sampler is controlled in response to the adjusted data phase error (block 36).
In the embodiment of FIG. 2A, the disk 18 comprises a plurality of servo tracks 38 defined by servo sectors 400-40N, wherein data tracks are defined relative to the servo tracks at the same or different radial density. The data tracks are further divided into data sectors, wherein as shown in FIG. 2B the data and servo sectors may comprise a first periodic pattern 20 (e.g., a preamble), a sync mark 42, sector data 22, and a second periodic pattern 44 (e.g., a postamble). The control circuitry 24 processes a read signal 46 emanating from the head 16 to demodulate the servo sectors 400-40N and generate a position error signal (PES) representing an error between the actual position of the head and a target position relative to a target track. The control circuitry 24 filters the PES using a suitable compensation filter to generate a control signal 48 applied to a voice coil motor (VCM) 50 which rotates an actuator arm 52 about a pivot in order to actuate the head 16 radially over the disk 18 in a direction that reduces the PES. The servo sectors 400-40N may comprise any suitable head position information, such as a track address for coarse positioning and servo bursts for fine positioning. The servo bursts may comprise any suitable pattern, such as an amplitude based servo pattern (FIG. 1) or a phase based servo pattern.
FIG. 3A shows control circuitry according to an embodiment comprising a timing recovery circuit 54 operable to generate a sampling clock 56 applied to a signal sampler 58 in order to generate the signal samples 60. An equalizer filter 62 filters the signal samples 60 according to a desired response (e.g., a partial response), and the equalized signal samples 64 are processed by a sequence detector 66 to detect the data recorded on the disk. In one embodiment, the timing recovery circuit 54 generates the sampling clock 56 synchronous with the data rate of the recorded data so that the signal samples 60 are substantially synchronous with the data rate.
FIG. 3B shows a timing recovery circuit 54 according to an embodiment for generating the sampling clock 56 synchronous with the data rate. Signal samples 68 (which may be at the input or output of the equalizer filter 62) are input into a phase detector 70 for detecting a phase error 72 representing a difference between the actual phase of each signal sample 68 and an ideal phase. A loop filter 74 filters the phase error 72, and the output 76 of the loop filter 74 is integrated 78 to generate an integrated phase error 80 (representing the data phase error at block 32 of FIG. 2C). The integrated phase error 80 is used to phase interpolate 82 a reference clock 84 in order to adjust the phase of the sampling clock 56. Accordingly, the timing recovery circuit 54 of FIG. 3B implements a digital phase-locked loop (DPLL) that locks the frequency/phase of the sampling clock 56 onto the frequency/phase of the read signal. In the embodiment of FIG. 3B, the timing recovery circuit 54 comprises a zero-phase start block 86 which computes an initial phase error 88 of the sampling clock 56 relative to the signal samples 68. The initial phase error 88 is used to initialize the integrator 78 which reduces the convergence time of the DPLL.
In one embodiment, if there is a substantial frequency error between the frequency of the reference clock 84 and the data rate of the read signal, the timing recovery circuit 54 of FIG. 3B may be unable to lock onto the read signal. That is, the timing recovery circuit 54 may be unable to track the phase error induced by a substantial frequency error caused, for example, by a vibration perturbing the rotation frequency of the disk 18. Accordingly, in one embodiment a frequency induced phase error 90 is learned at block 92 of FIG. 3B while reading a periodic pattern of a sector (e.g., preamble 20), wherein the frequency induced phase error 90 is used to adjust the integrated phase error 80, thereby enabling the timing recovery circuitry 54 to lock onto the frequency/phase of the read signal.
In one embodiment, reading the periodic signal (e.g., preamble 20) of a sector results in a read signal in the form of a sine wave having a frequency f0. The sine wave may be sampled at a frequency (1+Δ)f0, where Δ represents the frequency error between the frequency of the sine wave and the frequency of the reference clock 84. The phase error (as a fraction of 2π) between f0 and the sampling frequency (1+Δ)f0 manifests as the accumulation of δ, where:
That is, the frequency induced phase error introduced at each signal sample is represented as δ, and therefore the total frequency induced phase error at any given signal sample index k is represented as kδ. Accordingly, in one embodiment the fraction δ is learned while reading the periodic pattern (e.g., preamble 20) of a sector, and then the fraction δ is used to generate the frequency induced phase error 90 for each signal sample of the sector data 22.
In one embodiment, when reading the periodic pattern (e.g., preamble 20) a phase estimate φk 94A of one of the signal samples 68 at index k is generated by computing a single frequency discrete Fourier transform (DFT) at frequency f0 using the control circuitry shown in FIG. 3D. The odd signal samples 96A are extracted and the even signal samples 96B are extracted from the signal samples 68. The odd/even signal samples are passed through a 1/1+D2 filter to accumulate the even/odd sequences as well as average out signal noise. A first block 98A processes the accumulated and filtered odd/even sequences Y1 and Y0 to estimate a phase φk 94A of the signal samples 68 at index k, and a second block 98B processes the accumulated and filtered odd/even sequences Y1 and Y0 to estimate a phase φk-1 94B of the signal samples 68 at index k−1.
If the preamble 20 comprises a 2T pattern, and there is no phase error or frequency error (Δ=0) when sampling the read signal 46, then the normalized amplitude of the signal samples representing the preamble 20 will be (++−−++−−++−− . . . ) and the change in phase between consecutive signal samples 68 will be 0.25 of 2π. The phase error φe(k) between two consecutive signal samples may therefore be represented as:
which is zero when the frequency error is zero (Δ=0). The above equation is computed at block 100 in FIG. 3C to generate a phase error φe(k) 102 at each signal sample index k. The instant contribution to the fraction δ 110 at signal sample index k may be represented as:
ξ(k)=φe(k)−φe(k−1)+(−1)k/2
The above equation is computed at block 104 of FIG. 3C to generate ξ(k) 106, and as each new signal sample 68 is processed, each new value ξ(k) 106 is integrated 108 which causes the fraction δ 110 to converge toward a steady state value. An accumulator 112 accumulates the fraction δ 110 to generate the frequency induced phase error kδ 90 at each signal sample index k.
In one embodiment, the integrator 108 of FIG. 3C is enabled by control signal 114 while reading the periodic pattern (e.g., preamble 20) of a sector, and disabled while reading the sync mark 42 and sector data 22. That is, the fraction δ 110 is learned (updated) while reading the periodic pattern (e.g., preamble 20), and then the learned fraction δ 110 is held constant while reading the sync mark 42 and sector data 22. In one embodiment, the control signal 114 may disable the integrator 108 when the head 16 approaches the end of the preamble 20 since the beginning of the sync mark 42 is unknown.
In one embodiment, the sector may comprise a postamble 44 as shown in FIG. 2B, wherein the fraction δ 110 may be further updated after reading the sector data 22. The sector may comprise a data sector of a data track, or a servo sector 40, of a servo track. In one embodiment, a first fraction δDATA may be learned for the data sectors of a data track, and a second fraction δSERVO may be learned for the servo sectors of a servo track. In one embodiment, during an access operation (write or read) after the head 16 settles onto the target data track, the periodic pattern (e.g., preamble 20) in a number of data sectors preceding the target data sectors may be processed in order to learn the fraction δ 110 prior to reaching the target data sectors of the access operation. When accessing the target data sectors, the fraction δ 110 may be further updated when reading the periodic pattern of each target data sector (e.g., preamble 20 and/or postamble 44). In this manner, the frequency induced phase error 90 is essentially removed from the phase error 72 of the DPLL, thereby enabling the DPLL to lock onto the read signal even in the presence of a substantial frequency error between the reference clock 84 and the data rate of the read signal.
In one embodiment, the signal sample index k is reset to zero by the zero-phase start block 86 of FIG. 3B each time the zero-phase start is computed at the beginning of a preamble 20. That is, after executing the zero-phase start, the frequency induced phase error 90 for the next signal sample of the preamble 20 is 1·δ, and for the next signal sample 2·δ, and so on. If there is an error in the fraction δ, it will manifest in the difference ζ(k) 106, and this error will eventually integrate to zero. Since ξ is a fraction of 2π, the accumulated fraction kδ will automatically reset when it exceeds 2π. When processing the first signal sample of the sync mark 42, the frequency induced phase error 90 will be generated based on kδ, where k represents the signal sample index relative to the signal sample index k=0 which is reset by the zero-phase start block 86.
Any suitable control circuitry may be employed to implement the flow diagrams in the above embodiments, such as any suitable integrated circuit or circuits. For example, the control circuitry may be implemented within a read channel integrated circuit, or in a component separate from the read channel, such as a disk controller, or certain operations described above may be performed by a read channel and others by a disk controller. In one embodiment, the read channel and disk controller are implemented as separate integrated circuits, and in an alternative embodiment they are fabricated into a single integrated circuit or system on a chip (SOC). In addition, the control circuitry may include a suitable preamp circuit implemented as a separate integrated circuit, integrated into the read channel or disk controller circuit, or integrated into a SOC.
In one embodiment, the control circuitry comprises a microprocessor executing instructions, the instructions being operable to cause the microprocessor to perform the flow diagrams described herein. The instructions may be stored in any computer-readable medium. In one embodiment, they may be stored on a non-volatile semiconductor memory external to the microprocessor, or integrated with the microprocessor in a SOC. In another embodiment, the instructions are stored on the disk and read into a volatile semiconductor memory when the disk drive is powered on. In yet another embodiment, the control circuitry comprises suitable logic circuitry, such as state machine circuitry.
The various features and processes described above may be used independently of one another, or may be combined in various ways. All possible combinations and subcombinations are intended to fall within the scope of this disclosure. In addition, certain method, event or process blocks may be omitted in some implementations. The methods and processes described herein are also not limited to any particular sequence, and the blocks or states relating thereto can be performed in other sequences that are appropriate. For example, described tasks or events may be performed in an order other than that specifically disclosed, or multiple may be combined in a single block or state. The example tasks or events may be performed in serial, in parallel, or in some other manner. Tasks or events may be added to or removed from the disclosed example embodiments. The example systems and components described herein may be configured differently than described. For example, elements may be added to, removed from, or rearranged compared to the disclosed example embodiments.
While certain example embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions disclosed herein. Thus, nothing in the foregoing description is intended to imply that any particular feature, characteristic, step, module, or block is necessary or indispensable. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions disclosed herein.
Patent Grant
8780470
