Disk drives comprise a disk and a head connected to a distal end of an actuator arm which is rotated about a pivot by a voice coil motor (VCM) to position the head radially over the disk. The disk comprises a plurality of radially spaced, concentric tracks for recording user data sectors and servo sectors. The servo sectors comprise head positioning information (e.g., a track address) which is read by the head and processed by a servo control system to control the velocity of the actuator arm as it seeks from track to track.
Because the disk is rotated at a constant angular velocity, the user data rate is typically increased toward the outer diameter tracks (where the surface of the disk is spinning faster) in order to achieve a more constant linear bit density across the radius of the disk. To simplify design considerations, the data tracks are typically banded together into a number of physical zones, wherein the user data rate is constant across a zone, and increased from the inner diameter zones to the outer diameter zones. This is illustrated in
The prior art disk format of
Each data track is typically divided into a number of data sectors for storing user data, wherein each data sector comprises a preamble and sync mark similar to the servo sectors. The sync mark enables the control circuitry to symbol synchronize to the user data after synchronizing timing recovery and gain control to the preamble. If the sync mark is corrupted by a defect on the disk, it may render the corresponding sector (servo or data) difficult or even impossible to recover. In some designs, if a servo sync mark is corrupted, the corresponding servo sector is typically ignored which can degrade performance of the servo system.
In the embodiment of
In one embodiment, each data track 32 in
The detected data sequence 40 is correlated with the target sync mark pattern 42 and the target data 44A and 44B using XNOR circuits, wherein the output of an XNOR circuit is 1 if a bit in the detected data sequence matches the corresponding bit in the target sync mark pattern or the target data. A first adder 46A sums the outputs of the target sync mark pattern XNOR circuits to generate a first correlation 48A, and a second adder 46B sums the outputs of the target data XNOR circuits to generate a second correlation 48B. A sync mark detector 50 biases the first correlation 48A relative to the second correlation 48B in order to detect the sector sync mark pattern in the detected data sequence 40. In other embodiments, the biasing may occur as part of one or more of the correlations, such as by scaling an output of each XNOR circuit used to correlate the target sync mark pattern 42 with the detected data sequence 40.
The sync mark detector 50 may bias the first correlation 48A relative to the second correlation 48B in any suitable manner. In an embodiment shown in
The first and second coefficients 52A and 52B as well as the threshold Th may comprise any suitable values (including fractional values) such that the first correlation 48A is given more weight relative to the second correlation 48B. In other embodiments, the coefficient values and a threshold Th may be selected such that the sector sync mark pattern is detected when there is more than one mismatched bit in the first correlation 48A. For example, if the first coefficient 52A is eight, the second coefficient 52B is two, and the threshold Th is seventy-nine, then the sector sync mark pattern is detected if eight of ten bits in the first correlation 48A match and all eight bits in the second correlation 48B match.
Any suitable control circuitry may be employed to implement the flow diagrams in the embodiments of the present invention, such as any suitable integrated circuit or circuits. For example, the control circuitry may be implemented within a read channel integrated circuit, or in a component separate from the read channel, such as a disk controller, or certain steps described above may be performed by a read channel and others by a disk controller. In one embodiment, the read channel and disk controller are implemented as separate integrated circuits, and in an alternative embodiment they are fabricated into a single integrated circuit or system on a chip (SOC). In addition, the control circuitry may include a suitable preamp circuit implemented as a separate integrated circuit, integrated into the read channel or disk controller circuit, or integrated into an SOC.
In one embodiment, the control circuitry comprises a microprocessor executing instructions, the instructions being operable to cause the microprocessor to perform the steps of the flow diagrams described herein. The instructions may be stored in any computer-readable medium. In one embodiment, they may be stored on a non-volatile semiconductor memory external to the microprocessor, or integrated with the microprocessor in a SOC. In another embodiment, the instructions are stored on the disk and read into a volatile semiconductor memory when the disk drive is powered on. In yet another embodiment, the control circuitry comprises suitable logic circuitry, such as state machine circuitry.
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