Disk drives comprise a disk and a head connected to a distal end of an actuator arm which is rotated about a pivot by a voice coil motor (VCM) to position the head radially over the disk. The disk comprises a plurality of radially spaced, concentric tracks for recording user data sectors and servo sectors. The servo sectors comprise head positioning information (e.g., a track address) which is read by the head and processed by a servo control system to control the actuator arm as it seeks from track to track.
Data is typically written to data sectors within a data track by modulating the write current of a write element, for example, using a non-return to zero (NRZ) signal, thereby writing magnetic transitions onto the disk surface. A read element (e.g., a magnetoresistive (MR) element) is then used to transduce the magnetic transitions into a read signal that is demodulated by a read channel. The recording and reproduction process may be considered a communication channel, wherein communication demodulation techniques may be employed to demodulate the read signal.
When reading data from the disk, a read channel typically samples the read signal to generate read signal samples that are equalized according to a target response (e.g., a partial response). A sequence detector (e.g., a Viterbi detector) detects an estimated data sequence from the equalized samples, and errors in the estimated data sequence are corrected, for example, using a Reed-Solomon error correction code (ECC) or using a Low Density Parity Check (LDPC) code.
It is typically desirable to measure the performance of the disk drive in terms of bit error rate in order to qualify each disk drive as acceptable and/or calibrate various parameters of each disk drive (e.g., by selecting a data density or calibrating read channel parameters). Since the bit error rate of a Reed-Solomon ECC or LDPC decoder is typically very low, the prior art has suggested to margin the read channel during the quality test and or calibration procedures by adding random noise to the read signal or enhancing random noise in the read signal.
In the embodiment of
The estimated noise sequence 66 may be used for any suitable purpose in various different embodiments. For example, the estimated noise sequence 66 may be evaluated to characterize and/or verify the quality of the recording channel, such as the quality of the magnetic media and/or the quality of the head 16. In another embodiment the estimated noise sequence 66 may be evaluated to detect defects on the disk 18 which may be mapped out. In yet another embodiment, the estimated noise sequence 66 may be used to amplify the noise in the read signal samples in order to evaluate the performance of the sequence detector 70, and/or calibrate parameters of the read channel, such calibrate coefficients of the equalizer 24 and/or calibrate parameters of the detector 70. This embodiment is understood with reference to
Any suitable technique may be employed to identify the response of the read channel at the input of the equalizer 24.
In one embodiment, the coefficients of the response filter 82 are adapted according to:
where ĥi represents the coefficients of the response filter, x[n] represents the read signal samples 60, and {circumflex over (x)}[n] represents the output 86 of the response filter 82. The coefficients of the response filter are adapted until the above equation reaches a minimum. In one embodiment, the solution to the above equation can be derived using a Weiner filter solution for n=−∞ to +∞. In another embodiment, the Wiener filter solution can be simplified to a least mean squares (LMS) solution by considering only the error e[n] for the current signal sample such that the coefficients of the response filter may be updated according to:
ĥi[n+1]=ĥi[n]+2μ(e[n])(s[n−i])
where e[n] represents the error signal 84, s[n−i] represents the test pattern 54, and μ is a step size.
Any suitable control circuitry may be employed to implement the flow diagrams in the above embodiments, such as any suitable integrated circuit or circuits. For example, the control circuitry may be implemented within a read channel integrated circuit, or in a component separate from the read channel, such as a disk controller, or certain operations described above may be performed by a read channel and others by a disk controller. In one embodiment, the read channel and disk controller are implemented as separate integrated circuits, and in an alternative embodiment they are fabricated into a single integrated circuit or system on a chip (SOC). In addition, the control circuitry may include a suitable preamp circuit implemented as a separate integrated circuit, integrated into the read channel or disk controller circuit, or integrated into a SOC.
In one embodiment, the control circuitry comprises a microprocessor executing instructions, the instructions being operable to cause the microprocessor to perform the flow diagrams described herein. The instructions may be stored in any computer-readable medium. In one embodiment, they may be stored on a non-volatile semiconductor memory external to the microprocessor, or integrated with the microprocessor in a SOC. In another embodiment, the instructions are stored on the disk and read into a volatile semiconductor memory when the disk drive is powered on. In yet another embodiment, the control circuitry comprises suitable logic circuitry, such as state machine circuitry.
As will be apparent, many variations on the systems and methods described above are possible. For example, while the above disclosure has described processes as performed for “each” sector, zone or other disk portion, in some cases, the processes may be performed for only one or some of the disk portions and not necessarily for each of the disk portions.
The various features and processes described above may be used independently of one another, or may be combined in various ways. All possible combinations and subcombinations are intended to fall within the scope of this disclosure. In addition, certain method, event or process blocks may be omitted in some implementations. The methods and processes described herein are also not limited to any particular sequence, and the blocks or states relating thereto can be performed in other sequences that are appropriate. For example, described tasks or events may be performed in an order other than that specifically disclosed, or multiple may be combined in a single block or state. The example tasks or events may be performed in serial, in parallel, or in some other manner. Tasks or events may be added to or removed from the disclosed example embodiments. The example systems and components described herein may be configured differently than described. For example, elements may be added to, removed from, or rearranged compared to the disclosed example embodiments.
While certain example embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions disclosed herein. Thus, nothing in the foregoing description is intended to imply that any particular feature, characteristic, step, module, or block is necessary or indispensable. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions disclosed herein.
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