Disk drives comprise a disk and a head connected to a distal end of an actuator arm which is rotated about a pivot by a voice coil motor (VCM) to position the head radially over the disk. The disk comprises a plurality of radially spaced, concentric tracks for recording user data sectors and servo sectors. The servo sectors comprise head positioning information (e.g., a track and wedge address) which is read by the head and processed by a servo control system to control the actuator arm as it seeks from track to track as well as establish rotational position of the head.
In the embodiment of
During an access operation (write/read), the control circuitry 28 seeks the head 26 to a target data track, and then tracks a centerline of the data track in response to the servo sectors 200-20N. In order to demodulate a servo sector 20i, the control circuitry 28 opens a servo gate, and in an embodiment illustrated in
In the embodiment of
In one embodiment, the timing recovery circuit 32 generates the sampling clock 58 synchronous to the data rate of the servo data (i.e., the analog signal 60 is sampled synchronously). Accordingly in this embodiment the servo preamble 22 is processed in order to initially synchronize the timing recovery circuit 32 prior to reading the servo data 24. In one embodiment, the timing recovery circuit 32 executes a zero-phase start operation wherein the phase of a phase-locked loop (PLL) is initialized based on the first few signal samples of the servo preamble 22. Once the phase of the PLL has been initialized, the remaining signal samples of the servo preamble 22 are processed to further lock the PLL to the frequency/phase of the servo preamble 22. Accordingly, in one embodiment the control circuitry 28 enables the servo read gate (
At least some of the components of the servo read channel shown in
Any suitable data 40 may precede the servo preamble 22 in
In one embodiment, the data 40 that precedes the servo preamble 22 in
Any suitable control circuitry may be employed to implement the flow diagrams in the above embodiments, such as any suitable integrated circuit or circuits. For example, the control circuitry may be implemented within a read channel integrated circuit, or in a component separate from the read channel, such as a disk controller, or certain operations described above may be performed by a read channel and others by a disk controller. In one embodiment, the read channel and disk controller are implemented as separate integrated circuits, and in an alternative embodiment they are fabricated into a single integrated circuit or system on a chip (SOC). In addition, the control circuitry may include a suitable preamp circuit implemented as a separate integrated circuit, integrated into the read channel or disk controller circuit, or integrated into a SOC.
In one embodiment, the control circuitry comprises a microprocessor executing instructions, the instructions being operable to cause the microprocessor to perform the flow diagrams described herein. The instructions may be stored in any computer-readable medium. In one embodiment, they may be stored on a non-volatile semiconductor memory external to the microprocessor, or integrated with the microprocessor in a SOC. In another embodiment, the instructions are stored on the disk and read into a volatile semiconductor memory when the disk drive is powered on. In yet another embodiment, the control circuitry comprises suitable logic circuitry, such as state machine circuitry.
The various features and processes described above may be used independently of one another, or may be combined in various ways. All possible combinations and subcombinations are intended to fall within the scope of this disclosure. In addition, certain method, event or process blocks may be omitted in some implementations. The methods and processes described herein are also not limited to any particular sequence, and the blocks or states relating thereto can be performed in other sequences that are appropriate. For example, described tasks or events may be performed in an order other than that specifically disclosed, or multiple may be combined in a single block or state. The example tasks or events may be performed in serial, in parallel, or in some other manner. Tasks or events may be added to or removed from the disclosed example embodiments. The example systems and components described herein may be configured differently than described. For example, elements may be added to, removed from, or rearranged compared to the disclosed example embodiments.
While certain example embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions disclosed herein. Thus, nothing in the foregoing description is intended to imply that any particular feature, characteristic, step, module, or block is necessary or indispensable. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions disclosed herein.
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