Patent Application
20080001562
The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which:
The demonstrable need for an evolved approach to spin-downs is illustrated by way of the graphs in
Accordingly,
In accordance with at least one presently preferred embodiment of the present invention, there is additionally provided a dedicated spin-down device driver 112 in communication with OS 110 which concertedly manages spin-downs of HDD 102 and motor 104 in a manner now to be described. This driver 112 is preferably configured to control a cache management protocol or software component 114 whereby, within the main memory 116 of the computer 100, a dedicated spin-down cache 118 is created. Spin-down device driver 112 is preferably in communication with HDD device driver 108, in a manner that will be appreciated, such that the former acts to manage the cache 118 at appropriate times and instances.
Essentially, cache 118 can take over command operations during low activity periods and can thus act as a buffer (effectively between HDD 102 and OS 110) to permit HDD 102 to go “unaccessed” for significant periods of time. Accordingly, this would permit spin-down times that should prove to be more than sufficient for prolonging HDD motor life as previously discussed. As such, cache management 114 is preferably configured such that the actual spin-down and spin-up of motor 104 can be concertedly and “smartly” controlled through IDE interface 106. The manner of controlling spin-down and spin-up can follow essentially any suitable or desired protocol but, in a preferred embodiment of the present invention, will be based on a relationship between cache miss activity and HDD activity. More particularly, spin-downs can be managed and controlled on the basis of historical spin down activity (e.g., within a predetermined time period) and/or general historical system activity or operation.
Management of cache 118 preferably proceeds such that, in essence, disk write activity is reduced. More particularly, all writes to HDD 102 are preferably “caught” by cache 118 and temporarily stored. Preferably, any reads from HDD 102 will be “checked” with cache 118 to determine if data is available without accessing the drive 102. In the case of a cache miss, the hard disk drive 102 would be spun up to retrieve data, which is then preferably stored in cache 118 to increase the potential of future cache hits. Read-ahead algorithms and other cache techniques to improve the hit percentage can also be utilized.
Spin-down times can vary but it is generally recognized that within a 24-hour period, 10 minutes total of spin-down is sufficient for prolonging motor life and avoiding the problems discussed previously.
Generally, by implementing a cache between a hard drive and the operating system as discussed, it is possible to drastically reduce hard drive traffic generated by low I/O, background applications. This result, combined with actively controlling the spin-up/spin-down capability of the hard drive 102, allows for long periods of motor spin down from what would have originally been 24×7 applications.
In a particularly preferred embodiment of the present invention, spin-downs are not managed by driver 112 and management protocol 114 haphazardly, but take into account current and historical spin-down or general activity, and weighing this against the total amount of time that the HDD 102 has been spun down within a predetermined (e.g., 24 hour) period. In this manner, excessive “thrashing” (i.e., frequent switches between spin-up and spin-down) can be avoided, to thus help minimize overall wear on motor 104.
It is to be understood that the present invention, in accordance with at least one presently preferred embodiment, includes elements which may be implemented on at least one general-purpose computer running suitable software programs. These may also be implemented on at least one Integrated Circuit or part of at least one Integrated Circuit. Thus, it is to be understood that the invention may be implemented in hardware, software, or a combination of both.
If not otherwise stated herein, it is to be assumed that all patents, patent applications, patent publications and other publications (including web-based publications) mentioned and cited herein are hereby fully incorporated by reference herein as if set forth in their entirety herein.
Although illustrative embodiments of the present invention have been described herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be affected therein by one skilled in the art without departing from the scope or spirit of the invention.
