BACKGROUND
Disk drives comprise a disk and a head connected to a distal end of an actuator arm which is rotated about a pivot by a voice coil motor (VCM) to position the head radially over the disk. The disk comprises a plurality of radially spaced, concentric tracks for recording user data sectors and servo sectors. The servo sectors comprise head positioning information (e.g., a track address) which is read by the head and processed by a servo control system to control the actuator arm as it seeks from track to track.
FIG. 1 shows a prior art disk format 2 as comprising a number of servo tracks 4 defined by servo sectors 60-6N recorded around the circumference of each servo track. Each servo sector 6i comprises a preamble 8 for storing a periodic pattern, which allows proper gain adjustment and timing synchronization of the read signal, and a sync mark 10 for storing a special pattern used to symbol synchronize to a servo data field 12. The servo data field 12 stores coarse head positioning information, such as a servo track address, used to position the head over a target data track during a seek operation. Each servo sector 6i further comprises groups of servo bursts 14 (A,B,C,D in the example shown), which are recorded with precise intervals and offsets relative to the servo track centerlines. The servo bursts 14 provide fine head position information used for centerline tracking while accessing a data track during write/read operations.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a prior art disk format comprising a plurality of servo tracks defined by embedded servo sectors.
FIG. 2A shows a disk drive according to an embodiment comprising a head actuated over a disk.
FIG. 2B is a flow diagram according to an embodiment wherein data comprising a first periodic pattern, a payload, and a second periodic pattern is written to and read from the disk, and the payload samples adjusted based on a phase error between the first and second periodic patterns.
FIG. 2C shows an embodiment wherein the written data comprises a preamble (first periodic pattern), a sync mark, a payload, and a postamble (second periodic pattern).
FIG. 3A shows control circuitry according to an embodiment comprising a frequency synthesizer for generating an asynchronous sampling clock, and a phase error detector operable to detect a phase error between the first and second periodic patterns.
FIG. 3B illustrates an example wherein the sampling frequency matches the rotation frequency of the disk, and therefore there is no phase error between the first and second periodic patterns.
FIG. 3C illustrates an example wherein an error between the sampling frequency and the rotation frequency of the disk results in a phase error between the first and second periodic patterns.
FIG. 4 is a flow diagram according to an embodiment wherein the asynchronous signal samples of the payload are upsampled and processed to compensate for the frequency error between the sampling frequency and the rotation frequency of the disk.
DETAILED DESCRIPTION
FIG. 2A shows a disk drive according to an embodiment comprising a head 16 actuated over a disk 18, and control circuitry 20 operable to execute the flow diagram of FIG. 2B. Data is written to the disk (FIG. 2C) comprising a first periodic pattern 21 (e.g., a preamble), a payload 23, and a second periodic pattern 25 (e.g., a postamble) (block 22). The data is first read from the disk to generate a first read signal (block 24), and the first read signal is sampled asynchronously to generate first asynchronous signal samples (block 26). The first asynchronous signal samples representing the first periodic pattern are processed to measure a first phase (block 28), and the first asynchronous signal samples representing the second periodic pattern are processed to measure a second phase (block 30). A first phase error is generated based on a difference between the first phase and the second phase (block 32). The first asynchronous signal samples representing the payload are adjusted in response to the first phase error to generate first adjusted asynchronous signal samples (block 34).
In the embodiment of FIG. 2A, a plurality of concentric servo tracks 36 are defined by embedded servo sectors 380-38N, wherein a plurality of concentric data tracks are defined relative to the servo tracks 36. The control circuitry 20 processes a read signal 40 emanating from the head 16 to demodulate the servo sectors and generate a position error signal (PES) representing an error between the actual position of the head and a target position relative to a target track. The control circuitry 20 filters the PES using a suitable compensation filter to generate a control signal 42 applied to a voice coil motor (VCM) 44 which rotates an actuator arm 46 about a pivot in order to actuate the head 16 radially over the disk 18 in a direction that reduces the PES. The servo sectors may comprise any suitable head position information, such as a track address for coarse positioning and servo bursts for fine positioning. The servo bursts may comprise any suitable pattern, such as an amplitude based servo pattern (FIG. 1) or a phase based servo pattern.
The payload 23 in FIG. 2C may represent any suitable data, wherein in one embodiment the payload 23 comprises a test pattern written to the disk during a diagnostic or calibration procedure of the disk drive. For example, in one embodiment a test pattern may be written to and read from the disk in order to evaluate the performance characteristics of a component, such as the performance characteristics of the head 16. As an example, it may be desirable to evaluate a stability characteristic of a magnetoresistive read element of the head 16 by reading the test pattern from the disk and evaluating a non-repeatable signal noise in the read signal. That is, the non-repeatable signal noise may be indicative of head instability which is a random phenomena whereas repeatable signal noise is typically caused by fixed anomalies, such as defects on the disk or tracking errors due to written-in errors in the servo sectors. In order to adequately test a component of the disk drive, it may be desirable to write a test pattern comprising one or more frequencies that have little or no timing recovery information. For example, it may be desirable to write a DC test pattern to the disk in order to evaluate the non-repeatable signal noise in the read signal. In one embodiment, sampling the read signal asynchronously and performing timing recovery using the preamble 21 and postamble 25 (rather than over the payload 23) enables the test pattern to be written with any desirable frequency components.
In another embodiment, the payload 23 in FIG. 2C may comprise user data of an unrecoverable data sector encountered during a read operation. During a retry read operation, the data sector may be read and the read signal sampled asynchronously. The preamble of the unrecoverable data sector may be processed as the first periodic pattern 21, and the preamble of the following data sector may be processed as the second periodic pattern 25 in order to compensate for the frequency error in the signal samples. That is, the preamble of a following data sector may be used as a postamble to an unrecoverable data sector during a retry operation.
FIG. 3A shows control circuitry according to an embodiment wherein a frequency synthesizer 48 generates a sampling clock 50 for sampling the read signal 40 asynchronously to generate asynchronous signal samples 52. In one embodiment, the sampling clock 50 is generated at the same frequency used to write the payload 23 to the disk 18; that is, the frequency synthesizer 48 applies the sampling clock 50 to a preamp 54 during the write operation so that the payload 23 is written to the disk 18 at a target frequency. If when reading the payload 23 the disk is rotating at the same frequency as when the payload 23 was written, then there will be no frequency error between the sampling clock 50 and the rotation frequency of the disk. Consequently, there will be no phase error between the signal samples of the preamble 21 and the signal samples of the postamble 25 as illustrated in FIG. 3B. However, if when reading the payload 23 the disk is rotating at a different frequency as when the payload 23 was written, then the frequency error will induce a phase error between the signal samples of the preamble 21 and the signal samples of the postamble 25 as illustrated in FIG. 3C. Accordingly in the embodiment of FIG. 3A, a phase error detector 56 processes the asynchronous signal samples 52 to detect the phase error 58 between the postamble 25 and the preamble 21. The phase error 58 is then used at block 60 to adjust the asynchronous signal samples representing the payload 23.
In one embodiment, the data written to the disk at block 22 of FIG. 2B is read multiple times to generate a plurality of buffered asynchronous signal samples representing the payload 23. After adjusting for the frequency error in each of the buffered sequences (and in one embodiment a phase error between the sequences), the sequences are amplitude normalized and averaged to generate a nominal sequence. A difference between the nominal sequence and each frequency/phase adjusted sequence is generated in order to extract the non-repeatable signal noise from each sequence, wherein the non-repeatable signal noise may indicate a faulty component, such as a faulty head.
This embodiment is understood with reference to the flow diagram of FIG. 4 which extends on the flow diagram of FIG. 2B, wherein after generating the phase error (block 32) during a first read of the data, the asynchronous signal samples are upsampled by at least ten times (block 62). In one embodiment, upsampling the asynchronous signal samples may be achieved using a suitable interpolation algorithm. The frequency error in the signal samples of the payload 23 is then compensated based on the measured phase error (block 64). In one embodiment, the frequency error is compensated by upsampling or decimating the upsampled asynchronous signal samples depending on the polarity of the frequency error.
When the phase error indicates the frequency error is negative (meaning that the frequency of the signal samples is too low relative to the data written on the disk), then the frequency error is compensated by further upsampling the upsampled asynchronous signal samples. The upsampling may be implemented in any suitable manner and with any suitable resolution relative to the magnitude of the phase error. In one embodiment, the upsampling is implemented by dividing the phase error into a number of signal sample periods, and then inserting an interpolated signal sample into the upsampled asynchronous signal samples at a corresponding interval. For example, consider the simple example where the upsampled asynchronous signal samples comprise 1100 samples, and the phase error spans 10 signal sample periods. An interpolated signal sample may be inserted into the upsampled asynchronous signal samples every 100 samples in order to compensate for the frequency error.
When the phase error indicates the frequency error is positive (meaning that the frequency of the signal samples is too high relative to the data written on the disk), then the frequency error is compensated by decimating the upsampled asynchronous signal samples. In the above example where the upsampled asynchronous signal samples comprise 1100 samples, and the phase error spans 10 signal sample periods, a signal sample may be decimated (removed) from the upsampled asynchronous signal samples every 100 samples in order to compensate for the frequency error.
The flow diagram of FIG. 4 is repeated at block 66 in order to reread the data from the disk and generate multiple of the upsampled, frequency compensated asynchronous signal samples representing the payload 23. During each read operation, the rotation frequency of the disk may be slightly different and therefore the resulting frequency error may be slightly different. In addition, the start of each read operation may vary slightly resulting in a global phase error in the signal samples relative to each read operation. Accordingly, in one embodiment after compensating for the frequency error in each sequence of signal samples representing each read operation, the global phase error is compensated by phase aligning the upsampled sequences (block 68). In one embodiment, all of the sequences are phase aligned to one of the sequences, such as the sequence generated during the first read operation. Phase aligning the upsampled sequences may be implemented in any suitable manner, such as by phase shifting each sequence relative to the target sequence until a correlation between the sequences reaches a maximum.
After compensating for the frequency error in each upsampled sequence and phase aligning the upsampled sequences, the upsampled sequences are decimated (block 70) by the inverse amount of upsampling in block 62. The signal samples in each sequence are amplitude normalized (block 72), for example, by computing the average signal amplitude across all of the sequences, and then adjusting the amplitude of each sequence based on the average amplitude. Amplitude normalizing the sequences may help account for variations in signal quality that occur across the multiple read operations due, for example, to off-track errors or fly height errors. An average waveform is then generated by averaging the amplitude normalized sequences (block 74), and the average waveform is then subtracted from each normalized sequence of signal samples in order to extract the non-repeatable signal noise. In one embodiment, the non-repeatable signal noise may be evaluated, for example, to identify faulty components, such as an unstable read element as described above.
The phase error detector 56 in FIG. 3A may compute the phase error between the first periodic pattern 21 and the second periodic pattern 25 (FIG. 3C) in any suitable manner. In one embodiment, the phase error detector 56 may compute the phase of the first periodic pattern 21 by computing a discrete Fourier transform (DFT), and in one embodiment, by computing a single frequency DFT at the frequency of the periodic pattern. The phase error detector 56 may also similarly compute the phase of the second periodic pattern 25 using a single frequency DFT, and then subtract the two phase measurements to generate the phase error 58.
In the example of FIG. 3C, the first periodic pattern 21 and the second periodic pattern 25 comprises a 2T signal, such as a non-return to zero (NRZ) sequence comprising (+1+1−1−1+1+−1−1 . . . ). In another embodiment, the first and second periodic patterns may be written at a much lower frequency, such as a 16T signal in order to detect a phase error caused by the frequency error that spans up to 16T. Other embodiments may employ an even lower frequency periodic pattern in order to accommodate even larger phase errors that may be caused by larger frequency errors.
In the embodiment of FIG. 2C, the data written to the disk comprises a sync mark 27 following the first periodic pattern 21 which is used to detect the beginning of the payload 23. In addition, the sync mark 27 in each sequence generated during each read of the data may also be used to coarsely phase align (within a signal sample period) the payloads 23 of the resulting sequences. In one embodiment, since the data is sampled asynchronously without employing any real-time timing recovery, the sync mark 27 may be recorded as a low frequency, long sequence of bits (e.g., 160 bits) which helps ensure accurate detection of the sync mark 27 within the asynchronous signal samples.
In one embodiment, the written data shown in FIG. 2C may be read multiple times without performing the phase-alignment and averaging process described above with respect to the flow diagram of FIG. 4. For example, when attempting to recover a data sector during retry operations, each sequence of asynchronous signal samples may be processed independently in an attempt to recover the data sector. In another embodiment, only some of the processing in the flow diagram of FIG. 4 may be performed on each sequence of asynchronous signal samples, such as phase-aligning and averaging in order to improve the signal-to-noise ratio of the asynchronous signal samples without attempting to extract the non-repeatable noise from the read signal.
Any suitable control circuitry may be employed to implement the flow diagrams in the above embodiments, such as any suitable integrated circuit or circuits. For example, the control circuitry may be implemented within a read channel integrated circuit, or in a component separate from the read channel, such as a disk controller, or certain operations described above may be performed by a read channel and others by a disk controller. In one embodiment, the read channel and disk controller are implemented as separate integrated circuits, and in an alternative embodiment they are fabricated into a single integrated circuit or system on a chip (SOC). In addition, the control circuitry may include a suitable preamp circuit implemented as a separate integrated circuit, integrated into the read channel or disk controller circuit, or integrated into a SOC.
In one embodiment, the control circuitry comprises a microprocessor executing instructions, the instructions being operable to cause the microprocessor to perform the flow diagrams described herein. The instructions may be stored in any computer-readable medium. In one embodiment, they may be stored on a non-volatile semiconductor memory external to the microprocessor, or integrated with the microprocessor in a SOC. In another embodiment, the instructions are stored on the disk and read into a volatile semiconductor memory when the disk drive is powered on. In yet another embodiment, the control circuitry comprises suitable logic circuitry, such as state machine circuitry.
The various features and processes described above may be used independently of one another, or may be combined in various ways. All possible combinations and subcombinations are intended to fall within the scope of this disclosure. In addition, certain method, event or process blocks may be omitted in some implementations. The methods and processes described herein are also not limited to any particular sequence, and the blocks or states relating thereto can be performed in other sequences that are appropriate. For example, described tasks or events may be performed in an order other than that specifically disclosed, or multiple may be combined in a single block or state. The example tasks or events may be performed in serial, in parallel, or in some other manner. Tasks or events may be added to or removed from the disclosed example embodiments. The example systems and components described herein may be configured differently than described. For example, elements may be added to, removed from, or rearranged compared to the disclosed example embodiments.
While certain example embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions disclosed herein. Thus, nothing in the foregoing description is intended to imply that any particular feature, characteristic, step, module, or block is necessary or indispensable. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions disclosed herein.
Patent Grant
8947811
