Patent Application
20070085776
The present application claims priority from Japanese application JP2005-298310 filed on Oct. 13, 2005, the content of which is hereby incorporated by reference into this application.
The present invention relates to display apparatuses for displaying television (TV) images by use of a flat face panel display unit with electron emission elements.
In display apparatuses such as TV receivers, advances in display units bring challenges for development of matrix type display apparatuses using field emission elements or electron emission elements or else as the flat panel (flat-face panel type) display unit. These matrix type display apparatuses are usually designed so that a large number of light-emitting elements which constitute picture elements or “pixels” are laid out in a matrix form for performing visual display operations. A single light-emitting element is generally made up of an electron source for releasing electrons into a vacuum space and a layer of fluorescent material which is applied a high voltage for acceleration of the electrons thus released and which performs light emission due to excitation by such electrons. A display screen is configured from a matrix of rows and columns of display operation-performing elements, which are disposed on a flat plane of the display screen and are connected by conductive wiring lines that extend longitudinally and laterally. One typical approach to enabling operation of respective light-emitting elements is to employ a so-called matrix drive technique for selectively activating a light-emitting element residing at a cross-point or “intersection” of the longitudinal and lateral conductive wiring lines.
In the case of driving multiple light-emitting elements which are laid out in the matrix on the flat plane, the electrical resistance of wiring lines becomes hardly negligible. More specifically, those lines with a relatively short length in close proximity to the end portion of a drive unit of the display screen are appreciably different in wiring resistance from other wiring lines with an increased length. This wire resistance difference causes the potential drop-down of a voltage applied thereto, which in turn results in occurrence of image quality deterioration, such as brightness irregularities. Known techniques for correction of this image quality reduction are disclosed, for example, in JP-A-2001-324957 and JP-A-2005-115314.
JP-A-2001-324957 discloses therein a scheme for detecting a drive voltage decrease due to the presence of wire resistance and for feeding it back to the voltage on a supply side to thereby finally apply a prespecified drive voltage.
JP-A-2005-115314 discloses a technique for application of a voltage which is designed to increase in its pulse width with an increase in distance of an electrode from a drive circuit operatively associated therewith.
Unfortunately, the above-stated prior known techniques fail to take into consideration any influence of capacitive components of the light-emitting elements. Specifically, the prior art schemes do not sufficiently recognize the fact which follows. In case the waveform of a drive voltage is of a rectangle shape, the actually applied waveform has a delay, resulting in unwanted creation of a shape with the lack of a portion of the waveform. This leads to the failure of application of a sufficient voltage, which makes it impossible to finally obtain any intended brightness or luminance.
The present invention provides a technique suitably adaptable for improvement of the display image quality by successfully correcting or “amending” the image quality with respect to image quality deterioration otherwise occurring due to the presence of capacitive components of the light-emitting elements.
To this end, this invention provides a display apparatus which includes a plurality of scan lines, a scan line drive circuit connected to at least either one of right and left ends of the plurality of scan lines for sequentially applying a scan voltage pulse to the scan lines, a plurality of signal lines, a signal line drive circuit connected to the plurality of signal lines-for applying to these signal lines a drive voltage pulse pursuant to an input image signal, an electron source connected to respective intersections of the plurality of scan lines and the plurality of signal lines for giving off electrons in accordance with a potential difference between the scan voltage and the drive voltage, and a control unit, wherein the control unit is operative to control the scan line drive circuit and the signal line drive circuit in such a way that the drive voltage pulse becomes greater in width than the scan voltage pulse.
With such an arrangement, it becomes possible to apply an appropriate drive voltage in a way pursuant to a delay of waveform due to capacitive components. Furthermore, for example, in the drive of a line which is large in waveform delay, that is, a line with its delay becoming larger with an increase in distance from a drive element-side end face, control is provided to ensure that the drive voltage becomes greater in pulse width than the scan voltage.
According to this invention, it is possible to provide a technique adaptable for the improvement of the display image quality by effectively correcting the image quality with respect to image quality deterioration occurrable due to the presence of capacitive components of light-emitting elements.
Other objects, features and advantages of the invention will become apparent from the following description of the embodiments of the invention taken in conjunction with the accompanying drawings.
Several embodiments of the present invention will be described while referring to the accompanying drawings below. Note that those constituent parts or components with similar functions are denoted by identical reference numerals, and repetitive explanations thereof will be eliminated for brevity purposes of the description.
FIGS. 1 to 8 are explanation diagrams of a first embodiment of this invention. Explanation will first be given of outline contents of an operation by using FIGS. 1 to 8; thereafter, individual operation contents will be set forth in a sequential order of
Turning back to
A display operation is achieved by execution of a light emission operation which follows. Electrons that are released out of the electron emitter 210 are attracted to an acceleration high-voltage applying unit—e.g., an anode electrode 280 to which a high voltage of 5 kV (5000 V) or above is applied—and then reach the fluorescent material 230 by way of orbits 220 to excite the fluorescent material 230, thereby performing a light emission operation.
The display panel 200 is generally made up of a pair of spaced-apart glass substrates—namely, a cathode substrate 240 and an anode substrate 250—and components in a vacuum space 270 which is formed by spacers 260 that retain the distance between the substrates.
The electron emitter side 210 is structured from a thinned dielectric layer 212 and an upper electrode 213, wherein the layer 212 is part of a protective dielectric layer 214 which overlies a lower electrode 211 that is above the cathode substrate 240. The lower electrode 211 and the upper electrode 213 are spaced apart from each other by the dielectric layer 212 as interposed therebetween. By applying between them a predetermined voltage of 9 V or else as an example, electrons are given off toward the vacuum space 270. The amount of such electrons to be emitted by the application voltage is controllable. Additionally, the lower electrode 211, the protective dielectric layer 214, an interlayer mask 215, a thick-film electrode 218 and the upper electrode 213 are arranged beneath the spacers 260 in this order of sequence when viewed from the cathode substrate side.
A structure of the fluorescent material side is such that it is constituted from the fluorescent material 230 which is provided at the anode substrate 250 that is made of transparent glass and which has prespecified electrical conductivity and the anode electrode 280 which surrounds the fluorescent material that makes up a picture element or “pixel.” The anode electrode 280 is applied a high voltage of 5000 V or else, for example, which is supplied from external circuitry of the display panel 200 such as the acceleration high-voltage applying unit, wherein the voltage is applied between it and the lower electrode of the cathode substrate. At this time the fluorescent material 230 that is connected to the anode electrode 280 is at substantially the same potential. The previously stated electrodes emitted from the electron emitter 210 on the cathode side are attracted to the fluorescent material 230 that is coupled to the anode electrode 280 and progress within the vacuum space 270 as indicated by the orbits 220 to collide or impinge with the fluorescent material 230 to thereby perform a light emission operation by means of scintillation effects of the fluorescent material 230.
The electron emitter 210 is structured from the lower electrode 211 that overlies the cathode substrate 240, the upper electrode 213, and the protective dielectric layer 214 interposed therebetween. As previously stated in
As shown in
The thick-film electrode 218 is connected as a conductor which continuously extends from the upper-left to the lower-right direction in
In this way, a plurality of thick-film electrodes 218 and lower electrodes 211 are laid out so that these cross together at right angles in a matrix form, wherein electron emitters 210 are disposed at cross-points or “intersections” thereof.
Note here that when activating a specific electron emitter 210, a thick-film electrode 218 and a lower electrode 211 which are connected to the electron emitter 210 may be selected. Upon activation of its neighboring electron emitter 210′, a thick-film electrode 218′ and lower electrode 211 which are connected to the electron emitter 210′ may be selected. In explanations to be given later, the connection destination of these thick-film electrodes 218 is assumed to be a scan drive circuit while supposing that the connection destination of the electron lower electrodes 211 is a data drive circuit.
Beneath the spacers 260, the lower electrode 211, protective dielectric layer 214, interlayer mask 215, thick-film electrode 218 and upper electrode 213 are arranged in this order of sequence from the cathode substrate side. The lower electrode 211 is formed by a deposition process to have a film thickness of 10 μm as an example. This thickness is far less than the thickness of thick-film electrode 218, e.g., 300 μm. Additionally the lower electrode 211 is designed for example to have a width of 400 μm, which is less than the pixel size of 500 μm, for a longitudinal screen size of 400 mm, although it is variable depending on a screen size. Thus, its internal electrical resistance is not negligible. For instance, the internal resistance becomes 1 kΩ for the longitudinal size of 400 mm. This causes the above-noted example to exhibit a difference in resistance of 1 kΩ between the nearest element connected to the drive circuit and an element furthest therefrom in a sense of circuitry. For this reason, it is necessary to perform correction of the internal resistance of the lower electrode.
An operation of the overall drive circuit is performed in a procedure which follows. Firstly, at a first step, display data of one line is set up at each driver unit on the data drive side. Then, at a second step, a switch unit on the scan drive side is rendered operative to select a line to be activated and then apply a voltage thereto.
The data drive side operation at the first step will be explained sequentially from a data input stage. First, digital data as input from a data input terminal 450 is converted by a D/A converter 410 into an analog signal. The digital data is such that 4,095 (=1,365×3) per-pixel three-color data segments are supplied sequentially for a plurality of—e.g., 1,365—pixels in a single line along the horizontal direction of the displaying screen. Data switching is performed in a sequential order in response to a clock signal 451 as input thereto. At this time, a voltage to be supplied from a data power supply 620 is used as a reference voltage of the D/A converter circuit. A voltage range in which the analog signal after D/A conversion is variable in potential is defined by this data power supply 620. The data as has been converted to the analog signal is input to a shift register 440 and then retained and stored in the shift register 440 in response to the clock signal 451. In this way, 4,095 data items are input, which correspond to one linear array of pixels—e.g., 1,365 pixels—corresponding to one lateral line of the screen.
Next, the one-line data is held at a latch circuit 430. This latch circuit 430 is provided to ensure that the display data is kept unchanged during the displaying of the one-line data even while the next one-line data is in a process of input to the shift register. An output from the latch circuit 430 has outputs which correspond in number to the light-emitting elements for displaying, e.g., 4,095 elements. The output signal is subjected to impedance conversion at a driver 420 and then sent to the panel 350 by means of low impedance driving techniques, thereby to drive the light-emitting elements. At this time, a latch signal 731 to the latch circuit 430 is generated by the pulse generator circuit A 730 on the basis of an input from a terminal 530 for receipt of an externally transmitted scan signal. Further, as will be described later, the latch signal's width is modified in deference to the number of a line for light up. The latch circuit 430 is rendered operative upon rising up of the waveform of the latch signal 731. Regarding the width of latch signal, description will be given later.
Next, an operation of the switch unit on the scan drive side at the second step will be explained. The scan side which is another terminal of the panel 350 performs its operation in responding to the application of a prespecified voltage to one line to be selectively operated. For example, in order to drive a first line 351 of the panel 350, the switch A 510 is rendered operative. When it is in a rest state, the switch A 510 is set to its voltage 0 V side in a ground state, by way of example. When letting it operate, the switch A 510 is changed over to apply a voltage of a scan power supply 610 to the first line 351. This switch A 510 operates in responding to a pulse which is generated by a pulse generator circuit B 740 to have a predetermined length of about 0.017 ms, for example.
A signal as output from the pulse generator circuit B 740 is also supplied to a counter B 550. At a count-up circuit of the counter B 550, it counts up the number of input pulses and performs output toward the lines to be driven sequentially. An example is that when a first pulse of the first line is input, a signal is output to a signal line as connected to a gate A 520. Upon input of a second pulse, a signal is output to a signal line connected to a gate B 521, which is in charge of the second line. Upon input of the 768-th pulse, a signal is output to a signal line connected to a gate D 525, which is in charge of the 768-th line. In this way, the counter B 550 sequentially counts up the pulses of, from the first to 768-th line for example, outputs signals to respective output lines, and then selects a line to be operated, i.e., activated for light emission.
Here, explanation is given of the entire operation by turning back to an upstream side. A signal for startup of a one-line display operation operates with the pulse signal from the scan input terminal 530 as a trigger. The scan signal is sent from the control unit (not shown) once at a time whenever a one-line operation is done.
The input pulse-shaped signal is sent to a counter A 710 and the pulse generator circuit A 730. At this time, the counter A 710 counts up the number of input pulses and then sends its result to ROM 720 as a line number. At ROM 720, the information being stored therein is read out of it based on the counted line number and is then sent as pulse width data to the pulse generator circuit A 730. The pulse generator circuit A 730 is responsive to receipt of the pulse width data as sent thereto, for outputting to a latch signal line 731 certain pulse width values; for example, 0.001 ms for the first line, 0.005 ms for the 374-th line, and 0.009 ms for the 768-th line.
The pulses of the latch signal are again pulsed or “repulsed,” by the pulse generator circuit B 740 for transmission to the counter B 550. The counter B 550 switches between lines to be sequentially output on a per-latch signal basis. More specifically, the initially identified first output line becomes a first line portion, for permitting a line connected to the gate A 520 to operate. At this time, the gate A 520 takes AND operation of a pulse being sent from the pulse generator circuit B 740 and a signal as sent from the counter B 550, and then sends its output to the switch A 510. During a light emission operation of the first line, the switch A 510 is made operative within a time period corresponding to the width of a pulse to be output from the pulse generator circuit B 740, e.g., for 0.017 ms, to apply the voltage of the scan power supply 610, e.g., 9 V, to a scan line A 351. During an operation of the second line, the gate B 521 is rendered operative for activation of a switch B 511 to thereby drive a scan line B 352. With such procedure, during an operation of the 768-th line, a scan line D 355 is driven, resulting in completion of a display operation of one screen.
At the control unit (not shown), upon receipt of a signal from a scan terminal 540 for take out of the signal of the pulse generator circuit B 740, it determines that the one-line operation is ended, and then inputs a pulse for use as a startup signal to a scan signal terminal 530 that is expected to initiate the next one-line operation. Within this session, the time of one-line operation becomes a total sum of the above-stated latch signal by means of the pulse generator circuit A 730 and the scan signal due to the pulse generator circuit B 740. The one-line operation time is such that at the first line for example, the latch signal width is 0.001 ms and the scan signal width is 0.017 ms so that a total time is 0.018 ms. At the second line for example, the latch signal width is 0.005 ms and the scan signal width is 0.017 ms so that the one-line operation time becomes 0.022 ms in total. At the 768-th line for example, the latch signal width is 0.009 ms and the scan signal width is 0.017 ms so that the one-line operation time is 0.026 ms in total. In this way, the operation is performed for a specified operation time corresponding to the line number. More specifically, in case the line number is less and when driving a line adjacent to the driver 420 on the drive side, the operation time is shortened. On the contrary, in case the line number is large and when driving a line spaced far from the drive-side driver 420, the operation time is made longer.
It should be noted that whereas panel inside electrodes on the drive side are made of thin film, panel inside electrodes on the scan side are thick-film electrodes by way of example. These thick-film electrodes have an electrical resistance value of 10Ω for example, which is negligibly small when compared to the resistance value on the drive side, e.g., 1 kΩ.
Additionally, an acceleration voltage of 5 kV for example as supplied from a high voltage circuit 900 is supplied to the panel 350.
Next, explanation will be given with a center focus on the light-emitting element part.
As previously described with reference to FIGS. 2 to 4, a single light-emitting element is connected to scan drive and data drive circuits. In
Firstly, at the data drive circuit side, digital data as input from the data input 450 is converted by D/A converter 410 into an analog signal and then driven by a data driver 421 for applying a voltage to the light-emitting element 300. At this time, the voltage to be supplied from the data power supply 620 is employable as the reference voltage of D/A converter circuit. A voltage change range due to D/A conversion is defined by the voltage of the data power supply 620.
Next, on the scan drive circuit side, at the gate A 520 to which a scan signal 741 and a select signal 551 are input, a signal with coincidence of these signals is sent to the switch A 510. At this time, the switch A 510 is arranged to select for output either one of the positive (plus) side and ground side of the scan power supply 610. In other words, either one of the potential levels of the positive-side and the ground of scan power supply 610 is supplied via the switch A 510 based on the scan pulse signal and select signal.
Summarizing the operation of the light-emitting element, the voltage supplied to the light-emitting element 300 is such that a certain voltage is supplied which is due to combination of the positive-side voltage that is the voltage of the scan power supply 610 on the scan drive circuit side and the negative (minus)-side voltage as defined by the data power supply 620 on the data drive circuit side. For example, supposing that a voltage of +7 V is supplied from the scan drive circuit side while a voltage of −1.5 V is fed from the data drive circuit side, 8.5 V voltage with a potential difference therebetween is applied to the element. Obviously, the voltage on the data drive circuit side is variable in potential depending on an output from the D/A converter circuit 440, so the above-stated value of −1.5 V is a value which is set up based on data of specific brightness and is the one that changes in various ways during a display operation.
Regarding an operation of element peripheral circuitry in
The 768-th element 305 is presently selected, causing the 768-th capacitor 315 to be connected in parallel to the series circuit of zener diode 325 and diode 335, which is an equivalent circuit of the element. In this select state, the positive side of the scan power supply 610 is connected. Here, assume for example that an output voltage of D/A converter 410 is −1.5 V based on input image data whereas the voltage of the scan power supply 610 is at 7.0 V. Suppose that a flowing current is a micro-current of 0.001 mA or more or less. If this is the case, the voltage to be applied to the 768-th element 305 becomes about 8.5 V in total.
At this time, when looking at from the driver A 421 side, it operates as a capacitor of about 0.0768 μF as a result of combination of parallel-coupled 768 capacitance components in case a total value of serial coupled resistors, e.g., 768 capacitors, is set at 1,000Ω, and thus functions as a low-pass filter (LPF). When applying a drive waveform to the final stage of light-emitting element 305, a waveform delay can occur as a matter of course.
Next, practical drive conditions will be explained. The explanation will be given while referring to
Explanation will be given in a viewpoint of the operating time.
As shown in
In addition, by performing light emission while setting up an appropriate arrival time depending upon variability of the delay time in a way pursuant to the brightness to be displayed even in case where the applied voltage is −1.0 V at E3 at 930 for example, or at −0.5 V at E4 at 9.40, it is possible to perform the light emission operation with constant brightness at all times.
It is also possible to set up a per-line operation time within a total one-screen operation time period. This makes it possible to allow the display operation to offer its inherent proper operability without causing the one-screen operation time to become irregular.
This second embodiment is arranged not only to change a one-line display operation time during a display operation of a single line making up the display of one screen but also to modify the ratio of a lighting time to a rest time during the display operation time.
In
The scan signal is sent from the control unit (not shown) per one-line operation. The input pulse-shaped signal is sent to a counter A 710, pulse generator circuit A 730 and counter C 910. At this time, the counter A 710 counts up the number of input pulses and then sends its result to the ROM 720 as a line number. At ROM 720, the information being stored therein is read out of it based on the counted line number and is then sent as pulse width data to the pulse generator circuit A 730. The pulse generator circuit A 730 is responsive to receipt of the pulse width data as sent thereto, for outputting to a latch signal line 731 certain pulse width values; for example, 0.001 ms for the first line, 0.005 ms for the 374-th line, and 0.009 ms for the 768-th line. Meanwhile, the counter C 910 counts up the number of input pulses and then sends its result to ROM B 920 as a line number. At ROM B 920, the data being stored therein is read based on the counted line number and is then sent as pulse width data to a pulse generator circuit C 930. The pulse generator circuit C 930 is responsive to receipt of the pulse width data as sent thereto, for outputting to a latch signal line 741 certain pulse width values; for example, 0.015 ms for the first line, 0.022 ms for the 374-th line, and 0.028 ms for the 768-th line.
The pulse that was generated at the pulse generator circuit C 930 with the pulse of latch signal as a trigger is sent to the counter B 550. The counter B 550 switches between lines to be sequentially output on a per-latch signal basis. More specifically, the initially identified first output line becomes a first line portion, for permitting a line connected to the gate A 520 to operate. At this time, the gate A 520 takes AND operation of a pulse being sent from the pulse generator circuit C 940 and a signal as sent from the counter B 550, and then sends its output to the switch A 510. During a light emission operation of the first line, the switch A 510 is made operative within a time period corresponding to the width of a pulse to be output from the pulse generator circuit B 740, e.g., for 0.015 ms, to apply the voltage of the scan power supply 610, e.g., 9 V, to a scan line A 351. During an operation of the second line, the gate B 521 is rendered operative for activation of a switch B 511 to thereby drive a scan line B 352, thereby operating for a time corresponding to the pulse width, e.g., 0.017 ms, as stated previously. In this way, during an operation of the 768-th line, a scan line D 355 is driven to operate for the time of the pulse width, e.g., 0.019 ms, resulting in completion of a display operation of one screen.
At the control unit (not shown), upon receipt of a signal from a scan terminal 540 for take out of the signal of the pulse generator circuit B 740, it determines that the one-line operation is ended, and then inputs a pulse for use as a startup signal to a scan signal terminal 530 that is expected to begin the next one-line operation. Within this session, the time of one-line operation becomes a total sum of the above-stated latch signal by means of the pulse generator circuit A 730 and the scan signal due to the pulse generator circuit C 930. The one-line operation time is such that at the first line for example, the latch signal width is 0.001 ms and the scan signal width is 0.015 ms so that a total time is 0.016 ms. At the 384-th line for example, the latch signal width is 0.005 ms and the scan signal width is 0.017 ms so that the one-line operation time becomes 0.022 ms in total. At the 768-th line for example, the latch signal width is 0.009 ms and the scan signal width is 0.022 ms, so the one-line operation time is 0.028 ms in total. In this way, the operation is performed for a specified operation time corresponding to the line number. More specifically, in case the line number is less and when driving a line adjacent to the driver 420 on the drive side, the operation time is shortened in both the rest time and the lighting time. On the contrary, in case the line number is large and when driving a line spaced far from the drive-side driver 420, the operation time is made longer both in rest time and in lighting time.
Explanation will be given in a viewpoint of the operating time.
As stated with reference to
The third embodiment is arranged to change or modify the acceleration voltage of electrons without varying the display operation time of one line during a display operation of one line making up the display of one screen. In
The input pulse-shaped signal is sent to a counter A 710 and pulse generator circuit A 730. At this time, the counter A 710 counts up the number of input pulses and then sends its result to ROM 720 as a line number. At ROM 720, the information as stored therein is read based on the counted line number and is then sent as pulse width data to the pulse generator circuit A 730. Simultaneously, the acceleration voltage data is sent from ROM 720 to a high voltage circuit 900 via a signal line 901. The pulse generator circuit A 730 is responsive to receipt of the pulse width data as sent thereto, for outputting to a latch signal line 731 certain pulse width values; for example, 0.001 ms for the first line, 0.005 ms for the 374-th line, and 0.009 ms for the 768-th line. The high voltage circuit 900 generates by the acceleration voltage data as sent thereto an acceleration voltage of 7.0 kV for the first line, 7.8 V for the 374-th line, and 8.8 kV for the 768-th line and then supplies it to the display panel 350. The light emission amount of the display panel changes due to variability of the acceleration voltage. Thus, modifying the acceleration voltage on a per-line basis makes it possible to adjust the brightness per one line.
The pulses of the latch signal are repulsed by the pulse generator circuit B 740 for transmission to the counter B 550. The counter B 550 performs switching between lines to be sequentially output on a per-latch signal basis. More specifically, the initially identified first output line becomes a first line portion, for permitting a line connected to the gate A 520 to operate. At this time, the gate A 520 takes AND operation of a pulse being sent from the pulse generator circuit B 740 and a signal as sent from the counter B 550, and then sends its output to the switch A 510. During a light emission operation of the first line, the switch A 510 operates within a time period corresponding to the width of a pulse to be output from the pulse generator circuit B 740, e.g., for 0.017 ms, to apply the voltage of the scan power supply 610, e.g., 9 V, to a scan line A 351. During an operation of the second line, the gate B 521 is rendered operative for activation of a switch B 511 to thereby drive a scan line B 352. With such a procedure, during an operation of the 768-th line, a scan line D 355 is driven, resulting in completion of a display operation of one screen.
With such an arrangement for varying the operation time on a per-line basis and further modifying the high-potential acceleration voltage also in units of lines, it is possible to prevent irregularities of the brightness in one screen even in cases where the voltage to be applied to a light-emitting element is large in delay and thus its potential stabilization takes time. This makes it possible to achieve uniform screen displayability.
Although the embodiment explanation above is given based on a specific example having its display unit using electron emission elements, it is needless to say that similar effects and advantages are obtainable even for those using self-luminous light-emitting elements of other electronic display schemes, such as field emission elements, for example.
In addition, although in the above-noted embodiment explanation three representative embodiments have been described which have three principal features in regard to the technique for appropriately changing two time periods, i.e., the rest time and lighting time, within the operation time of one line and the scheme for modifying the acceleration voltage with a high potential level, it would readily occur to a skilled person that similar effects are still available even when employing other combinations—for example, an arrangement for modifying only the acceleration voltage while forcing the rest time and the lighting time to stay constant throughout all the lines involved.
Furthermore, although in the above-noted embodiments the scan-line drive circuit for sequential application of scan voltage pulses is installed at one end of an ensemble of scan lines, such may alternatively be provided at its both ends. Similarly, while the signal-line drive circuit which applies drive voltage pulses pursuant to an input video signal is situated at one end of a group of signal lines, a couple of similar circuits may alternatively be installed at both ends thereof.
It should be further understood by those skilled in the art that although the foregoing description has been made on embodiments of the invention, the invention is not limited thereto and various changes and modifications may be made without departing from the spirit of the invention and the scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2005-298310 | Oct 2005 | JP | national |
