Patent Application
20150255018
This application claims the benefit of Japanese Priority Patent Application JP 2014-044979 filed Mar. 7, 2014, the entire contents of which are incorporated herein by reference.
The present technology relates to a display apparatus and an electronic device including the display apparatus.
In recent years, a display apparatus has been developed to have a large sized screen using a flat type display panel such as a liquid crystal display panel and an electroluminescence display panel.
A signal waveform of a scanning line in the display panel is subjected to a transient effect of wiring resistance and parasitic capacitance and is changed thereby. Thus, at near and far ends of the driver producing a scanning signal, there is a difference in slowdown of the waveform. This may cause a difference in a signal write time of each pixel in the display panel, and shading may be generated on an image displayed.
In avoid this, capacitance of the pixel is changed depending on a distance from the driver (see Japanese Patent Application Laid-open No. 2011-100138). The shading is decreased by adding capacitance to the scanning line to positively slow down the signal, thereby decreasing the shading (see Japanese Patent Application Laid-open No. 2013-044891).
The configurations described in the above-described Japanese Patent Application Laid-open No. 2011-100138 and Japanese Patent Application Laid-open No. 2013-044891 are fixed and are difficult to control setting corresponding to a production tolerance and a temperature change. With the configuration that a slew rate of the signal generated by the driver can be controlled and a signal waveform is slow downed in advance, an individual control corresponding to the production tolerance is possible.
For example, when an output stage of a driver is configured of a plurality of transistors connected in parallel and the number of the transistors to be operated is controlled, the individual control is possible. However, the control is not sequentially but discretely, which is undesirable.
In view of the circumstances as described above, there is a need for providing a display apparatus that a slew rate of a scanning signal can be sequentially controlled and shading can be effectively inhibited, and an electronic device including the display apparatus.
According to an embodiment of the present technology, there is provided a display apparatus including:
a display panel where display elements connected to a scanning line and a signal line are arrayed in a two dimensional matrix, and
a driving circuit unit configured to drive the display panel, the driving circuit unit including a gate driver configured to feed a scanning signal to the scanning line such that a back gate voltage of a field effect transistor configuring an output buffer for generating the scanning signal is capable of controlling.
According to an embodiment of the present technology, there is provided an electronic device including a display apparatus, which includes:
a display panel where display elements connected to a scanning line and a signal line are arrayed in a two dimensional matrix, and
a driving circuit unit configured to drive the display panel, the driving circuit unit including a gate driver configured to feed a scanning signal to the scanning line such that a back gate voltage of a field effect transistor configuring an output buffer for generating the scanning signal is capable of controlling.
By the display apparatus and the electronic device including the display apparatus according to an embodiment of the present technology, as the slew rate of the scanning signal can be controlled sequentially, the shading can be effectively inhibited.
These and other objects, features and advantages of the present technology will become more apparent in light of the following detailed description of best mode embodiments thereof, as illustrated in the accompanying drawings.
Hereinafter, an embodiment of the present technology will be described with reference to the drawings. The present technology is not limited to the embodiments, various numerals and materials in the embodiments are provided for purposes of illustration only. In the following description, the same symbols are used for the same matter or the matter having the same function, an overlapped description will be omitted. The embodiments of the present technology will be described in the following order.
A display apparatus according to an embodiment of the present technology or the display apparatus included in an electronic device (hereinafter simply referred to as “a display apparatus according to the present technology”) has a feature that:
an output buffer includes a first field effect transistor and a second field effect transistor,
one source/drain region of the first transistor is connected to one source/drain region of the second transistor,
a first voltage is applied to the other source/drain region of the first transistor,
a second voltage is applied to the other source/drain region of the second transistor, and
a back gate voltage of the first transistor and a back gate voltage of the second transistor are configured to be capable of controlling.
In this case, the back gate voltage of the first transistor and the back gate voltage of the second transistor may be configured to be capable of controlling independently. According to the feature, slowdown rise and fall in waveforms of the scanning signal generated by the output buffer can be controlled independently. For example, it can be applicable to the case that the slowdown rise in the waveforms of the scanning signal becomes greater than the slowdown fall in the waveforms of the scanning signal, which is a desirable countermeasure against shading.
The back gate voltage of the first transistor and the back gate voltage of the second transistor can be controlled based on temperature information of a gate driver. For example, it is contemplated that the waveform of the scanning signal may be changed by a temperature change of the gate driver accompanied by the operation of the display apparatus and that a shading degree may be changed. In this case, by acquiring the temperature information from a temperature sensor such as a thermal diode incorporated in the gate driver and by referring to a lockup table to control the back gate voltage, the change in the shading degree can be decreased.
In this case, the back gate voltage of the first transistor and the back gate voltage of the second transistor can be controlled based on the temperature information of the gate driver and temperature information of the display panel. For example, it is contemplated that a resistance value of a scanning line in the display panel is changed by a temperature change accompanied by the operation of the display apparatus to cause a change in a time constant upon signal propagation, thereby changing the shading degree. In this case, by acquiring the temperature information from a temperature sensor such as a thermistor attached to the display panel and by referring to a lockup table to control the back gate voltage, the change in the shading degree can be decreased. By this configuration, as controlling is performed based on the temperature information of the gate driver and temperature information of the display panel, the change in the shading degree can be more effectively decreased.
In the display apparatus according to the present technology including a variety of desirable configurations as described above, the output buffer may include the first transistor and the second transistor that have different conductive types or have a same conductive type.
In the display apparatus according to the present technology including a variety of desirable configurations as described above, the feature of the display element configuring the display panel is not especially limited. For example, the display element may include a current driving element or a voltage driving element. For example, the display panel may be an electroluminescence display panel or a liquid display panel.
The display panel may have a so-called monochrome display configuration or a color display configuration. In the color display configuration, one pixel includes a plurality of sub-pixels, specifically, one pixel includes three sub-pixels: a red display sub-pixel, a green display sub-pixel and a blue display sub-pixel. Moreover, the color display may be configured of one set including these three sub-pixels and one or more of sub-pixels (for example, one set including the three sub-pixels and a sub-pixel for displaying white to improve brightness, one set including the three sub-pixels and a sub-pixel for displaying a complementary color to widen a color reproduction range, one set including the three sub-pixels and a sub-pixel for displaying yellow to widen a color reproduction range and one set including the three sub-pixels and a sub-pixel for displaying yellow and cyan to widen a color reproduction range).
Non-limiting examples of a pixel value of the display panel include VGA (640, 480), S-VGA (800, 600), XGA (1024, 768), APRC (1152, 900), S-XGA (1280, 1024), U-XGA (1600, 1200), HD-TV (1920, 1080), Q-XGA (2048, 1536), (1920, 1035), (720, 480), (1280, 960) for image display resolution.
For example, the driving circuit unit used by the present technology can be configured of well-known circuit elements such as a logic circuit, an arithmetic circuit, a memory element and an operational amplifier. For example, the gate driver may be a driver IC (Integrated Circuit).
The feature of the electronic device including the display apparatus is not especially limited. There is an illustrative electronic device that displays a video signal inputted from outside or a video signal generated inside as an image or a video.
A variety of conditions shown in the present specification should be strictly or substantially satisfied. Some design or production variability may be allowable.
The first embodiment relates to the display apparatus according to the present technology.
The driving circuit unit 150 includes a gate driver 110 feeding a scanning signal to the scanning line SCL such that a back gate voltage of a field effect transistor configuring an output buffer for generating the scanning signal can be controlled. The gate driver 110 is composed, for example, of a CMOS integrated circuit.
In the first embodiment, the driving circuit unit 150 further includes a data driver 120, a power source unit 130 and a voltage control unit 140 besides the gate driver 110.
In the display panel 100, the display element 101 including a current driving light emitting part ELP and a pixel circuit for driving the light emitting part ELP are connected to the scanning line SCL extending to a row direction (an X direction in
The display panel 100 further includes power feeding lines PS1 connected to the display element 101 arrayed in the row direction and a second power feeding line PS2 connected commonly to all display elements 101. A predetermined driving voltage is fed to the power feeding lines PS1 from the power source unit 130. A common voltage VCat (for example, a ground potential) is fed to the second power feeding line PS2.
Although not shown in
Each number of the scanning line SCL and the power feeding lines PS1 is M. An mth (where m=1, 2, . . . M) row of the display element 101 is connected to an mth scanning line SCLm and an mth feeding line PS1m and configures one display element row. In
The number of the data line DTL is N. An nth (where n=1, 2, . . . N) display element 101 is connected to an nth data line DTLn. In
The display apparatus 1 is a monochrome display and one display element 101 configures one pixel. The display apparatus 1 is line-sequentially scanned by the scanning signal from the gate driver 110. The display element 101 positioned at the mth row and the nth column is hereinafter referred to the (n, m)th display element 101 or an (n, m)th pixel.
As a matter of description convenience, a basic operation of displaying an image by the display apparatus 1 will be firstly described.
In the display apparatus 1, each display element 101 configuring the N pixel arrayed in the mth row is concurrently driven. In other words, a timing of light emission/no light emission of each N display element 101 arranged along the row direction is controlled per row to which the display element belongs. A scanning period (so-called horizontal scanning period) per row upon line-sequential scanning of the display apparatus 1 is less than (1/FR)×(1/M) seconds, where a display frame rate of the display apparatus 1 is represented by FR (frame per second).
A gradation signal vDSig corresponding to the image to be displayed is inputted to the data driver 120 of the display apparatus 1 from an apparatus (not shown), for example. Among the gradation signals vDSig inputted, the gradation signal corresponding to the (n, m)th display element 101 represents as vDSig(n,m). A video signal voltage applied to the data line DTLn by the data driver 120 based on the value of the gradation signal vDSig(n,m) is represented by voltage VSig(n,m).
Each display element 101 at least includes the current driving light emitting part ELP, a write transistor TRW, a driving transistor TRD and a capacitance C1. Once a current flows to the light emitting part ELP via a source/drain region of the driving transistor TRD, light is emitted.
The capacitance C1 is used to hold a voltage of the gate electrode to the source region of the driving transistor TRD (so-called gate-source voltage). While the display element 101 emits light, one source/drain region (a side connected to the power feeding line PS1 in
The write transistor TRW includes a gate electrode connected to the scanning line SCL, one source/drain region connected to the data line DTL and other source/drain region connected to the gate electrode of the driving transistor TRD.
The gate electrode of the driving transistor TRD is connected to the other source/drain region of the write transistor TRW and the other electrode of the capacitance C1, the other source/drain region of the driving transistor TRD is connected to one electrode of the capacitance C1 and the anode electrode of the light emitting part ELP.
The other end of the light emitting part ELP (specifically, a cathode electrode) is connected to the second power feeding line PS2. A capacitance of the light emitting part ELP is represented by a symbol CEL.
When the write transistor TRW is in a conduction state by the scanning signal from the gate driver 110 with a voltage VSi corresponding to the brightness of the image to be displayed being fed to the data line DTL from the data driver 120, the voltage corresponding to the brightness of the image to be displayed is written into the capacitance C1. After the write transistor TRW is in a non-conduction state, a current flows to the driving transistor TRD depending on the voltage held at the capacitance C1 and the light emitting part ELP emits light.
The basic operation of displaying an image by the display apparatus 1 is described above. Next, for a better understanding of the present technology, a relationship between slowdown of the scanning signal propagating the scanning line SCL and shading. Then, a reference embodiment for changing a slew rate of the scanning signal and problems thereof will be described.
In general, the rise and fall of the signal propagating wiring become slowdown and deform due to distributed capacitance and wiring resistance. As a signal propagation path is longer, the degree of the deformation becomes significant. When the scanning signal in the scanning line SCL is taken in consideration, a path length of a display element 1011 nearest to the gate driver 110 (display element arranged at a left end) is different from a path length of a display element 101N farthest from the gate driver 110 (display element arranged at a right end).
Accordingly, when the gate driver 110 feeds an ideal rectangular pulse to the scanning line SCL, a less slowdown pulse shown as a waveform BF1 is applied to the display element 1011 and a pulse having a slowdown rise and fall shown as a waveform BFN is applied to the display element 101N. It arises a difference between a period of the conduction state of the write transistor TRW in the display element 1011 and a period of the conduction state of the write transistor TRW in the display element 101N.
The slowdown of the waveform gets greater approaching the right end. As a result, the period of the conduction state of the write transistor TRW in the display element 101 changes gradually from the left end to the right end of the display panel. This may cause a phenomenon (shading) that the image becomes light or dark from the left end to the right end.
The degree of shading can be decreased by controlling the slew rate of the pulse generated by the gate driver 110. Hereinafter, referring to
Also in this case, the waveform BFN having a slowdown rise/fall lower than the waveform BF1 is applied to the display element 101N. However, as the waveform BF1 already has a slowdown rise/fall, the period of the conduction state of the write transistor TRW in the display element 101 less changes gradually from the left end to the right end. As a result, the shading may be decreased.
The circuit shown in
One source/drain region of the transistors QP1, QP2 and QP3 and one source/drain region of the transistors QN1, QN2 and QN3 are connected, which configures an output part of the output buffer.
A first voltage VDD (for example, 20 volts) is applied to the other source/drain region of the transistors QP1, QP2 and QP3 and a second voltage VSS (for example, 0 volt) is applied to the other source/drain region of the transistors QN1, QN2 and QN3.
For example, switches SW1P, SW2P, SW3P, SW1N, SW2N, SW3N shown in
Based on the above-described status, when the switches SW3P and SW3N shown in
When the switches SW2P, SW2N, SW3P and SW3N shown in
In this way, when the number of the transistor groups to be operated is changed, the slew rate of the signal can be controlled. However, the slew rate only can be controlled gradually and it is less suitable to control the slew rate individually in view of variability of the display panel.
Heretofore, the reference embodiment for changing the slew rate of the scanning signal and problems thereof are described. Next, the configuration of the voltage control unit and the gate driver of the display apparatus 1 according to the first embodiment will be described.
As shown in
one source/drain region of the first transistor QP is connected to one source/drain region of the second transistor QN,
a first voltage VDD is applied to the other source/drain region of the first transistor QP,
a second voltage VSS is applied to the other source/drain region of the second transistor QN, and
a back gate voltage VPGB of the first transistor QP and a back gate voltage VNGB of the second transistor QN are configured to be capable of controlling.
The embodiment shown in
The voltage VPGB and the voltage VNGB are fed to a back gate of the first transistor QP and a back gate of the second transistor QN from the voltage control unit 140, specifically, a back gate voltage generation unit 142.
The back gate voltage generation unit 142 (as a matter of drawing convenience, it is represented as a BG voltage generation unit in
In the circuit shown in
In contrast, in the back gate voltage generation unit 142 shown in
Here, an operation change of the transistor by controlling the back gate voltage will be qualitatively described referring to
Specifically, while the drain voltage is set to 10 [volts], the IDS-VGs property is shown when a back gate voltage VNBG is set to 0, −2, −4 and −10 [volts]. Note that as a matter of drawing convenience, the drain current IDS normalized is shown.
As shown in
Thus, by controlling the back gate voltage of the transistors QP1 and QN1 configuring the output buffer of the gate driver 110, the slew rate of the scanning signal generated can be controlled.
The voltage control unit 140 shown in
As the gate driver 110 is operated, the temperature increases. This may cause a phenomenon that an operation point of the transistor is changed such that the slew rate of the signal outputted to the scanning line SCL is changed.
In the first embodiment, the back gate voltage of the first transistor QP and the back gate voltage of the second transistor QN are configured to be controlled based on the temperature information of the gate driver 110.
The control circuit (not shown) included in the voltage control unit 140 acquires the temperature information of the gate driver 110 based on a detection result of the temperature sensor such as a thermal diode incorporated in the gate driver 110, for example, (see
A suitable value is assigned to the look up table 141 in a delivery inspection of the display apparatus 1 in a factory, for example, based on the variability of the display panel 100 and a temperature property of the gate driver 110 (Step S101). For example, by measuring a property change of shading of the display apparatus 1 in an actual operation inspection, the suitable value may be set, as appropriate.
When the display apparatus 1 after shipment is operated, the temperature information of the gate driver 110 (Step S102) is acquired and the look up table (LUT) is referred. Based on the result, the back gate voltage generation unit 142 is controlled (Step S103). The control circuit (not shown) incorporated into the voltage control unit 140 repeats Step S102 and Step S103 at adequate time intervals. The time interval may be set depending on the specification of the display apparatus, as appropriate.
As described above, in the display apparatus according to the first embodiment, the shading can be controlled independently in view of the variability of the display panel as well as the temperature property of the gate driver.
In the above description, the gate driver is the CMOS. For example, the gate driver may be composed of only NMOS or PMOS.
The second embodiment also relates to the display apparatus according to the present technology.
The display apparatus according to the second embodiment has the same configuration as the display apparatus according to the first embodiment except that the back gate voltage is controlled based on the temperature information of the display panel.
The driving circuit unit 250 includes the gate driver 110 feeding the scanning signal to the scanning line SCL such that the back gate voltage of the field effect transistor configuring the output buffer for generating the scanning signal can be controlled. The gate driver 110 is composed, for example, of the CMOS integrated circuit.
In the second embodiment, the driving circuit unit 250 further includes the data driver 120, the power source unit 130 and a voltage control unit 240 besides the gate driver 110. As a schematic circuit diagram illustrating the configurations of the voltage control unit and the gate driver of the display apparatus according to the second embodiment, the voltage control unit 140, the look up table 141 and the back gate voltage generation unit (BG voltage generation unit) 142 may be taken as a voltage control unit 240, a look up table 241 and a back gate voltage generation unit (BG voltage generation unit) 242 in
As described in the first embodiment referring to
In the display apparatus 2 according to the second embodiment, the controlling is performed in view of the temperature information of the display panel 100 in addiction to the temperature information of the gate driver 110. In other words, the back gate voltage of the first transistor and the back gate voltage of the second transistor are controlled based on temperature information of the gate driver 110. The temperature information of the display panel 100 may be acquired based on a detection result of a temperature sensor such as a thermistor attached to a rear face of the display panel 100, for example.
A suitable value is assigned to the look up table 241 in a delivery inspection of the display apparatus 2 in a factory, for example, based on the variability of the display panel 100, the temperature property of the gate driver 110 and the temperature property of the display panel 100 (Step S201). For example, by measuring a property change of shading of the display apparatus 2 in an actual operation inspection, the suitable value may be set, as appropriate.
When the display apparatus 2 after shipment is operated, the temperature information of the gate driver 110 and the temperature property of the display panel 100 (Step S202) is acquired and the look up table (LUT) is referred. Based on the result, the back gate voltage generation unit 242 is controlled (Step S203). The control circuit (not shown) incorporated into the voltage control unit 240 repeats Step S202 and Step S203 at adequate time intervals.
As described above, in the display apparatus according to the second embodiment, the shading can be controlled independently in view of the variability of the display panel as well as the temperature properties of the gate driver 110 and the display panel.
An application embodiment of the above-described display apparatus to an electronic device will be described. As an example, there is an electronic device that displays a video signal inputted from outside or generated inside as an image or a video.
While the present technology is described herein with reference to illustrative embodiments for particular applications, it should be understood that the present technology is not limited thereto and various modifications can be practiced based on the technical spirits of the present technology. The numerical values, the structures, the substrates, the raw materials and the processes in the above-described embodiments are only illustrative, and any numerical values, structures, substrates, raw materials and processes different therefrom may be used, as appropriate.
The present technology may have the following configurations.
[1] A display apparatus, including:
a display panel where display elements connected to a scanning line and a signal line are arrayed in a two dimensional matrix, and
a driving circuit unit configured to drive the display panel, the driving circuit unit including a gate driver configured to feed a scanning signal to the scanning line such that a back gate voltage of a field effect transistor configuring an output buffer for generating the scanning signal is capable of controlling.
[2] The display apparatus according to [1] above, in which
an output buffer includes a first field effect transistor and a second field effect transistor,
one source/drain region of the first transistor is connected to one source/drain region of the second transistor,
a first voltage is applied to the other source/drain region of the first transistor,
a second voltage is applied to the other source/drain region of the second transistor, and
a back gate voltage of the first transistor and a back gate voltage of the second transistor are configured to be capable of controlling.
[3] The display apparatus according to [2] above, in which
the back gate voltage of the first transistor and the back gate voltage of the second transistor are configured to be capable of controlling independently.
[4] The display apparatus according to [2] above, in which
the back gate voltage of the first transistor and the back gate voltage of the second transistor are controlled based on temperature information of the gate driver.
[5] The display apparatus according to [4] above, in which
the back gate voltage of the first transistor and the back gate voltage of the second transistor are controlled based on the temperature information of the gate driver and temperature information of the display panel.
[6] The display apparatus according to any one of [2] to [5] above, in which
the first transistor and the second transistor are configured of transistors having different conductive types.
[7] The display apparatus according to any one of [2] to [5] above, in which
the first transistor and the second transistor are configured of transistors having a same conductive type.
[8] An electronic device, including a display apparatus, the display apparatus including:
a display panel where display elements connected to a scanning line and a signal line are arrayed in a two dimensional matrix, and
a driving circuit unit configured to drive the display panel, the driving circuit unit including a gate driver configured to feed a scanning signal to the scanning line such that a back gate voltage of a field effect transistor configuring an output buffer for generating the scanning signal is capable of controlling.
[9] The electronic device according to [8] above, in which
an output buffer includes a first field effect transistor and a second field effect transistor,
one source/drain region of the first transistor is connected to one source/drain region of the second transistor,
a first voltage is applied to the other source/drain region of the first transistor,
a second voltage is applied to the other source/drain region of the second transistor, and
a back gate voltage of the first transistor and a back gate voltage of the second transistor are configured to be capable of controlling.
[10] The electronic device according to [9] above, in which
the back gate voltage of the first transistor and the back gate voltage of the second transistor are configured to be capable of controlling independently.
[11] The electronic device according to [9] above, in which
the back gate voltage of the first transistor and the back gate voltage of the second transistor are controlled based on temperature information of the gate driver.
[12] The electronic device according to [11] above, in which
the back gate voltage of the first transistor and the back gate voltage of the second transistor are controlled based on the temperature information of the gate driver and temperature information of the display panel
[13] The electronic device according to any one of [9] to [12] above, in which
the first transistor and the second transistor are configured of transistors having different conductive types.
[14] The electronic device according to any one of [9] to [12] above, in which
the first transistor and the second transistor are configured of transistors having a same conductive type.
It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2014-044979 | Mar 2014 | JP | national |
