Exemplary embodiments of the present invention are described hereinafter in detail with reference to the drawings. The following description explains some embodiments of the present invention by way of illustration, and the present invention is not limited to the embodiments described hereinbelow.
A first embodiment of the present invention achieves reduction of leakage current by forming an upper electrode of a capacitor in a display apparatus so as to cover the edge of a lower electrode. To begin with, the structure of a typical display apparatus is described. The display apparatus includes a plurality of scan signal lines arranged in parallel on a display area of an insulating substrate and a plurality of display signal lines arranged in parallel to intersect with the scan signal lines. An area surrounded with adjacent scan signal lines and display signal lines serves as a pixel, and a plurality of pixels are arranged in matrix on the display area. Further, a scan signal driver for driving the scan signal lines and a display signal driver for driving the display signal liens are placed on the insulating substrate. At least one thin film transistor (TFT) and capacitor are formed in each pixel.
A transparent glass substrate or the like may be used as an insulating substrate 40. Alternatively, a metal substrate such as Al or stainless steel may be used. An insulating base layer 60 is formed on the insulating substrate 40. The base layer 60 is formed substantially all over the insulating substrate 40. A silicon nitride film 51 and a silicon oxide film 53, which are transparent insulating films, may be used as the base layer 60. Although the base layer 60 has a multilayer structure in this example, it may be a single layer structure having either one film. The semiconductor film 52 is formed on the base layer 60. The semiconductor film 52 is patterned into an island-shape. Thus, the semiconductor film 52 on the base layer 60 has a rectangular pattern.
The semiconductor film 52 includes a source region 521, a channel region 522, and a drain region 523. The channel region 522 is placed between the source region 521 and the drain region 523. The source region 521 and the drain region 523 are conductive regions containing impurities, and they are placed on both sides of the channel region 522. The channel region 522 is a region where a channel is formed upon application of a gate voltage to the gate electrode. The semiconductor film 52 is made of a polycrystalline silicon film, for example. In the patterning of the semiconductor film 52, the edge of the semiconductor film 52 may be tapered. This ensures that the semiconductor film 52 is covered with the gate insulating film 50, which is described later. It is thereby possible to reduce defects such as dielectric breakdown.
The capacitor lower electrode 70 is formed at a separate position from the semiconductor film 52 or as the same island as the drain region 523. The gate insulating film 50 is formed on the semiconductor film 52. The gate insulating film 50 entirely covers the semiconductor film 52. Thus, the lower surface of the gate insulating film 50 is in contact with the upper surface of the semiconductor film 52. Further, the gate electrode 54 is formed on the gate insulating film 50. The gate electrode 54 is placed above the channel region 522 of the semiconductor film 52. Thus, the gate electrode 54 and the channel region 522 of the semiconductor film 52 are placed opposite to each other with the gate insulating film 50 interposed therebetween. Furthermore, the capacitor upper electrode 71 is formed at a separate position from the gate electrode 54 and opposite to the capacitor lower electrode 70 with the gate insulating film 50 interposed therebetween.
The interlayer insulating film 55 is formed on the gate electrode 54 and the gate insulating film 50. The interlayer insulating film 55 covers the gate electrode 54. The interlayer insulating film 55 and the gate insulating film 50 have the contact holes 62. The contact holes 62 penetrate through the interlayer insulating film 55 and the gate insulating film 50. The contact holes 62 thereby reach the semiconductor film 52.
The source electrode 56 and the drain electrode 57 are respectively filled in the contact holes 62. The source electrode 56 is connected with the source region 521. The drain electrode 57 is connected with the drain region 523.
In this way, the source electrode 56 and the drain electrode 57 extend from the top of the interlayer insulating film 55 to the semiconductor film 52. Thus, the source electrode 56 and the drain electrode 57 are exposed outside on the interlayer insulating film 55. Further, the passivation film 58 is formed on the interlayer insulating film 55 so as to cover the source electrode 56 and the drain electrode 57. The passivation film 58 may have through holes 63 for establishing a connection with the source electrode 56 and the drain electrode 57.
The structure of a capacitor in the display apparatus having such a structure is described hereinafter with reference to
As shown in
When a distance from the edge of the polycrystalline silicon electrode 18 to the edge of the gate metal electrode 17 is Y, a film thickness of the polycrystalline silicon electrode 18 is a, a film thickness of the gate insulating film 16 is b, and a film thickness of the gate metal electrode 17 is c, it is preferred to satisfy Y≧(a+b+c)/2. This is because, if the distance Y from the edge of the polycrystalline silicon electrode 18 to the edge of the gate metal electrode 17 is equal to or larger than a sum of ½ of a total of each film thickness, the gate metal electrode 17 can sufficiently cover the polycrystalline silicon electrode 18, which enables reduction of leakage current from the polycrystalline silicon electrode 18. Each film thickness preferably satisfies the relationship of c>a, b. Satisfying the relationship of c>a, b allows the edge of the polycrystalline silicon electrode 18 to be covered for sure. The film thickness of the polycrystalline silicon electrode 18 is 50 to 100 nm, for example, under the constraint of the irradiation energy when obtaining polycrystalline silicon from amorphous silicon by laser annealing. The film thickness b of the gate insulating film 16 is 50 to 150 nm, for example, under the constraint of transistor characteristics. The film thickness c of the gate metal electrode 17 is 200 to 400 nm, for example, for ion doping upon forming a source-drain region of a transistor, for use as a self-alignment mask upon ion implantation, and in consideration of a resistance of the gate electrode. The relationship of c>a,b may be satisfied based on those device characteristics, under process constraints and so on.
A method of manufacturing the display apparatus of the first embodiment having such a structure is described hereinafter with reference to
Referring first to
The amorphous silicon film 12 is molten by excimer laser annealing or the like and then cooled to be hardened, thereby forming a polycrystalline silicon film. After forming a resist pattern on the polycrystalline silicon film by photolithography, the polycrystalline silicon film is patterned into a polycrystalline silicon pattern 15 by dry etching as shown in
Referring next to
Referring then to
As described earlier, the gate metal electrode 17, which is one electrode of a capacitor, is in the inner position with respect to the polycrystalline silicon electrode 18, which is the other electrode of the capacitor, when viewed from the top in the display apparatus of the related art. In such a structure, leakage current from the polycrystalline silicon electrode is high, causing unstable storage characteristics.
To avoid this, the edge of the gate metal electrode 17 is placed in the outer position with respect to the edge of the polycrystalline silicon electrode 18 when viewed from the top as shown in
In this embodiment, the edge of the gate metal electrode 17 is located outside of the edge of the polycrystalline silicon electrode 18 when viewed from the top, so that the gate metal electrode 17 covers the polycrystalline silicon electrode 18 excluding the lead wiring portion thereof. It is thereby possible to reduce leakage current from the polycrystalline silicon electrode 18 with a very simple structure. This enables obtainment of stable storage characteristics of a capacitor, thus providing a display apparatus which exhibits stable display characteristics.
A display apparatus according to a second embodiment of the present invention is described hereinafter with reference to
The display apparatus of this embodiment shown
The manufacturing process of this embodiment is the same as that of the first embodiment up to the step of forming the gate insulating film 16. After forming the gate insulating film 16, the gate metal electrode 27 is formed. The gate metal electrode 27 is formed to have a shape which covers the polycrystalline silicon electrode 18 excluding the four corners.
According to this embodiment, the gate metal electrode 27 covers the polycrystalline silicon electrode 18 excluding the four corners. It is thereby possible to prevent the occurrence of electric field concentration at the corners of the polycrystalline silicon electrode 18, thus avoiding insulation failure. This enables obtainment of stable storage characteristics and insulation characteristics in a display apparatus.
A display apparatus according to a third embodiment of the present invention is described hereinafter with reference to
The display apparatus of this embodiment shown
The manufacturing process of this embodiment is the same as that of the first embodiment up to the step of forming the gate insulating film 16. After that, in the step of forming the gate metal electrode, the opening 38a is formed in a part of the gate metal electrode 37a as shown in
As shown in
According to this embodiment, an electrical connection between the polycrystalline silicon electrode 18 and the wiring layer is established by forming the opening 38a in a part of the gate metal electrode 37a or by forming the recess 38b in a part of the gate metal electrode 37b, rather than by forming a lead wiring directly from the polycrystalline silicon electrode 18. Further, a contact hole for connecting the polycrystalline silicon electrode 18 and the wiring layer is formed in the opening 38a or the recess 38b. It is thereby possible to obtain a capacitor which enables reduction of leakage current.
A TFT array substrate which includes the capacitor and the TFT described in the first to third embodiments has the advantages of reducing the leakage current from the polycrystalline silicon electrode and providing stable storage characteristics. It is thus suitable for use in a display apparatus. Specifically, it is applicable to a display apparatus which includes an active matrix array substrate having signal lines and scan lines intersecting with each other and a TFT with a capacity located in the vicinity of each intersection.
For example, it is applicable to a liquid crystal display apparatus in which an array substrate and a color filter substrate are attached to each other by a sealing material, with a liquid crystal material interposed therebetween. Further, it is also applicable to an EL display apparatus in which a self-luminous material and a counter electrode are placed on top of a drain electrode or a pixel electrode connected with the drain electrode on an array substrate. Furthermore, it is applicable to not only a TFT in a display area but also a TFT in a driver placed in the vicinity of the display area. In such a case, the TFT in the driver can be formed at the same time as the TFT in the display area.
From the invention thus described, it will be obvious that the embodiments of the invention may be varied in many ways. Such variation are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended for inclusion within the scope of the following claims.
Number | Date | Country | Kind |
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2006-238500 | Sep 2006 | JP | national |