Patent Application
20160322003
The present application claims priority to and incorporates by reference the entire contents of Japanese Patent Application No. 2015-094024 filed in Japan on May 1, 2015.
1. Field of the Invention
The present invention relates to a display apparatus and a method for driving the display apparatus.
2. Description of the Related Art
A display apparatus using a liquid crystal display element has an insufficient response speed of a liquid crystal for displaying a moving image and an unsatisfactory display quality of a moving image. Conventionally, therefore, moving image performance has been enhanced through insertion of a black display period in which black is displayed in each frame of a video signal with transmittance of a liquid crystal of approximately 0%. In addition, Japanese Laid-open Patent Publication No. 2013-168834 discloses a technique for further improving moving image performance in a projection apparatus using a liquid crystal display element, by inserting a black display period into a video signal and by controlling a diaphragm mechanism to be fully closed in the black display period in order to further improve display quality of a moving image.
However, there is a problem that a certain delay time (for example, several milliseconds) exists for a transition to the black display period, for example, for a transition of liquid crystal transmittance from a state of approximately 100% to a state of approximately 0% due to characteristics of a liquid crystal, and that a sufficient effect of insertion of the black display period is not obtained. Therefore, it is difficult to sufficiently improve display quality of a moving image through insertion of the black display period into a video signal.
In addition, since the diaphragm mechanism is fully closed in the black display period according to the technique of Japanese Laid-open Patent Publication No. 2013-168834, improvement in display quality of a moving image is expected. However, Japanese Laid-open Patent Publication No. 2013-168834 needs to open and close the diaphragm mechanism on a frame-by-frame basis, which could complicate control.
It is an object of the present invention to at least partially solve the problems in the conventional technology.
According to one embodiment of the present invention, there is provided a display apparatus comprising: a liquid crystal display control unit configured to control each of pixels of a display element in which each of the pixels is controlled to ON and OFF in accordance with a video signal to OFF in a predetermined first period including at least one of a front end and a rear end of a frame period of the video signal; and a light source control unit configured to stop light emission of a light source that emits light on the display element in a second period including the first period, wherein the first period is shorter than the frame period.
The above and other objects, features, advantages and technical and industrial significance of this invention will be better understood by reading the following detailed description of presently preferred embodiments of the invention, when considered in connection with the accompanying drawings.
Preferred embodiments of a display apparatus and a method for driving the display apparatus will be described in detail below with reference to the accompanying drawings. Specific numerical values, external appearance and structure, and the like illustrated in such embodiments are merely illustrative for facilitating understanding of the present invention, and do not limit the present invention unless otherwise specified. It is to be noted that elements having no direct relation with the present invention omit detailed description and illustration.
The projection apparatus according to a first embodiment will be described.
A video signal is input into the video processor 110. Here, the video signal is a digital video signal for displaying a moving image with a frame image updated in a predetermined frame cycle (for example, 60 frames per second). The video signal is not limited to this example, and for example, the video processor 110 may convert an analog video signal into a digital video signal. For purposes of description, the video signal can represent 13-level gradation from a gradation value “0” to gradation value “12” for each of the pixels. Here, the gradation value “0” and gradation value “12” correspond to black display and white display, respectively, and the gradation value “1” through gradation value “11” correspond to halftone display of brightness according to the gradation value.
The video processor 110 extracts a frame synchronization signal Vsync indicating a front of a frame, and gradation information Grad of each pixel from the input video signal. The gradation information Grad includes the gradation value (luminance value) of a pixel. The video processor 110 supplies the extracted gradation information Grad to the drive unit 111. In addition, the video processor 110 supplies the extracted frame synchronization signal Vsync to the subframe production unit 112.
The subframe production unit 112 is a divided period production unit that produces divided periods obtained through equal division of a one-frame period in accordance with the frame synchronization signal Vsync supplied from the video processor 110. These divided periods are hereinafter referred to as subframes. In this example, the subframe production unit 112 equally divides the one-frame period, for example, by using a number of divisions of 12 to produce 12 subframes from SF1, SF2, . . . , SF12.
The subframe production unit 112 generates, for example, a subframe synchronization signal SFsync that indicates timing of the divided each subframe SF1, SF2, . . . , SF12, and then outputs the generated subframe synchronization signal SFsync together with the frame synchronization signal Vsync. The frame synchronization signal Vsync and subframe synchronization signal SFsync that are output from the subframe production unit 112 are supplied to each of the drive unit 111 and the light source control unit 113.
The light source control unit 113 generates a light source control signal for controlling light emission of the light source 120 based on the frame synchronization signal Vsync and subframe synchronization signal SFsync supplied from the subframe production unit 112. The light source 120 is, for example, a semiconductor laser, and at least light emission and stop of light emission of a laser beam is controlled in accordance with the light source control signal supplied from the light source control unit 113. In addition, light emission timing of the light source 120 is controllable at least on an aforementioned subframe basis in accordance with the light source control signal.
It is to be noted that the light source 120 may be a light source of another type as long as light emission timing is controllable on a subframe basis and a response speed is high. For example, an LED (Light Emitting Diode) may be used as the light source.
Meanwhile, the drive unit 111 generates a driving signal for driving the display element 121 in accordance with the gradation information Grad for each pixel supplied from the video processor 110, and the frame synchronization signal Vsync and subframe synchronization signal SFsync supplied from the subframe production unit 112. The driving signal is supplied to the display element 121.
The display element 121 includes pixels arranged in a matrix, and modulates and emits light incident from the light source 120 for each pixel in accordance with the driving signal supplied from the drive unit 111, based on the video signal. According to the first embodiment, a liquid crystal display element using characteristics of a liquid crystal is used as the display element 121. The liquid crystal display element includes a liquid crystal inserted between a pixel electrode for each pixel and a common electrode common to respective pixels. The liquid crystal display element displays a video by changing transmittance of the liquid crystal to light of a specific polarization direction, through application of a voltage to each pixel according to the video signal by the pixel electrode.
According to the first embodiment, a reflective liquid crystal display element is used as the display element 121. In the reflective liquid crystal display element, light emitted on an incident plane travels through a liquid crystal layer from the incident plane, is emitted on a reflection plane, is reflected by the reflection plane, travels through the liquid crystal layer again, and is emitted from the incident plane to outside. In order to change a polarization state of the incident light for emission, polarization separation of the incident light and emitted light are performed by using a polarization beam splitter and the like by the reflective liquid crystal display element.
Next, control according to the first embodiment will be more specifically described. According to the first embodiment, the drive unit 111 drives the display element 121 under a digital drive scheme to control display made by the display element 121. That is, the drive unit 111 functions as a liquid crystal display control unit that controls display made by the display element 121 using a liquid crystal. Under the digital drive scheme according to the first embodiment, the drive unit 111 controls each pixel in two states, an ON state and an OFF state. Here, the ON state is, for example, a state where transmittance of a liquid crystal is highest, and is a state where incidence of white light to a liquid crystal produces display of approximate white (white display). Meanwhile, the OFF state is, for example, a state where transmittance of a liquid crystal is lowest, and is a state where incidence of white light to a liquid crystal produces display of approximate black (black display). In addition, for a certain pixel, among subframes within a one-frame period, the drive unit 111 selects the number of continuous subframes according to a gradation value of the pixel from a front end or rear end of the one-frame period, controls the pixel to an ON state in the selected subframes, and controls the pixel to an OFF state in other subframes. Thus, the drive unit 111 represents gradation in the pixel.
The first embodiment controls light emission and stop of light emission of the light source 120 within the one-frame period. At this time, in a predetermined period including either one of the front end and rear end of the one-frame period, the drive unit 111 causes the light source 120 to stop light emission, and the drive unit 111 causes the light source 120 to emit light in a period other than the predetermined period. In this way, providing a period in which light emission of the light source 120 is stopped in the front end or rear end of the one-frame period makes it possible to mask a non-black display state caused by a delay in response of the liquid crystal when the liquid crystal transitions to a black display state.
Light source control according to the first embodiment will be more specifically described with reference to a time chart of
TIME CHART B in
TIME CHART D in
Here, the digital drive scheme applicable to the first embodiment will be schematically described.
The drive unit 111 selects the consecutive subframes the number of which depends on the gradation value of the pixel from the front end of the frame period, and controls the pixel to an ON state in the selected subframes. In
For example, when the gradation value of a certain pixel is “3”, the drive unit 111 selects three subframes from the front subframe SF1 of the frame period (subframes SF1, SF2, and SF3). The drive unit 111 then controls the pixel to an ON state in the selected subframes. Meanwhile, the drive unit 111 controls the pixel to an OFF state in other nine subframes (subframes SF4 to SF12).
For example, when the gradation value of a certain pixel is “12”, the drive unit 111 selects 12 subframes from the front subframe SF1 of the frame period (subframes SF1 to SF12). The drive unit 111 then controls the pixel to an ON state in the selected subframes. In this case, there exists no subframe to be controlled to an OFF state. Furthermore, for example, when the gradation value of a certain pixel is “0”, the drive unit 111 controls the pixel to an OFF state in all the subframes (subframes SF1 to SF12) within the one-frame period. In this case, there exists no subframe to be controlled to an ON state.
Thus, according to the existing technique, the subframes to undergo ON control and OFF control are allocated in advance for each gradation.
Next, the digital drive scheme according to the first embodiment will be described. First, characteristics of a liquid crystal will be described with reference to
Furthermore, at time t1 when the liquid crystal becomes in an ON state, for example, application of the voltage to the pixel electrode is stopped to control the liquid crystal to an OFF state. In this case, transmittance of the liquid crystal becomes approximately 0% at time t2 when predetermined time elapses from time t1.
For example, consider a case where a period from time t0 to time t2 is the one-frame period, and where the liquid crystal is controlled so that transmittance becomes saturated at time t1. In this case, a period from time t1 to time t2 during which transmittance decreases from the saturation state to approximately 0% (referred to as a black transition period) is typically several milliseconds. Meanwhile, when the video signal is, for example, 60 frames/sec, the one-frame period is 1/60 seconds, that is, approximately 16.7 msec. For example, when the black transition period is 2 msec, the black transition period will account for 12% of the one-frame period, which could degrade display quality of a moving image.
Therefore, in a period including this black transition period, the first embodiment performs black display insertion for controlling all the pixels to an OFF state, and stops light emission of the light source 120. A stop of light emission of the light source 120 provides black display in a state where an influence of the characteristics of a liquid crystal is inhibited, which improves display quality of a moving image. Here, as the light source 120, it is preferable to select a light source with response time at least shorter than the black transition period of a liquid crystal.
Returning to
In the example of TIME CHART C in
According to the first embodiment, furthermore, the digital drive pattern is a pattern in which the black display period is inserted.
Therefore, according to the first embodiment, as illustrated in
In other words, according to the first embodiment, the one-frame period is divided into the subframes SF1 to SF12 including the black transition period, and the subframes SF1 to SF9 that do not include the black transition period are set as a gradation representation period to which the gradation values are allocated.
Control of the projection unit 122 according to the first embodiment will be more specifically described with reference to
It is assumed here that the video signal in which each pixel has the gradation value illustrated in
Human visual characteristics have a tendency to have difficulty in recognizing a change in a bright image (image with a great gradation value) as compared with a change in a dark image (image with a small gradation value). Therefore, as described above, even if the gradation value of the pixel having the gradation value that exceeds the drivable upper limit gradation value is changed to this upper limit gradation value, this is unlikely to be a factor in significant degradation of display quality.
TIME CHART A in
With reference to
In addition, since the changed gradation value of pixel (x4, y0) is “9”, the drive unit 111 sets the subframes SF1 to SF9 to an ON section 130.
TIME CHART B in
Although light emission of the light source 120 is stopped in the predetermined period including the rear end of the one-frame period in the above case, the predetermined period is not limited to this example. That is, the predetermined period for stopping light emission of the light source 120 may include at least one of the front end and rear end of the one-frame period.
Next, a second embodiment will be described.
The video processing and drive unit 200 generates, for example, a light source control signal for controlling the light source 210, and a driving signal for driving the display element 220 based on a video signal supplied from a video output apparatus 101.
The light source 210 corresponds to the light source 120 of
The polarization separator 212 includes a polarization separating plane for separating the P-polarized light and the S-polarized light included in the light, and the polarization separating plane transmits the P-polarized light and reflects the S-polarized light. As the polarization separator 212, a polarizing beam splitter can be used. The light incident in the polarization separator 212 from the illumination optical system 211 is separated into the P-polarized light and the S-polarized light by the polarization separating plane. The P-polarized light passes through the polarization separating plane, and the S-polarized light is reflected by the polarization separating plane, and is emitted on the display element 220.
The display element 220 corresponds to the display element 121 of
The S-polarized light incident on the display element 220 travels through the counter electrode 2201 and the liquid crystal layer 2202, and is incident on the pixel electrode unit 2203. The S-polarized light is then reflected by the pixel electrode unit 2203, travels through the liquid crystal layer 2202 and the counter electrode 2201 again, and is emitted from the display element 220. At this time, the liquid crystal layer 2202 modulates the S-polarized light that is incident and reflected in accordance with the voltage applied between the counter electrode 2201 and the pixel electrode of the pixel electrode unit 2203 in response to the driving signal. The S-polarized light incident on the counter electrode 2201 is modulated during a process of reflection by the pixel electrode unit 2203 and emission from the counter electrode 2201. The S-polarized light is then emitted from the counter electrode 2201 as light including the P-polarized light and the S-polarized light.
Returning to
In a similar manner to the aforementioned first embodiment, it is assumed below that the gradation is represented by 10-level gradation of the gradation value “0” to “9”, that the frame period is equally divided into 12 divided periods including a black transition period in the display element 220, and that 12 subframes SF1 to SF12 are produced.
In
The pixel electrode unit 2203 includes a source driver 33, a gate driver 34, and respective pixel circuits 2210. Here, the source driver 33 and the gate driver 34 may be provided outside of the pixel electrode unit 2203.
In the pixel electrode unit 2203, pixel circuits 2210 are arranged in a matrix, are connected to column data lines D0, D1, . . . , Dn in a column direction, respectively, and are connected to row selection lines W0, W1, . . . , Wm in a row direction, respectively. Each of the column data lines D0, D1, . . . , Dn is connected to the source driver 33. Each of the row selection lines W0, W1, . . . , Wm is connected to the gate driver 34.
The memory control unit 28 is supplied with a frame synchronization signal Vsync and a subframe synchronization signal SFsync from the subframe data production unit 26 described later. In addition, the memory control unit 28 stores subframe data (to be described later) of each subframe SF produced by the subframe data production unit 26 in the frame buffer 29 divided for each subframe SF in response to the subframe synchronization signal SFsync. The frame buffer 29 has double-buffer structure including a first frame buffer and a second frame buffer. The memory control unit 28 can read the subframe data from the first frame buffer while storing video signal data in the second frame buffer.
The drive control unit 31 is supplied with the frame synchronization signal Vsync and the subframe synchronization signal SFsync from the subframe data production unit 26. The drive control unit 31 controls timing of processing for each subframe SF and the like. In accordance with these synchronization signals, the drive control unit 31 provides transmission commands to the data transfer unit 30, and controls the source driver 33 and gate driver 34. More specifically, in accordance with the frame synchronization signal Vsync and the subframe synchronization signal SFsync, the drive control unit 31 generates a vertical start signal VST, a vertical shift clock signal VCK, a horizontal start signal HST, and a horizontal shift clock signal HCK.
The vertical start signal VST and the horizontal start signal HST specify front timing of the subframe SF, and front timing of the line, respectively. The vertical shift clock signal VCK specifies the row selection lines W0, W1, . . . , Wm. Meanwhile, the horizontal shift clock signal HCK performs specification corresponding to the column data lines D0, D1, . . . , Dn. The vertical start signal VST and the vertical shift clock signal VCK are supplied to the gate driver 34. The horizontal start signal HST and the horizontal shift clock signal HCK are supplied to the source driver 33.
In accordance with control by the drive control unit 31, the data transfer unit 30 commands the memory control unit 28 to read the subframe data of the specified subframe SF from the frame buffer 29. The data transfer unit 30 receives, from the memory control unit 28, the subframe data read from the frame buffer 29, and transfers the received subframe data to the source driver 33 in accordance with control by the drive control unit 31, for example, on a line-by-line basis.
Every time the source driver 33 receives the subframe data of one line from the data transfer unit 30, the source driver 33 transfers the subframe data to the corresponding pixel circuits 2210 simultaneously using the column data lines D0, D1, . . . , Dn. The gate driver 34 activates the row selection line of the row specified by the vertical start signal VST and vertical shift clock signal VCK supplied from the drive control unit 31 among the row selection lines W0, W1, . . . , Wm. This allows transfer of the subframe data of each pixel to each of the pixel circuits 2210 of all the columns of the specified row.
Furthermore, the drive control unit 31 generates a voltage timing signal based on the frame synchronization signal Vsync and the subframe synchronization signal SFsync. The voltage timing signal is supplied to the voltage control unit 32. In addition, a zero voltage Vzero with a voltage value of 0 V and the saturation voltage Vw are supplied to the voltage control unit 32. With timing indicated by the voltage timing signal, the voltage control unit 32 supplies voltages based on the zero voltage Vzero and saturation voltage Vw to respective pixel circuits 2210 as a voltage V0, which is a blanking voltage, and a voltage V1, which is a drive voltage. In addition, the voltage control unit 32 outputs a common voltage Vcom to be supplied to the counter electrode 2201. Here, the blanking voltage and the drive voltage correspond to a voltage for controlling a pixel to an OFF state and a voltage for controlling a pixel to an ON state, respectively.
Next, an operation of the video processing and drive unit 200 will be described. The digital video signal is supplied to the signal conversion unit 21. The signal conversion unit 21 both extracts the frame synchronization signal Vsync from the supplied video signal, and converts the video signal into video signal data in a predetermined number of bits for output. The signal conversion unit 21 supplies the extracted frame synchronization signal Vsync to the error diffusion unit 23, the frame rate control unit 24, the limiter unit 25, and the subframe data production unit 26, respectively.
In addition, the video signal data that is output from the signal conversion unit 21 undergoes predetermined signal processing by the error diffusion unit 23, the frame rate control unit 24, and the limiter unit 25, and is then supplied to the subframe data production unit 26.
With reference to
The signal conversion unit 21 converts the input N-bit video signal data into (M+F+D)-bit data having a larger number of bits. Here, a value M represents the number of bits corresponding to the number of subframes SF represented in binary, a value D represents the number of bits to be required for interpolation by the error diffusion unit 23, and a value F represents the number of bits to be required for interpolation by the frame rate control unit 24. Here, each of the value N, value M, value F, and value D is an integer equal to or greater than 1. In the example of
The signal conversion unit 21 performs bit number conversion processing, for example, using a look-up table. In general, as described above, a display has input-output characteristics according to a gamma curve of a gamma value γ=2.2. Therefore, the video signal that is output from the video output apparatus 101 is a signal corrected by the gamma curve according to the gamma value of reciprocal of the gamma value of the display so as to obtain linear gradation representation when displayed on the display.
The signal conversion unit 21 converts the input video signal data by using the look-up table adjusted in advance so as to bring the input-output characteristics of the projection unit 240 close to standard characteristics, that is, the characteristics of the gamma curve of the gamma value γ=2.2. This conversion processing is referred to as calibration. At this time, using the look-up table, the signal conversion unit 21 converts the N-bit video signal data into the (M+F+D)-bit video signal data for output. In this example where the value N=8, value D=4, value F=2, and value M=4, the signal conversion unit 21 converts 8-bit video signal data into 10-bit video signal data for output.
The video signal data converted into (M+F+D) bits by the signal conversion unit 21 is converted into (M+F)-bit data by the error diffusion unit 23 diffusing lower-D-bit information into nearby pixels. In this example where the value N=8, value D=4, value F=2, and value M=4, the error diffusion unit 23 diffuses lower-4-bit information of the 10-bit video signal data of each pixel that is output from the signal conversion unit 21 into nearby pixels, and quantizes the 10-bit video signal data into upper-6-bit data.
An error diffusion method is a method for compensating shortage of gradation by diffusing an error (display error) between the video signal to be displayed and an actually displayed value into nearby pixels. According to the second embodiment, lower 4 bits of the video signal to be displayed are defined as a display error, 7/16 of the display error is added to a pixel right neighbor to the noted pixel, 3/16 of the display error is added to a lower left pixel, 5/16 of the display error is added to a pixel directly under the noted pixel, and 1/16 of the display error is added to a lower right pixel. This processing is performed on each pixel, for example, from left to right within one frame of video, and this processing is performed on each line from top to bottom within one frame of video.
An operation of the error diffusion unit 23 will be described in more detail. While the noted pixel diffuses the error as described above, the error diffused by an immediately preceding noted pixel is added to the noted pixel. The error diffusion unit 23 first reads, from an error buffer, the error diffused from the immediately preceding noted pixel, and adds the read error to the noted pixel of the input 10-bit video signal data. The error diffusion unit 23 divides the 10-bit noted pixel to which a value of the error buffer is added into upper 6 bits and lower 4 bits.
A value of the divided lower four bits, which is denoted as (lower four bits, display error), is as follows.
The display error corresponding to the value of the divided lower 4 bits is added to the error buffer for storage. In addition, the value of the divided lower 4 bits is compared with a threshold, and when the value is larger than “1000” in binary notation, “1” is added to the value of the upper 6 bits. Then, upper 6-bit data is output from the error diffusion unit 23.
The video signal data converted into (M+F) bits by the error diffusion unit 23 is input into the frame rate control unit 24. The frame rate control unit 24 performs frame control processing for displaying a pseudo gradation, by setting p frames (p is an integer equal to or greater than 2) for one-pixel display of the display element 220 as one period, performing ON display in q frames (q is an integer of p>q>0) of the period, and performing OFF display in remaining (p-q) frames.
In other words, the frame rate control processing is processing for making a pseudo intermediate gradation by using rewriting of a screen and an afterimage effect of a retina. For example, by rewriting a certain pixel alternately with a gradation value “0” and a gradation value “1” for each frame, the pixel appears to have a gradation value intermediate between the gradation value “0” and the gradation value “1” to human eyes. Then, control of such alternate rewriting of the gradation value “0” and the gradation value “1”, for example, for four frames as one set, enables pseudo representation of three-level gradation between the gradation value “0” and gradation value “1”.
The frame rate control unit 24 includes a frame rate control table illustrated in
Each column of the large matrix is specified by a lower 2-bit value in a counter value of the frame counter. Each row of the large matrix is specified by a lower 2-bit value in the 6-bit video signal data that is input into the frame rate control unit 24. Each column and each row of each small matrix are specified based on positional information of a pixel within a display area, that is, coordinates of the pixel. More specifically, each column of each small matrix is specified by a lower 2-bit value of an X coordinate of the pixel, and each row is specified by a lower 2-bit value of a Y coordinate of the pixel.
The frame rate control unit 24 specifies a position within the frame rate control table from a lower F-bit value of supplied (M+F)-bit video signal data, positional information on the pixel, and frame count information. The frame rate control unit 24 then adds a value (value “0” or value “1”) at the position to upper M bits. Thereby (M+F)-bit video signal data is converted into M-bit data.
In this example where the value F=2 and value M=4, the 6-bit video signal data that is output from the error diffusion unit 23 is input into the frame rate control unit 24. The frame rate control unit 24 acquires the value “0” or value “1” from the frame rate control table, based on the lower 2-bit information of this video signal data, positional information in the display area, and frame counter information. The frame rate control unit 24 then adds the acquired value to an upper 4-bit value separated from 6 bits of the input video signal data.
More specifically, the frame rate control unit 24 divides the input six-bit video signal data (pixel data) into upper 4-bit data and lower 2-bit data. The frame rate control unit 24 specifies a position in the large matrix and small matrix of the frame rate control table of
Thus, the frame rate control unit 24 controls on/off of the pixel for each gradation on a pixel block basis. This enables further representation of pseudo gradation between two continuous gradations.
With reference to
In addition, the subframe data production unit 26 generates the subframe synchronization signal SFsync based on the supplied frame synchronization signal Vsync. The subframe data production unit 26 supplies the frame synchronization signal Vsync and the subframe synchronization signal SFsync to the memory control unit 28 and the drive control unit 31, and to the light source control unit 230.
According to the second embodiment, contrary to the example of the first embodiment described with reference to
According to the second embodiment, the drive gradation table 27 stores the value “0” that represents OFF control of the pixel in association with respective gradation values of the subframes SF1 to SF3.
Thus, according to the second embodiment, in a similar manner to the aforementioned first embodiment, the subframes for performing ON and OFF control are allocated in advance for each gradation.
With reference to the drive gradation table 27 in accordance with the video signal data, the subframe data production unit 26 converts data of each pixel into data of a value “0” or value “1” (hereinafter referred to as 0/1 data) for each subframe SF, and produces the subframe data.
For example, with reference to the aforementioned
TIME CHART C in
In TIME CHART C in
According to the second embodiment, the subframe data of the subframes SF1 to SF3 illustrated by hatching in TIME CHART D in
With reference to
As an example, the data transfer unit 30 transfers the subframe data to the source driver 33 on a line-by-line basis in accordance with control by the drive control unit 31. In accordance with control by the drive control unit 31, the source driver 33 writes the transferred subframe data, for example, in registers respectively corresponding to the data lines D0, D1, . . . , Dn for each pixel for holding. Here, the data to be held for each pixel is 0/1 data of a value “0” or value “1” obtained through conversion of the pixel gradation value in accordance with the drive gradation table 27.
In addition, in accordance with control by the drive control unit 31, the gate driver 34 sequentially selects the row selection lines W0, W1, . . . , Wm, with transfer timing of the subframe data on a line-by-line basis. This causes the sample and hold unit 16 of each pixel circuit 2210 selected by the row selection lines W0, W1, . . . , Wm to acquire and hold 0/1 data of each pixel held in the source driver 33. This causes the sample and hold units 16 of all the pixel circuits 2210 included in the pixel electrode unit 2203 to hold 0/1 data of the pixels in the period WC, respectively.
In the period DC, all the pixel circuits 2210 included in the pixel electrode unit 2203 are driven. With reference to
After the period WC ends, the period DC, which is the driving period, starts. In accordance with control by the drive control unit 31, the voltage control unit 32 drives each pixel circuit 2210 in each of a period DC #1 and DC #2 obtained through equal division of the period DC. In the period DC #1, the voltage control unit 32 sets the voltage V1 to the saturation voltage Vw, and sets the voltage V0 and common voltage Vcom to earth potential. In the period DC #2, contrary to the period DC #1, the voltage control unit 32 sets the voltage V1 to earth potential, and sets the voltage V0 and common voltage Vcom to the saturation voltage Vw.
In the pixel circuit 2210, when 0/1 data held in the sample and hold unit 16 is a value “0”, the voltage selection circuit 17 selects the voltage V0 as the voltage to be applied to the pixel electrode 2204. In the period DC #1, a voltage Vpe of the pixel electrode 2204 and the common voltage Vcom to be applied to the counter electrode 2201 are earth potential. Therefore, the voltage to be applied to the liquid crystal layer 2202 becomes 0 [V], and a drive state of the liquid crystal layer 2202 becomes in a blanking state (OFF state).
In the pixel circuit 2210, when 0/1 data held in the sample and hold unit 16 is a value “1”, the voltage selection circuit 17 selects the voltage V1 as the voltage to be applied to the pixel electrode 2204. In the period DC #1, the voltage Vpe of the pixel electrode 2204 becomes the saturation voltage Vw, and the common voltage Vcom to be applied to the opposite electrode 2201 becomes earth potential. Therefore, the voltage to be applied to the liquid crystal layer 2202 becomes the positive saturation voltage Vw with respect to potential of the counter electrode 2201, and the liquid crystal layer 2202 becomes in a drive state (ON state). In addition, in the period DC #2, the voltage Vpe of the pixel electrode 2204 becomes earth potential, and the common voltage Vcom to be applied to the counter electrode 2201 becomes the saturation voltage Vw (saturation voltage+Vw). The voltage to be applied to the liquid crystal layer 2202 becomes the negative saturation voltage Vw (saturation voltage−Vw) with respect to potential of the counter electrode 2201, and the liquid crystal layer 2202 becomes in a drive state (ON state).
By applying the voltages with an identical absolute value and different polarity (saturation voltage +Vw and −Vw) to the liquid crystal layer 2202 for an identical period, the voltage applied to the liquid crystal layer 2202 becomes 0 [V] on average for a long time, which may prevent burn-in of the liquid crystal.
Returning to description of
As an example, it is assumed that the light source 210 emits light in a high (H) state of the light source control signal, and that the light source 210 stops light emission in a low (L) state. In this case, in accordance with the frame synchronization signal Vsync and subframe synchronization signal SFsync supplied from the subframe data production unit 26, as illustrated in TIME-CHART F in
Thus, even light emission of the light source 210 is stopped in the predetermined period including the front end of the frame period, in a similar manner to the aforementioned first embodiment, a temporal section is masked including the black transition period in which control of the pixel is switched from an ON state to an OFF state, for example, due to transition from the subframe SF12 of the immediately preceding frame period to the current subframe SF1. This may provide black display more securely in the black transition period, and may improve display quality of a moving image.
The present invention produces an effect of enabling improvement in display quality of a moving image made by a liquid crystal display element.
Although the invention has been described with respect to specific embodiments for a complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modifications and alternative constructions that may occur to one skilled in the art that fairly fall within the basic teaching herein set forth.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2015-094024 | May 2015 | JP | national |
