Korean Patent Application No. 10-2018-0045740, filed on Apr. 19, 2018, in the Korean Intellectual Property Office, and entitled: “Display Apparatus and Method of Manufacturing the Same,” is incorporated by reference herein in its entirety.
One or more embodiments relate to a display apparatus and a method of manufacturing the same.
An electronic apparatus, e.g., a display apparatus, may include a plurality of circuit wirings and a plurality of electronic elements connected to the plurality of circuit wirings, and may operate by receiving an electrical signal. A conductive adhesive or a conductive film may be used to electrically connect the plurality of circuit wirings to the electronic elements.
According to one or more embodiments, a display apparatus may include a substrate including a display area and a non-display area around the display area, a plurality of pads located on the non-display area of the substrate and connected to signal lines of the display area, and protrusions located between the plurality of pads.
The display apparatus may further include an integrated circuit including a plurality of bumps connected to the plurality of pads.
The display apparatus may further include a conductive adhesive member configured to electrically connect the plurality of pads and the plurality of bumps.
The conductive adhesive member may include conductive particles.
The protrusions may have a height greater than a diameter of the conductive particles.
The protrusions may contact the conductive adhesive member.
The display apparatus may further include a plurality of fan-out lines configured to connect the signal lines to the plurality of pads.
The protrusions may include the same material as a material of one of a plurality of insulating layers of the display area.
The plurality of pads may include the same material as a material of one electrode of a thin-film transistor of the display area.
A width of the protrusions may be less than an interval between the plurality of pads.
The display apparatus may further include a thin-film transistor located on the display area, a first insulating layer covering the thin-film transistor, and a second insulating layer having an opening through which a part of a first electrode on the first insulating layer is exposed and covering an edge of the first electrode, wherein the protrusions include the same material as a material of the first insulating layer and the second insulating layer.
According to one or more embodiments, a method of manufacturing a display apparatus may include providing a substrate including a display area and a non-display area around the display area, forming a plurality of pads connected to signal lines of the display area on the non-display area of the substrate, and forming protrusions between the plurality of pads.
The method may further include connecting an integrated circuit including a plurality of bumps corresponding to the plurality of pads, to the plurality of pads.
The method may further include providing a conductive adhesive member between the plurality of pads and the integrated circuit.
The conductive adhesive member may include conductive particles.
The protrusions may have a height greater than a diameter of the conductive particles.
The protrusions may contact the conductive adhesive member.
A width of the protrusions may be less than an interval between the plurality of pads.
The protrusions may be formed at the same time as one of a plurality of insulating layers of the display area is formed.
The plurality of pads may be formed at the same time as one electrode of a thin-film transistor of the display area is formed.
Features will become apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which:
Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey exemplary implementations to those skilled in the art.
In the drawing figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when a layer or element is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Like reference numerals refer to like elements throughout.
It will be understood that although the terms “first”, “second”, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These elements are only used to distinguish one element from another. As used herein, the singular forms “a”, “an”, and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It will be further understood that the terms “comprises” and/or “comprising” used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.
As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list.
Referring to
On the display area DA, each of the plurality of pixels PX is connected to a corresponding data line DL and a corresponding scan line SL (
As illustrated in
On the mounting area 140, a driving unit 200 (
The signal pads 70 may include a transparent conductive film, e.g., indium tin oxide (ITO) or indium zinc oxide (IZO), or a metal or an alloy, e.g., aluminum or silver. However, the signal pads 70 are not limited to the above materials and may include any of various conductive materials having corrosion resistance.
Positions and number of lines for connecting elements in the display apparatus 10 and the signal pads 70, e.g., positions and number of the fan-out lines 40, are shown in
As further illustrated in
Examples of the display apparatus 10 may include various display apparatuses, e.g., an organic light-emitting display apparatus, a liquid-crystal display apparatus, and a field-emission display (FED) apparatus. While the following will be described assuming that the display apparatus 10 is an organic light-emitting display apparatus, embodiments are not limited thereto, i.e., the description may apply to other display apparatuses.
Referring to
The first transistor T1 includes a gate electrode connected to the scan line SL, a first electrode connected to the data line DL, and a second electrode. The second transistor T2 includes a gate electrode connected to the second electrode of the first transistor T1, a first electrode receiving a first power supply voltage ELVDD, and a second electrode connected to the light-emitting device ED. The capacitor Cst includes a first electrode connected to the second electrode of the first transistor T1 and the gate electrode of the second transistor T2, and a second electrode receiving the first power supply voltage ELVDD.
The light-emitting device ED may be connected to the pixel circuit through the second transistor T2. The light-emitting device ED may be an organic light-emitting diode (OLED). The organic light-emitting device ED includes a first electrode connected to the second electrode of the second transistor T2, a second electrode receiving a second power supply voltage ELVSS, and an emission layer between the first electrode and the second electrode. The first power supply voltage ELVDD may be higher than the second power supply voltage ELVSS.
Although one pixel PX includes two transistors and one capacitor in
Referring to
For example, as illustrated in
The conductive adhesive member AM may include a polymer resin and the conductive particles CP dispersed in the polymer resin. The conductive particles CP may be conductive particles of a tin alloy formed by alloying tin with at least one of, e.g., silver, copper, bismuth, zinc, and indium. Alternatively, the conductive particles CP may be conductive particles of an indium alloy formed by alloying indium with at least one of, e.g., silver, copper, bismuth, zinc, and tin. The conductive particles CP may be conductive particles having a low melting temperature. For example, a melting temperature of the conductive particles CP including at least one of tin and indium may be equal to or greater than 60° C. and equal to or less than 200° C.
The conductive adhesive member AM may further include a thermoplastic resin. The thermoplastic resin may be a vinyl acetate resin, a styrene resin, an ethylene-vinyl acetate copolymer resin, or a styrene-butadiene copolymer resin. Alternatively, the thermoplastic resin may be a polyester resin.
As further illustrated in
The protrusions 90 may guide the conductive particles CP of the conductive adhesive member AM to be located adjacent to the signal pads 70. As the conductive particles CP are located adjacent to the signal pads 70, a short-circuit between the signal pads 70 may be reduced.
The protrusions 90 may be formed of an insulating material. The protrusions 90 may be formed of the same material as that of at least one of various insulating layers formed on the display area DA, as will be discussed in detail with reference to A
In detail, as illustrated in
As illustrated in
The conductive particles CP included in the conductive adhesive member AM are irregularly arranged, without having a constant arrangement or interval. Accordingly, although a density of the conductive particles CP may be controlled, it is difficult to control an interval between the conductive particles CP. Also, the risk of a short-circuit between the signal pads 70 may be high when the density of the conductive particles CP is high, and driving may not be performed when the density of the conductive particles CP is low. Also, a short-circuit between the signal pads 70 may occur due to dielectric breakdown (DB) according to an operating voltage.
Therefore, according to example embodiments, the protrusions 90 are positioned between adjacent signal pads 70 to control the flow of the conductive particles CP while securing a minimum distance between the signal pads 70 for preventing DB. That is, the height of the protrusions 90 increases a flow path of the conductive particles CP between the signal pads 70, thereby minimizing a risk for short-circuit between the signal pads 70.
In detail, when there are no protrusions between adjacent signal pads, short-circuit may occur between the adjacent signal pads due to conductive particles of the conductive adhesive member. That is, when a distance between adjacent signal pads is small, a relatively small number of conductive particles may concentrate in a space between the adjacent signal pads and electrically connect therebetween, e.g., based on a shortest distance along the first direction between the adjacent signal pads.
In contrast, when the protrusions 90 according to an example embodiment are positioned between adjacent signal pads 70 and extend substantially above the adjacent signal pads 70, the number of conductive particles CP required to electrically connect the adjacent signal pads 70 over the height of the protrusions 90 is substantially increased. Accordingly, a potential for short-circuit between the adjacent signal pads 70 may be substantially reduced. That is, since the protrusions 90 according to an embodiment increase a path through which the conductive particles CP flow between the signal pads 70 (e.g., the path of the conductive particles CP over the protrusion 90 in
According to an embodiment, it is not necessary to change a size of the conductive particles CP according to a mode change by changing a height and/or a length of the protrusions 90 according to a model of the display apparatus 10.
Referring to
The pixel circuit including a thin-film transistor TFT and the light-emitting device ED connected to the thin-film transistor TFT may be provided on the display area DA of the substrate 100. The thin-film transistor TFT may be the first transistor T1 or the second transistor T2 of
The thin-film transistor TFT may include an active layer 151, a gate electrode 152, a source electrode 153, and a drain electrode 154. A first insulating layer 102 may be located between the active layer 151 and the gate electrode 152. A second insulating layer 103 and a third insulating layer 104 may be located between the gate electrode 152, and the source electrode 153 and the drain electrode 154. Each of the source electrode 153 and the drain electrode 154 may have a single or multi-layer structure formed of a conductive material having high conductivity. For example, the source electrode 153 and the drain electrode 154 may include the same material as that of the gate electrode 152. The source electrode 153 and the drain electrode 154 may be respectively connected to a source region and a drain region of the active layer 151 through contact holes formed in the first insulating layer 102, the second insulating layer 103, and the third insulating layer 104.
The light-emitting device ED may be connected to the thin-film transistor TFT with a fourth insulating layer 105 therebetween. The light-emitting device ED may include a first electrode 161, a second electrode 163 facing the first electrode 161, and an intermediate layer 162 located between the first electrode 161 and the second electrode 163.
The first electrode 161 may be electrically connected to the source electrode 153 or the drain electrode 154 (the drain electrode 154 in
The second electrode 163 may include any of various conductive materials. For example, the second electrode 163 may include a transflective film including at least one of, e.g., lithium (Li), calcium (Ca), lithium fluoride (LiF), aluminum (Al), magnesium (Mg), and silver (Ag) or may include a transparent metal oxide, e.g., ITO, IZO, or ZnO, and may be formed to have a single or multi-layer structure.
The plurality of fan-out lines 40 may be formed on the fan-out portion 120 of the non-display area NA. The fan-out lines 40 may include first fan-out lines 40a formed between the first insulating layer 102 and the second insulating layer 103 and second fan-out lines 40b formed between the second insulating layer 103 and the third insulating layer 104. The first fan-out lines 40a and the second fan-out lines 40b may be formed of the same material or different materials. For example, the first fan-out lines 40a and the second fan-out lines 40b may be formed of the same material as that of the gate electrode 152 of the thin-film transistor TFT. Since a distance (interval) between adjacent fan-out lines located on different layers may be reduced by locating the first fan-out lines 40a and the second fan-out lines 40b on different layers with the second insulating layer 103 therebetween, a short-circuit between the fan-out lines 40 may be prevented while more fan-out lines 40 are formed on the same area. In another embodiment, the fan-out lines 40 may be formed on the same layer. The plurality of fan-out lines 40 may be covered by the second insulating layer 103, the third insulating layer 104, the fourth insulating layer 105, and a fifth insulating layer 106.
The plurality of signal pads 70 and the protrusions 90 located between the signal pads 70 may be formed on the mounting area 140 of the non-display area NA. The signal pads 70 may be formed on the first insulating layer 102. The signal pads 70 may be formed of the same material as that of one electrode of the thin-film transistor TFT. Although the signal pads 70 are formed of the same material as that of the gate electrode 152 in
The protrusions 90 may be formed between the signal pads 70. The protrusions 90 may be formed of the same material as that of the fourth insulating layer 105 and/or the fifth insulating layer 106.
Referring to
The substrate 100 may be formed of various materials, e.g., glass, metal, or plastic. According to an embodiment, the substrate 100 may be a flexible substrate formed of a flexible material. The flexible substrate formed of the flexible material refers to a substrate that may be easily curved, bent, folded, or rolled. The substrate formed of the flexible material may be formed of ultra-thin glass, metal, or plastic.
The buffer layer 101 may prevent penetration of impurity elements through the substrate 100 and may planarize a surface, and may have a single or multi-layer structure formed of an inorganic material, e.g., silicon nitride (SiNx) and/or silicon oxide (SiOx). The buffer layer 101 may be omitted.
After a semiconductor layer is formed on the buffer layer 101, the active layer 151 of the thin-film transistor TFT may be formed by patterning the semiconductor layer. The semiconductor layer may include any of various materials. For example, the semiconductor layer may include an inorganic semiconductor material, e.g., amorphous silicon or crystalline silicon. Alternatively, the semiconductor layer may include an oxide semiconductor or an organic semiconductor material.
The first insulating layer 102 that covers the active layer 151 may be formed on the substrate 100. The first insulating layer 102 may be an inorganic insulating film. The first insulating layer 102 may be formed to have a single or multi-layer structure including at least one insulating film of, e.g., silicon oxide (SIO2), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), zirconium oxide (ZrO2), BST, and PZT.
The gate electrode 152, the first fan-out lines 40a, and the signal pads 70 may be formed on the first insulating layer 102. The gate electrode 152 may be formed of any of various conductive materials. For example, the gate electrode 152 may have a single or multi-layer structure formed of at least one from among Al, Pt, palladium (Pd), Ag, Mg, Au, Ni, Nd, Ir, Cr, Li, calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). The gate electrode 152 may overlap at least a part of the active layer 151.
The first fan-out lines 40a and the signal pads 70 may be formed of the same material as that of the gate electrode 152 of the thin-film transistor TFT.
In an embodiment, the active layer 151 may be doped with B or P ion impurities by using the gate electrode 152 as a mask. Accordingly, the active layer 151 may include a source region and a drain region doped with ion impurities, and a channel region located between the source region and the drain region.
The second insulating layer 103 that covers the gate electrode 152, the first fan-out lines 40a, and the signal pads 70 may be formed on the substrate 100. The second insulating layer 103 may be an inorganic insulating film. The second insulating layer 103 may have a single or multi-layer structure including at least one insulating film among SiO2, SiNx, SiON, Al2O3, TiO2, Ta2O5, HfO2, ZrO2, BST, and PZT. In another embodiment, the second insulating layer 103 may be an organic insulating film.
The second fan-out lines 40b may be formed on the second insulating layer 103. The second fan-out lines 40b may be formed of the same material as that of the gate electrode 152 of the thin-film transistor TFT.
The third insulating layer 104 that covers the second insulating layer 103 and the second fan-out lines 40b may be formed on the substrate 100. The third insulating layer 104 may have a single or multi-layer structure formed of an inorganic material. For example, the third insulating layer 104 may include SiO2, SiNx, SiON, Al2O3, TiO2, Ta2O5, HfO2, and/or ZrO2. In another embodiment, the third insulating layer 104 may include an organic material.
Contact holes through which parts of the source region and the drain region of the active layer 151 are exposed may be formed in the third insulating layer 104 by patterning the third insulating layer 104 along with the first insulating layer 102 and the second insulating layer 103. In this case, the first insulating layer 102, the second insulating layer 103, and the third insulating layer 104 on the mounting area 140 may be patterned and removed.
The source electrode 153 and the drain electrode 154 may be formed on the third insulating layer 104. The source electrode 153 and the drain electrode 154 may be formed of the same material as that of the gate electrode 152. The source electrode 153 and the drain electrode 154 may respectively contact the source region and the drain region of the active layer 151.
Referring to
The via hole VIA through which a part of the source electrode 153 or the drain electrode 154 of the thin-film transistor TFT is exposed may be formed in the fourth insulating layer 105 by patterning the fourth insulating layer 105. For example, the protrusions 90 of the mounting area 140 may be formed by patterning the fourth insulating layer 105. In another example, the protrusions 90 may be formed by patterning the fifth insulating layer 106. In yet another example, the protrusions 90 may be formed to have a two-layer structure by patterning the fourth insulating layer 105 and the fifth insulating layer 106.
For example, in an embodiment, after the fourth insulating layer 105 is stacked on the substrate 100, the protrusions 90 of the non-display area NA and the via hole VIA of the display area DA may be formed by performing photolithography. In another embodiment, after the fifth insulating layer 106 is stacked on the substrate 100, the protrusions 90 of the non-display area NA and an opening through which the first electrode 161 of the display area DA is exposed may be formed by performing photolithography. In another embodiment, after the fourth insulating layer 105 is stacked on the substrate 100, a lower layer of the protrusions 90 of the non-display area NA and the via hole VIA of the display area DA may be formed by performing photolithography, and after the fifth insulating layer 106 is stacked on the substrate 100, an upper layer of the protrusions 90 of the non-display area NA and an opening through which the first electrode 161 of the display area DA is exposed may be formed by performing photolithography.
According to an embodiment, an additional process for forming the protrusions 90 is not required as the protrusions 90 are formed by changing a mask design for patterning an insulating layer.
Referring to
The first electrode 161 of the light-emitting device ED may be formed on the fourth insulating layer 105, and the first electrode 161 may be electrically connected to the source electrode 153 or the drain electrode 154 of the thin-film transistor TFT exposed through the via hole VIA formed in the fourth insulating layer 105. The fifth insulating layer 106 having an opening through which a part of the first electrode 161 is exposed may be formed on the first electrode 161 to cover an edge of the first electrode 161. The fifth insulating layer 106 may have a single or multi-layer structure formed of an organic material, like the fourth insulating layer 105.
The intermediate layer 162 including an emission layer may be formed on the first electrode 161 exposed by the fifth insulating layer 106. The emission layer may include a low molecular weight organic material or a high molecular weight organic material. The light-emitting device ED may emit red, green, and blue light according to a type of the emission layer. However, the present disclosure is not limited thereto, and a plurality of organic emission layers may be included in one light-emitting device ED. For example, a plurality of organic emission layers that emit red, green, and blue light may be vertically stacked or combined to emit white light. In this case, a color conversion layer or a color filter for converting white light into a predetermined color may be further provided. The red, green, and blue colors are examples, and a combination of colors for emitting white light is not limited thereto.
The intermediate layer 162 may include at least one functional layer from among a hole injection layer, a hole transport layer, an electron transport layer, and an electron injection layer between the first electrode 161 and the emission layer and/or between the emission layer and the second electrode 163. According to an embodiment, the intermediate layer 162 may further include various functional layers other than the above layers.
Although the intermediate layer 162 is patterned to correspond only to the first electrode 161 in
By way of summation and review, one or more embodiments may provide a display apparatus for preventing vertical line defects on a screen by preventing a short-circuit between spider wirings. That is, according to embodiments, protrusions are positioned between adjacent signal pads to increase a flow path of conductive particles between the adjacent signal pads, thereby minimizing a risk for a short-circuit between the adjacent signal pads.
Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.
Number | Date | Country | Kind |
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10-2018-0045740 | Apr 2018 | KR | national |