Patent Application
20190080640
The present disclosure relates to a display apparatus having multiple pixels and a processing method, and more particularly to a method of transmitting display data from a signal processing unit in the display apparatus to a display panel.
In recent years, as the technology for computers, cameras, image processing and so forth have made progress, a high sense of reality is required for a display apparatus. For a display apparatus achieving a high sense of reality, a stereoscopic display apparatus providing an observer's right and left eyes with parallax images or a display apparatus on which a superfine image of 4K or 8K is displayed has been developed.
While the stereoscopic display apparatus includes an eyeglass type employing special eyeglasses and a naked-eye type requiring no eyeglasses as a technique for sending different images, respectively, to the right and left eyes of an observer, the development of the naked-eye type has been expected in terms of the burden of wearing eyeglasses.
Generally, in the stereoscopic display apparatus of the naked-eye type, a unit pixel for displaying a viewpoint image for the left eye and the right eye on a display panel is provided, to sort corresponding images to the right and left eyes of an observer by an optical member such as lenticular lens or parallax barrier. This requires unit pixels constituting viewpoint images by the number corresponding to the number of viewpoints, and an even larger number of pixels (the number of pixels in a regular display×the number of viewpoints) is required for stereoscopic display with an image quality having the smoothness and resolution of an image equal to that in a regular (two-dimensional) display, in order to achieve an increased sense of reality.
However, the increase in the number of pixels in a display panel causes the increase in the amount of display data to be sent from the signal processing unit in the display apparatus to the display panel, which further increases the transfer frequency of display data and the frequency of clock signals. As the frequency is higher, data signals and clock signals have larger distortion, causing a problem of degrading in the display quality and increasing in the power consumption by a driver IC due to the ground (GND) being unstable. Moreover, if display data signals in a data bus are changed at the same timing, the power line is significantly affected, which will cause noise in a driver circuit, deteriorating the display quality and increasing the power consumption. This phenomenon is generally called simultaneous switching noise.
The above-described influence of signal distortion, power-supply variation and noise on the display quality due to the increase in the drive frequency (display data transfer frequency and clock frequency) associated with the recent increase in the resolution (increase in the number of pixels) has been a cause to decelerate the development of the naked-eye type stereoscopic display apparatus. For example, a problem arises in that the stereoscopic optical characteristic (3D crosstalk) cannot be correctly evaluated. In general, a display panel of a naked-eye display apparatus supplies data to unit pixels respectively constituting different viewpoint images by the adjacent data lines. In order to evaluate the stereoscopic optical characteristic (3D crosstalk), a display pattern is used which maximizes the difference in gradation levels, i.e. gradation difference, of different viewpoint images (for example, black for the right-eye image and white for the left-eye image). This display pattern causes a simultaneous switching noise because each bit in the data bus are simultaneously changed. The noise further affects the result of measurement of the optical characteristics of an optical element which separates viewpoint images when the luminance is lowered in the display panel. This causes the stereoscopic optical characteristics (3D crosstalk), which are basically decided by the pixel layout and the characteristics of optical elements, to include the problem of a drive circuit, which hinders a correct evaluation.
Moreover, the above-described problems of signal distortion, power-supply variation and noise due to the higher drive frequency is caused also in a two-dimensional (2D) display apparatus for displaying superfine images of 4K or 8K as the number of pixels is increased, possibly deteriorating the display quality.
As a technique for suppressing the transfer frequency of the display data described above, a technique of dividing data signals to be sent to the display panel, to multiple buses. Furthermore, the technique of suppressing the peak of the noise components by shifting the phase of data for each bus, which is divided data signal, is known for suppressing simultaneous switching noise.
For example, Japanese Patent Application Laid-Open Publication No. H6-289822 discloses a method of dividing display data into two pieces and transferring one of the data pieces with a polarity opposite to that of the other data piece. Moreover, Japanese Patent Application Laid-Open Publication No. H11-249622 discloses a technique in which an input data signal is divided into multiple output signals and a phase difference is provided between the divided output signals so as to reduce the number of simultaneous changes of the output signals. Furthermore, Japanese Patent No. 3993297 discloses a method of outputting data signals with multiple stages of phases different for each data group (the RGB data group is divided into red(R), green(G) and blue(B), for example), and changing the phase difference randomly in terms of time.
Japanese Patent Application Laid-Open Publication No. H6-289822, however, poses problems in that the number of divided signal lines is limited to an even number, that one of the display data needs to have an opposite polarity and that the relationship between the wiring path in the panel and the driver IC arrangement is limited.
Furthermore, Japanese Patent Application Laid-Open Publication No. H11-249622 has a problem in that the drive frequency for the display apparatus is limited because the phase difference between divided data buses of a data output clock cycle 1CLKO is determined based on an input clock cycle 1CLKI.
In the case where the cycle of a clock output signal is shorter than the cycle of a clock input signal, multiple display data output signals with limited phase differences according to the cycles of the clock input signals are difficult to be latched by one clock output signal alone. For example, in a display apparatus which aims to have increased resolution by time-division display for each color in one pixel, or a display apparatus to which double speed driving is applied in order to enhance the performance of moving images, the cycle of a clock output signal is shortened compared to the cycle of a clock input signal. In such a display apparatus, data output signals are inconstant for the display data signal that cannot be latched, thereby causing a large disturbance in the display.
In Japanese Patent No. 3993297, the phase difference is randomly changed in terms of time, so that the timing for switching data can be dispersed, reducing the simultaneous switching. If, however, the case where the applied phase difference is 0 continues for a display pattern with frequent timing of data switching, such a problem arises that the effect of suppressing a peak of a noise component is insufficient.
All of the techniques disclosed in the prior art documents described above serve to suppress simultaneous switching noise by shifting the phase of display data irrespective of an input display pattern (data of an input image). However, shifting the phase between data shortens the setup time and hold time of data, increasing a probability of the occurrence of a data reading error as the transfer frequency becomes higher. That is, another problem of a smaller operation margin of data transfer occurs.
A display apparatus according to the present disclosure includes: a display panel in which unit pixels each constituted by a subpixel for displaying a first pattern and a subpixel for displaying a second pattern are alternately arranged in a column or a row direction; a determination part detecting a gradation difference between a first image signal input to the first subpixel and a second image signal input to the second subpixel and determining whether or not the gradation difference is equal to or larger than a preset threshold; a data output part outputting data to the display panel; and a timing control part varying phases so as to avoid synchronization of rise and fall of the first image signal and the second image signal and outputting the signals to the data output part if it is determined that the gradation difference is equal to or larger than the threshold.
In the display apparatus according to the present disclosure, the determination part determines, after it is determined that the gradation difference is equal to or larger than the preset threshold, whether or not a region having the gradation difference is equal to or larger than a predetermined number of subpixels preset in accordance with the gradation difference.
A method of processing an image signal input to a display panel in which unit pixels each constituted by a first subpixel displaying a first pattern and a second subpixel displaying a second pattern are alternately arranged in a row or column direction, according to the present disclosure, includes: obtaining a first image signal input to the first subpixel and a second image signal input to the second subpixel; detecting a gradation difference between the first image signal and the second image signal for each unit pixel; determining whether or not the gradation difference is equal to or larger than a threshold; outputting two or more clock signals with a same cycle, a same phase and a same pulse width generated for coupling the first image signal with the second image signal in synchronization with one another, if determined that the gradation difference is smaller than the threshold; and controlling the cycle, phase or pulse width such that the two or more clock signals are not synchronized with one another and outputting the two or more clock signals, if determined that the gradation difference is equal to or larger than the threshold.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of this disclosure.
The above and further objects and features will more fully be apparent from the following detailed description with accompanying drawing.
Embodiments of the present disclosure will be described below in detail with reference to the drawings. In the specification and drawings, components having substantially the same functional configurations are denoted by the same reference codes and the description thereof will not be repeated. Moreover, in the description below, the arrangement of pixels aligned in the “horizontal direction” corresponds to “row” whereas the arrangement of pixels aligned in the “vertical direction” corresponds to “column” in a display panel.
The signal processing unit 1 includes a determination part 12 to which an image signal DA1 of a first pattern 3 as well as an image signal DA2 of a second pattern 4 are input and outputting a determination result Result. The signal processing unit 1 further includes a timing control part 13 outputting two data coupling clock signals CLKO and CLKE that are controlled based on the determination result Result. Furthermore, the signal processing unit 1 includes a data output part 14 outputting a coupled image signal DB obtained by coupling DA1 with DA2 using CLKE and CLKO to the display panel 2.
The first pattern 3 represents parallax image data for the right eye in which eight pixels from 1R to 8R are arranged in four rows and two columns, whereas the second pattern 4 represents parallax image data for the left eye in which eight pixels from 1L to 8L are arranged in four rows and two columns. The image signals DA1 and DA2 correspond to signals indicating gradation levels of the respective pixels of 1R to 8R and 1L to 8L. The display panel 2 is constituted by the matrix of four rows and four columns in which the first subpixels 30 and the second subpixels 40 are alternately arranged in the row direction.
Each of the first subpixels 30 and the second subpixels 40 is a pixel with variable luminance. The luminance of the first subpixel 30 is decided by the corresponding first pattern 3 whereas the luminance of the second subpixel 40 is decided by the corresponding second pattern 4.
For example, the luminance of the first subpixel 30 located at the position of 1R in the display panel 2 is decided by 1R in the first pattern 3, whereas the luminance of the second subpixel 40 located at the position of 1L in the display panel 2 is decided by 1L in the second pattern 4. Accordingly, 1R to 8R in the first pattern 3 respectively correspond to 1R to 8R of the first subpixels 30 in the display panel 2, whereas 1L to 8L in the second pattern 4 respectively correspond to 1L to 8L of the second subpixels 40 in the display panel 2.
Furthermore, a lenticular lens 100 is arranged on the display surface side of the display panel 2. In the lenticular lens 100, cylindrical lenses 101 are aligned. The cylindrical lens 101 has a lens effect in the row direction in association with a unit pixel constituted by subpixels adjacent with each other in the row direction, in order of the first subpixels 30 and the second subpixels 40, for example, the combinations of 1R and 1L, 2R and 2L and so forth. The cylindrical lens 101 sorts out the light emitted from a pixel group 31 or 32 for the right eye constituted by the first subpixels 30 among the light emitted from a unit pixel, and assigns the light to the right eye of an observer. Moreover, the cylindrical lens 101 sorts out the light emitted from a pixel group 41 or 42 for the left eye constituted by the second subpixels 40, and assigns the light to the position of the left eye of the observer. Parallax images are used for the first pattern 3 and the second pattern 4, so that the observer is provided with a stereoscopic image.
The operation of the signal processing unit 1 will now be described with reference to
ΔDA is a difference between DA1 and DA2. Thus, ΔDA is 3 during the period from 1R-1L to 4R-4L, whereas it is 0 during the period from 5R-5L to 8R-8L. The determination result Result output by the determination part 12 is obtained by setting the threshold as 3, so that Result is 1 during the period in which ΔDA is 3 and is 0 during the period in which ΔDA is 0.
The data output part 14 latches either one of DA1 and DA2 to DB for each bit, using CLKE and CLKO, alternately in order of DA1 and DA2. The operation of the data output part 14 will be described in detail with reference to
First, DA1 in the period of 1R is latched to DB. Here, DA1[0] is latched by CLKE to make DB[0] at the High level, and DA1[1] is latched by CLKO to make DB[1] at the High level.
Next, DA2 in the period of 1L is latched to DB after one cycle of CLKE or CLKO. Similarly to the DA1 described above, DA2[0] is latched by CLKE to make DB[0] at the Low level, whereas DA2[1] is latched by CLKO to make DB[1] at the Low level.
Likewise, after one cycle of CLKE or CLKO, in 2R, 2L, 3R, 3L, 4R, 4L, 5R, 5L, 6R, 6L, 7R, 7L, 8R and 8L, in sequence, DA1[0] and DA2[0] are latched to DB[0] by CLKE, whereas DA1[1] and DA2[1] are latched to DB[1] by CLKO. In latching, a phase difference tp is generated between DB[0] and DB[1] if the phase difference tp is present between CLKE and CLKO, whereas no phase difference is generated between DB[0] and DB[1] if no phase difference is present between CLKE and CLKO.
As the signal processing unit 1 operates as described above, CLKE output by the timing control part 13 is used to latch DB[0], whereas CLKO output by the timing control part 13 is used to latch DB[1], for each bit. Accordingly, if it is determined that the gradation difference ΔDA between DA1 and DA2 is equal to or larger than the threshold, there is the phase difference tp between CLKE and CLKO, so that the phase difference tp is present between DB[0] and DB[1] to be output to the display panel 2.
It is noted that digital signals consisting of multiple bits such as DB are, in general, simultaneously latched by a single clock signal. Thus, the phase difference tp preferably remains within a range which allows DB[0] and DB[1] to be simultaneously latched by a single clock signal such as a dot clock DCLK.
Now, the effect of the phase difference tp between the adjacent DB[0] and DB[1] will be described with reference to
In
As such, a phase difference tp1 is present at the constant cycle T between DB[0] latched by CLKE and DB[1] latched by CLKO. Moreover, DB[0] and DB[1] are switched logically from High to Low or Low to High during the cycle T. Accordingly, the pulse width in the period during which DB[0] and DB[1] are High corresponds to either tw1 or tw2, and a phase difference tp2 is generated at the timings of rise and fall of DB[0] and DB[1].
As such, in addition to the phase difference tp1 between DB[0] and DB[1], the pulse width in the period during which each of DB[0] and DB[1] is High is varied to generate the phase difference tp2, so that the spike-like noise generated at GND is dispersed by the two phase differences tp1 and tp2 on the time axis. Therefore, compared to the example illustrated in
Thus, the phase difference tp1 is present at the cycle T between DB[0] latched by CLKE and DB[1] latched by CLKO. Furthermore, in the period of cycles T1 and T2, DB[0] and DB[1] are switched logically from High to Low or Low to High, so that the phase difference tp2 is generated at the timing of rise and fall of each of DB[0] and DB[1]. Moreover, during the period of cycle T, the cycle of DB[0] and DB[1] is varied from T1 to T2 or T2 to T1, which generates a phase difference tp3 at the timing of rise and fall of each of DB[0] and DB[1].
As such, in addition to the phase difference tp1 between DB[0] and DB[1], in each of DB[0] and DB[1], the cycle is varied to generate the phase differences tp2 and tp3, so that the spike-like noise generated on GND is dispersed by the three phase differences tp1, tp2 and tp3. Thus, compared to the example illustrated in
While an example has been described above where a display apparatus constituted by four rows and four columns in Embodiment 1, the number of subpixels constituting the display apparatus of the present disclosure is not limited thereto.
While digital signals of four gradation levels represented by 0 to 3 have been used in the description, the display apparatus according to the present disclosure is not intended to limit the number of gradation levels. Any digital signal of a gradation level constituted by multiple bits may be controlled for the presence/absence of a phase difference between an even bit and an odd bit.
As illustrated in
Moreover, in a digital signal constituted by a number of bits, such as a digital signal constituted by 24 bits including 8 bits for each of RGB, for example, in the case where a large number of spike-like noises generated on GND are overlapped with one another, the number of the data coupling clock signals to be output to the data output part 14 by the timing control part 13 may be set as three, and a phase difference may be provided between digital signals adjacent to each other at the cycle of 3 bits. Moreover, an even larger number of data coupling clock signals may also be used.
The timing control part 13 controls the phase differences among the data coupling clock signals CLKA, CLKB, CLKC and CLKD in accordance with the determination result of the determination part 12, and outputs the signals.
The data output part 14 controls adjacent digital signals such as DB[0] and DB[1] so as to have different phase differences using the data coupling clock signals CLKA, CLKB, CLKC and CLKD controlled for their respective phase differences, so that the spike-like noise generated on GND may further be dispersed in the time axis direction, compared to the case of the control using the two data coupling clock signals CLKO and CLKE as illustrated in
While the control is carried out using the phase difference tp between the adjacent coupled image signals DB in the example illustrated in
Moreover, the number of data coupling clock signals is not limited to four as described in the example above, but an even larger number of data coupling clock signals may also be used.
Now, examples of the present disclosure will be described below in detail with reference to the drawings.
The display panel 2a includes first subpixels 30 for displaying the first pattern 3 and second subpixels 40 for displaying the second pattern 4, constituting a unit pixel, that are alternately aligned in the row direction on a transparent substrate (not illustrated). Each of the first subpixel 30 and the second subpixel 40 is constituted by the TFT(Thin Film Transistor) 5, pixel electrode 6 and common electrode 7, and is connected to the data line 11, gate line 21 and common electrode power supply 8. The data line 11 is connected to the data driver 10 having the outputs of D1 to D4, and the gate line 21 is connected to the gate driver 20 having the outputs of G1 to G4. Though not illustrated, another surface of the display panel 2a different from the display surface is provided with a planar light source emitting light toward the direction of the display surface of the display panel 2a. Furthermore, as in Embodiment 1, a lenticular lens 100 constituted by cylindrical lenses 101 is provided at the display surface side of the display panel 2a.
The gate driver 20 outputs scanning signals, sequentially from the outputs G1 to G4, so as to select the gate line 21 to which each of the outputs is connected. Moreover, the data driver 10 supplies a signal corresponding to a subpixel connected to a gate line 21 being selected, from D1 to D4 to the data line 11 connected to each output. Thus, a signal voltage is supplied to the pixel electrode 6 through the TFT 5 connected to the selected gate line 21. The difference between the signal voltage supplied to the pixel electrode 6 and the Vcom voltage of the common electrode power supply 8 applied to the common electrode 7 serves to drive an electric optical element such as a liquid crystal.
The operation of the display panel 2a will now be described with reference to
After latching the input DB[0] and DB[1] at the timing of DCLK, the data driver 10 performs sampling in accordance with DB in order from D1 to D4, to sequentially output the signals to the data line 11. For example, in the first frame, a potential 203 of the gradation level 3 sampled during the period of 1R is output to D1, whereas a potential 200 of the gradation level 0 sampled during the period of 1L is output to D2. The potential 200 of the gradation level 0 sampled during the period of 2R is output to D3, whereas the potential 203 of the gradation level 3 sampled during the period of 2L is output to D4. Subsequently, for the periods from 3R to 8L, potentials sampled in an orderly manner are sequentially output to D1 to D4 in similar manners.
The gate driver 20 sequentially outputs the High level to the gate line 21 in order from G1 to G4. In the period of High level, the sampled potential of the data line 11 is sequentially applied to the pixel electrode 6 through the TFT 5 connected to the gate line 21, so that predetermined image signals are written into subpixels.
In
The other AC driving includes a mode in which the polarity is inverted in the column direction or a mode in which the polarity is inverted for each subpixel. By the use of the technique above described, in either mode of inversion, the timing of rise and fall between data outputs is shifted one from another, to disperse the influence of the distortion on GND in the time axis direction. This produces an effect of suppressing a drive load as well as a noise affecting the display quality.
The configuration and operation of Example 1 are the same as those in Embodiment 1 except for the differences described above, and thus the description thereof will not be repeated here.
While the display panel 2a used in the display apparatus according to Example 1 of the present disclosure includes subpixels arranged in a matrix of four rows and four columns for merely simplifying the illustration, this will not limit in any way the number of pixels. Furthermore, each of DA1, DA2 and DB is described as a digital signal composed of two bits for the sake of convenience, which however is not intended to limit the number of bits of a digital signal.
Here, the regularity for the gate line 21, the first subpixel 30 and the second subpixel 40 is described. At the output of the gate driver 20, the TFTs 5 of the second subpixels 40 that are adjacent to each other in the column direction, such as 3L and 5L, are connected to the gate line 21 selected by G1, G3 and G5. To the gate line 21 selected by G2 and G4, the TFTs 5 of the first subpixels 30 that are adjacent to each other in the column direction, such as 1R and 3R, are connected.
In the signal processing unit 1 according to Example 2, DA1 which is an image signal of the first pattern 3 and DA2 which is an image signal of the second pattern 4 are input to the determination part 12b as G1 to G5 illustrated in
Based on the gradation values corresponding to the first subpixels 30 adjacent to each other in the column direction or the second subpixels 40 adjacent to each other in the column direction, the determination part 12b determines whether or not the gradation difference ΔDA is equal to or larger than a threshold.
Moreover, the timing control part 13b and the data output part 14b operate differently from those in Embodiment 1 so as to correspond to the relationship illustrated in
DA1 and DA2 are input to the determination part 12b as in G1 to G5 illustrated in
Next, in the row of G2 illustrated in
Subsequently, in a similar manner, the gradation values are input to the determination part 12b so as to correspond to the order indicated by D1 to D5, in the G3 to G5 rows in
At the timing control part 13b, as in Embodiment 1, in the period during which the determination result Result is 1, CLKE and CLKO have a phase difference tp generated by the phase shift processing. In the period where the determination result Result is 0, no phase shift processing is performed so that there is no phase difference between CLKE and CLKO. In Example 2, CLKE and CLKO have the same cycles as those of DA1 and DA2.
At the data output part 14b, DA1 and DA2 are latched to DB. To latch the signals to DB, CLKE and CLKO are used to alternately latch DA1 and DA2 so as to correspond to the respective row units of G1 to G5 illustrated in
As described above, also in the display panel 2b with a connection between each TFT 5 and the data line 11 or the gate line 21 different from that in Example 1, the gradation difference ΔDA may be detected based on the first subpixels 30 adjacent to each other in the column direction or the second subpixels 40 adjacent to each other in the column direction. Accordingly, as in Embodiment 1, the phase difference tp for DB may be controlled, producing such an effect that the distortion affecting GND is dispersed in the time axis direction.
The connection between the data line 11 or gate line 21 and TFT 5 schematically illustrated in
The configuration and operation of Example 2 are the same as those in Embodiment 1 except for the differences described above, and thus the description thereof will not be repeated here.
As in Embodiment 1, such an effect is produced that the distortion affecting GND is dispersed in the time axis direction. Furthermore, as the pixel layout illustrated in
The connection between the data line 11 or the gate line 21 and TFT 5 schematically illustrated in
The configuration and operation of Example 3 are the same as those in Embodiment 1 except for the differences described above, and thus the description thereof will not be repeated here.
As in Embodiment 1, such an effect is produced that the distortion affecting GND is dispersed in the time axis direction. Furthermore, as the pixel layout illustrated in
In Example 3, the gate driver 20 is horizontally arranged whereas the data driver 10 is vertically arranged, as illustrated in
DB is a coupled image signal of a digital signal composed of 24 bits, which is divided into three groups (three 8-bit digital signals of DB[0]-[7], DB[8]1151 and DB[16]-DB[23]), and CLK indicates a data coupling clock signal for latching DB.
For the three groups of DB, in the display panel 2c illustrated in
In
The rate of variation in the negative power supply caused by distortion in GND is large, i.e. 2%, in the case of (1) in
Moreover, the variation rate of the luminance profile is reduced by 20% in the case of (1) in
As to the operation in Embodiment 1 described above, the following description may be applied.
In the case where certain right eye image data and left eye image data are used, if the difference ΔDA between DA1 and DA 2 that are image signals for the respective data is large enough, the determination result Result of 1 is obtained as described above, and the signals are output as the rise or fall of the bit signals of the coupled image signal DB are not synchronized.
For the right eye image data and left eye image data described above, the difference in the maximum gradation values between the respective image signals DA1 and DA2 is modulated in advance to a threshold plot 510 illustrated in
Also in the case where the same image data is used, synchronization or non-synchronization of the rise and fall of the bit signals in the coupled image signal DB may be controlled by only controlling in advance the difference between the maximum gradation values within an image.
As described above, according to Embodiment 1 of the present disclosure, by shifting the timing of fall and rise between data outputs to disperse the influence of distortion on GND in the time axis direction, the effect of suppressing a drive load as well as a noise affecting the display quality may be obtained even if the drive frequency is increased in the display apparatus.
In Embodiment 1, the determination part 12 determines, for each pixel, whether the difference between the maximum gradation value of the first pattern 3 (hereinafter referred to as right-eye image data) and that of the second pattern 4 (hereinafter referred to as left-eye image data) is equal to or larger than the threshold. In Embodiment 2, in addition to the determination described above, the ratio of the region having a large difference between gradation values of both of the data is calculated for determination.
For the ease of description of the characteristics according to Embodiment 2, an example of the threshold in Embodiment 1 is illustrated in
By contrast, determination is made based on two parameters of the gradation difference and the region with the gradation difference in Embodiment 2, allowing for detailed determination on the influence of the drive load and thereby suppressing the appearance rate of the phase shift processing to some degree. This can reduce the risk of the occurrence of a data error at the high drive frequency.
Though
As to the operation in Embodiment 2 described above, the following description may be applied.
In the case where certain right-eye image data and left-eye image data are used, if the difference ΔDA between DA1 and DA 2 that are image signals for the respective data as well as its region A(ΔDA) are large enough, the determination result Result of 1 is obtained as described above, and the signals are output as the rise or fall of the bit signals of the coupled image signal DB are not synchronized with each other.
For the right-eye image data and left-eye image data described above, the difference in the maximum gradation values between the respective image signals DA1 and DA2 is modulated in advance to a threshold plot 510 or smaller as illustrated in
As such, even if the same image data is used, by controlling only the maximum gradation difference within an image in advance, control for synchronizing or not synchronizing the rise and fall of bit signals in the coupled image signal DB may be carried out.
In the display apparatus according to Embodiments 1 and 2, parallax images are used for the first pattern 3 (right-eye image data) and the second pattern 4 (left-eye image data), so as to provide an observer with a stereoscopic image. The observer, however, does not always desire to view a stereoscopic image.
Embodiment 3 includes such a function that an observer may select whether or not a stereoscopic image is to be viewed.
The stereovision selecting unit 15 includes a function of outputting a stereovision selection signal Stereo to the stereovision switching part 16 in accordance with the selection of whether or not an observer is to view a stereoscopic image. The stereovision selection signal is set as “1” (Stereo=1) if the observer selects a stereoscopic view, whereas the stereovision selection signal is set as “0” (Stereo=0) if the observer selects a non-stereoscopic view, and is output to the stereovision switching part 16.
For example, the stereovision selecting unit 15 can be implemented by including an ON/OFF switch to be operated by the observer, who turns the switch ON in the case of stereoscopic viewing and OFF in the case of non-stereoscopic viewing, and configuring a circuit in which the stereovision selection signal is “1” (Stereo=1) during the state of the switch ON and the stereoscopic selection signal is “0” (Stereo=0) during the state of the switch OFF. A push button with lighting may be used for this ON/OFF switch, outputting Stereo=1 as ON when the light is turned on whereas Stereo=0 as OFF when the light is turned off, and ON/OFF may alternately be inverted every time the observer pushes the button.
Furthermore, for example, the stereovision selecting unit 15 may also be implemented by a circuit configured to detect a connection terminal for inputting a signal from the outside and a signal input through the connection terminal, and converting the signal into the stereovision selection signal Stereo in accordance with the detected signal.
The stereovision switching part 16 has a function of outputting the input two image signals DA1 and DA2 simply as two image signals without conversion (DA1″=DA1 and DA2″=DA2). The stereovision switching part 16 also has a function of distributing either one of DA1 and DA2, and outputting two image signals to be output as the same image signal (DA1″=DA1 and DA2″=DA1 or DA1″=DA2 and DA2″=DA2). Furthermore, the stereovision switching part 16 has a function of switching these outputs in accordance with the input stereovision selection signal Stereo. DA1″ and DA2″ output from the stereovision switching part 16 are input to the determination part 12 and the data output part 14.
Subsequently, as in Embodiment 1, the timing control part 13 in accordance with the determination result of the determination part 12 controls the presence/absence of a phase difference between DB[0] and DB[1] output from the data output part 14.
As illustrated in
Furthermore, if an observer feels eye fatigue in stereoscopic viewing or is difficult to view a stereoscopic image (e.g., if the observer's eyesight has a large difference between the right eye and the left eye or if the observer is a child who has a distance between the pupils smaller than that of an adult), the observer may interrupt the stereoscopic viewing with the use of the stereovision selecting unit 15.
In order to provide an observer with a stereoscopic image, a video image signal source (CPU, GPU, Blu-ray (registered trademark) player or TV tuner, for example) which can transmit a parallax image to a display apparatus often has a function of adjusting the amount of parallax in general. If the parallax is eliminated by the function of adjusting the amount of parallax, the observer cannot view a stereoscopic image. Thus, the parallax adjusting function may be used as the stereovision switching part 16 illustrated in
If the observer selects stereoscopic viewing (Stereo=1), the video signal source 1000 outputs the first pattern 3 and the second pattern 4 having parallax between them. If the observer selects non-stereoscopic viewing (Stereo=0), the video signal source 1000 outputs the first pattern 3 and the second pattern 4 with no parallax.
For the first pattern 3 and the second pattern 4 output by the video signal source 1000, in the case of 3D rendering in which a pattern with a depth feel is drawn on a flat surface based on a three-dimensional object or light source data, if the observer selects stereoscopic viewing (Stereo=1), the parallax is used for arithmetic operation. Accordingly, the video signal source 1000 outputs the first pattern 3 and the second pattern 4 with parallax between them after drawing. If the observer selects non-stereoscopic viewing (Stereo=0), the video signal source 1000 perform arithmetic operation with the parallax set as 0 and output the first pattern 3 and the second pattern 4 with no parallax after drawing.
Moreover, for example, in the case where the CPU performs arithmetic operation to generate an image with two sets of parallax based on a two-dimensional planar pattern such as image data and depth information data such as depth data, if the observer selects stereoscopic viewing (Stereo=1), the CPU performs the operation using the depth information. Accordingly, the first pattern 3 and the second pattern 4 with parallax between them are drawn and then output. If the observer selects non-stereoscopic viewing (Stereo=0), the CPU performs the operation without the use of the depth information, and outputs the images of the first pattern 3 and the second pattern 4 after drawing, or the two-dimensional planar patterns directly as the first pattern 3 and the second pattern 4.
For example, if the observer selects stereoscopic viewing (Stereo=1), the first pattern 3 and the second pattern 4 are output as they are. If the observer selects non-stereoscopic viewing (Stereo=0), the first pattern 3 is output as the first pattern 3 and a new second pattern 4, or the second pattern 4 is output as a new first pattern 3 and the second pattern 4.
Subsequently, as in Embodiment 1, based on the first pattern 3 and the second pattern 4 input from the video signal source 1000, the image signals DA1 and DA2 are input to the determination part 12. The timing control part 13 controls, in accordance with the determination result of the determination part 12, the presence/absence of a phase difference between DB[0] and DB[1] output from the data output part 14.
Furthermore, in the video signal source 1000, if the selection of non-stereoscopic viewing is made (Stereo=0), either one of the first pattern 3 and the second pattern 4 is generated and distributed to be output as the same pattern, so that a load on the pattern generation in the CPU or GPU may be alleviated.
It is noted that the stereovision selection signal Stereo may be processed using a transmission line for video signals while being included in various other signals superposed thereon and transmitted during a blanking period of video signals. For example, “InfoFrame transmitting 3D information” (meaning that a 3D video image is being transmitted) defined by the HDMI (registered trademark) standard Ver. 1.4, or information indicating the type of 3D mode of a video image, such as Frame Packing or Side-by-Side (Half).
While Embodiment 3 of the present disclosure has been described, the configuration and operation of Embodiment 3 are the same as those in Embodiment 1 except for the differences described above, and thus the description thereof will not be repeated here.
The display panel 2 used in the display apparatus according to Embodiment 3 of the present disclosure is similar to that in Embodiment 1, which is described with subpixels arranged in the matrix of four rows and four columns, while the display panel 2a in
Furthermore, while the gradation difference between DA1″ and DA2″ is used in the determination part 12 according to Embodiment 3, the determination results, based on calculated the occupancy ratio of the region with a large gradation difference between DA1″ and DA2″ may be combined together, as described in Embodiment 2. This allows for detailed determination about the influence of the drive load and thereby suppressing the appearance rate of the phase shift processing to some degree. This can reduce the risk of the occurrence of a data error at the high drive frequency described above.
Moreover, while the timing control part 13 according to Embodiment 3 performs processing of varying the phase between CLKE and CLKO, Embodiment 3 is not limited to the variation in the phase. As described with reference to
While Embodiment 1 described that DB obtained by coupling the first pattern 3 with the second pattern 4 is output to the display panel 2, DB is constituted by two or more clock lines in Embodiment 4.
The configuration and operation of Embodiment 4 are the same as those in Embodiment 1 except for the differences described above, and thus the description thereof will not be repeated here.
In the case where such a process is applied as to have different phases between DBs, as in DB[0] and DB[1], a setup time ts or a hold time th is also different between DBs. For example, in
In Embodiment 4, as illustrated in
Though two clocks are used in Embodiment 4, more than two clocks may also be used. For example, clocks with different phases may be used for each of 8-bit buses for each of RGB obtained by dividing 24-bit bus constituted by 8 bits of each of RGB.
In Embodiment 5, the frequency of DB may be varied at the data output part 14.
The configuration and operation of Embodiment 5 are the same as those in Embodiment 1 except for the differences described above, and thus the description thereof will not be repeated here.
In
The effect of Embodiment 5 will be specifically described below with reference to
DB is constituted by three sets of DBs, including 8 bits of gradation values DB[0]-DB[7] for potentials output from D1 and D4 of the data driver 10, 8 bits of gradation values DB[8]-DB[15] for potentials output from D2 and D5, and 8 bits of gradation values DB[16]-DB[23] for potentials output from D3.
In the display apparatus, assuming that the 8-bit gradation value (FF)16 corresponds to white and (00)16 corresponds to black, DB[0]-[7] and DB[16]1231 alternately repeat High and Low whereas DB[8]-[15] alternately repeat Low and High for each CLK cycle. Accordingly, the cycle varies so as to be different for each of the three sets of DBs in addition to the phase difference.
It can be seen that the number of generating of distortions on GND during a certain period is reduced in
As described above, even in the case where the drive frequency of the display apparatus according to the present disclosure is increased and one frame period TfA2 of input image data is significantly shortened, the timing of rise and fall between data outputs may be shifted by the application of Embodiment 5. That is, by further dispersing the distortion affecting GND in the time axis direction, the effect of suppressing a drive load as well as a noise affecting the display quality may be produced. Moreover, by varying the frequency of DB, the margin for the setup time is and the hold time th as described in Embodiment 4 may more easily be secured.
In Embodiment 1, the determination part 12 determines whether or not the gradation difference ΔDA between DA1 and DA2 is equal to or larger than the threshold, and the timing control part 13 in accordance with the determination result of the determination part 12 controls the presence/absence of a phase difference between DB[0] and DB[1] output from the data output part 14. In Embodiment 6, in addition to the determination based on the gradation difference ΔDA, detection is made as to whether the change in DB is for the fall from High to Low or for the rise from Low to High, based on DA1 and DA2. The determination part 12 determines whether or not the detected change corresponds to a predetermined change. The timing control part 13 in accordance with the determination result of the determination part 12 controls the presence/absence of a phase difference between DB[0] and DB[1] output from the data output part 14. In Embodiment 6, the determination and control serve not to synchronize either one of the rise and fall between DB[0] and DB[1].
Generally, an active element such as an IC which handles digital signals performs switching operation. In Embodiments 1 to 4, ideal digital signal waveforms consisting only of two states of ON and OFF in the switching operation are described with reference to the drawings. In practice, however, two more states in the middle between ON and OFF, i.e. the state of transition from OFF to ON and the state of transition from ON to OFF, are present.
In the case of
In the case of
In each of
As in
Thus, as for DB between the signal processing unit 1 and the display panel 2, the timing control part 13 controls to provide a phase difference only for a shorter one of the rise time tr and the fall time tf, so as to ensure the margin in the setup time and the hold time.
The change detected based on DA1 and DA2 corresponds to the rise time tr or the fall time tf, and the predetermined change corresponds to a shorter one thereof. To detect if the change corresponds to the predetermined change, corresponding bits of DA1 and DA2 are compared with one another.
For example, DB[0] illustrated in
Likewise, based on Low which is set to DA1[0] during the period of 2R and High which is set to DA2[0] during the period of 2L, such a change may be detected that DB[0] rises from Low to High during the period of 2R to the period of 2L.
As described above, in the case where the change detected from the corresponding bits for DA1 and DA2 does not match with the predetermined change, no determination is made as to whether or not the gradation difference ΔDA is equal to or larger than the threshold. As such, irrespective of the gradation difference ΔDA, whether or not the gradation difference ΔDA is equal to or larger than the threshold is determined if the result of less than the threshold, i.e. Result=0, is output and the detected change is the predetermined change. Thus, the timing control part 13 controls the presence/absence of a phase difference in a predetermined shorter one of the rise time tr and the fall time tf.
The effect of Embodiment 6 will be described with reference to
As for DBs indicated in
In
Comparison for the secured setup time and the secured hold time shows that ts3 and th3 are shorter than ts1 and th1. Thus, depending on the setting for the phase difference, the setup time as well as hold time may be different. Though ts4 and th4 are secured for a longer period of time compared to ts3 and th3, phase adjustment may be required to conform to the short period of ts3 and th3 if the dot clock DCLK is a single clock with a constant cycle. It is therefore difficult to secure the margin in the setup time and the hold time.
As described above, in the case where a phase difference is provided, a shorter one of the rise time and fall time is set to half the longer one thereof or less, so that the distortion affecting GND is reduced while easily securing the margin in the setup and hold time. Moreover, shifting of a phase oscillates a signal in the time axis direction. The signal oscillation may appear on the display as noise. According to Embodiment 6, a phase shift is carried out at either one of the rise and fall, thereby facilitating phase adjustment of a clock for sampling signals which is performed to reduce noise on the display.
Furthermore, the variations in the pulse width and cycle in Embodiment 1 as described with reference to
It is noted that the amplitude of the spike-like noise generated on GND illustrated in
While Embodiment 6 of the present disclosure has been described, the configuration and operation of Embodiment 6 are the same as those in Embodiment 1 except for the differences described above, and thus the description thereof will not be repeated here.
In Embodiment 7, a high definition color display apparatus is employed in which unit pixels each constituted by different colors of subpixels are arranged in row and column directions on a display panel 2. According to Embodiment 7, a threshold for determining a phase difference or the presence/absence of variation in the pulse width or cycle is set based on whether or not the gradation values of subpixels that are adjacent to each other in the row or column direction are inverted from each other.
A unit pixel in a general color display panel is constituted by subpixels of RGB which are the three primary colors of light, which expresses a red display by turning on only the subpixel of R while turning off the subpixels of G and B. In the case of a white display, the subpixels of RGB are turned on, and RGB are mixed together to express white. As such, different multiple colors are expressed by combinations of subpixels of different colors. Moreover, the number of colors to be expressed may further be increased by controlling the luminance of subpixels. For example, in the case of including three subpixels of RGB, 23=8 colors may be expressed. Furthermore, if the brightness is controlled in gradation of 256 levels for each subpixel of RGB, about 16,770,000((23)8) colors may be expressed.
While Embodiment 1 uses, as a threshold, the gradation difference between adjacent subpixels for determination on a phase difference, Embodiment 7 uses, as a threshold, whether or not the gradation levels are inverted between adjacent subpixels.
In the display panel 2d, unit pixels 90 each constituted by subpixels R, G and B for each color are arranged in four rows and four columns, and display is realized without the intermediary of the lenticular lens 100.
Input image data includes three patterns of an R pattern 60 constituted by gradation values corresponding to the subpixels 1R to 16R in the display panel 2d, a G pattern 70 constituted by gradation values corresponding to the subpixels of 1G to 16G in the display panel 2d, and a B pattern 80 constituted by gradation values corresponding to the subpixels of 1B to 16B in the display panel 2d.
Signals input to the determination part 12d are: an image signal RA obtained by reading out gradation values corresponding to subpixels 1R to 16R in an orderly manner from the R pattern 60; and an image signal GA obtained by reading out gradation values corresponding to subpixels of 1G to 16G in an orderly manner from the G pattern 70. Furthermore, an image signal BA obtained by reading out gradation values corresponding to subpixels 1B to 16B in an orderly manner from the B pattern 80 is input to the determination part 12d.
The determination on the relationship of inverted gradation levels is made by determining whether or not an inverted gradation value obtained from the gradation value for one of adjacent subpixels is equal to the gradation value for the other one of the adjacent subpixels, based on the gradation values of the obtained three image signals RA, GA and BA as well as the RGB resistor. Here, the inverted gradation value is obtained by subtracting the actual gradation value from the maximum value to be taken by a gradation value.
An example of two-bit gradation indicates that the maximum value taken by a gradation value is (11)2, which is 3. Here, the inverted gradation value of the gradation value 0 for one of the adjacent subpixels is represented by 3(=3−0). Here, if the gradation value for the other one of the adjacent subpixels is 3, it is determined as having the relationship of inverted gradation levels since it is equal to the inverted gradation value.
In general, digitized gradation values start from 0 and the maximum value taken by a gradation value is 3 in the case of the 2-bit gradation, 7 in the case of the 3-bit gradation and 255 in the case of 8-bit gradation, which are odd numbers. Thus, the determination as described above may be applicable.
It is to be noted that the above relationship is not satisfied when the maximum value taken by the gradation value is an even number, not corresponding to the values as described above. For example, if the maximum value taken by the gradation value is 4, the inverted gradation value for the gradation value 2 is 2(=4-2), which is a case where the obtained inverted gradation value is not inverted.
Moreover, the RGB resistor is a resistor for temporarily storing a gradation value, which holds the gradation value unless overwritten, and can read the gradation values individually from RA, GA and BA and write the gradation values.
As a result of determination, if the relationship corresponds to inverted gradation levels (S62: YES), the determination part 12d sets 1 to the determination result Result and outputs Result to the timing control part 13d (S63). If otherwise (S62: NO), the determination part 12d sets 0 to the determination result Result and outputs Result to the timing control part 13d (S64). After the output, the determination part 12d stores RA, GA and BA in the RGB resistor (S65), and returns the processing to step S61. The RGB resistor in which RA, GA and BA are stored is used for determination on whether or not the subsequently obtained RA, GA and BA have the relationship of inverted gradation levels. Note that the cycle for determination conforms to the cycle of DB.
In
First, determination on gradation inversion is made between 1R and 1G. As illustrated in
Next, since 1B has the gradation value (11)2 whereas 2R has the gradation value (00)2, showing the relationship of inverted gradation levels, the determination part 12d sets 1 to the determination result Result.
Next, since 2R has the gradation value (00)2 whereas 2G and 2B each has the gradation value of (00)2, not showing the relationship of inverted gradation levels continuously, the determination part 12d sets 0 to the determination result Result.
Next, since 2B has the gradation value of (00)2 whereas 3R has the gradation value of (11)2, and 3G has the gradation value of (00)2, showing the relationship of inverted gradation levels continuously, the determination part 12d sets 1 to the determination result Result.
Subsequently, sequential determinations are made as to whether or not the corresponding gradation values have inverted gradation levels in order of between the subpixels R and G, between G and B, and between B and R. The determination results Result are then output to the timing control part 13d.
The timing control part 13d outputs CLKE and CLKO with a phase difference to the data output part 14d during the period in which Result is 1. Further, the cycle of each of CLKE and CLKO corresponds to a third of the cycle of each of RA, GA and BA.
The data output part 14d, as in Embodiment 1, using CLKE and CLKO output from the timing control part 13d, sequentially latches RA, GA and BA to DB[0]-DB[1] in the time axis direction, and outputs the latched DB to the display panel 2d.
In the example above, DB is latched using CLKE and CLKO with the phase difference controlled by the determination part 12d. Accordingly, in the case where adjacent subpixels have the relationship of inverted gradation levels, the corresponding DB[0]-[1] may be provided with phase shift processing so as not to be logically inverted at the same time, which can disperse the influence of distortion on GND in the time axis direction.
While the determination part 12d according to Embodiment 7 performs determination between subpixels, such as between 1R and 1G, determination before 1R or after 16B may additionally be performed. Since no subpixel is present before 1R or after 16B in practice, such determination cannot be used to determine the relationship of inverted gradation levels on the display. It may, however, address the occurrence of noise due to simultaneous switching on the periphery of the display by determining whether or not logical inversion is performed for all bits of digital signals.
Each of image signals RA, GA, BA and DB corresponding to RGB subpixels is described as a digital signal composed of two bits for the sake of convenience, which however is not intended to limit the number of bits of a digital signal.
While the display panel 2d used in the display apparatus according to Embodiment 7 of the present disclosure was described with the subpixels of RGB, the subpixels constituting the display apparatus of the present disclosure are not limited thereto. Furthermore, though unit pixels constituted by the subpixels of RGB are arranged in a matrix of four rows and four columns, this arrangement is for merely simplifying the illustration and will not limit in any way the number of pixels.
Moreover, the determination part 12d according to Embodiment 7 determines the presence/absence of a phase difference based on whether or not adjacent subpixels have the relationship of inverted gradation levels, which will not limit the present disclosure. For example, elements described in Embodiments 1 to 5 may also be combined with one another. For example, as in Embodiment 1, the determination part 12d may make a determination by using a gradation difference between adjacent subpixels as a threshold.
Moreover, as described in Embodiment 2, by determining whether or not the region with the inverted gradation levels is equal to or larger than a predetermined number of unit pixels, the appearance rate of the phase shift processing may be suppressed to some extent. Thus, a data error, which has an increased risk of occurrence thereof in the case of a higher drive frequency of the display apparatus may be reduced.
Moreover, while the timing control part 13d according to Embodiment 7 performs processing of varying the phase between CLKE and CLKO if the determination result Result is 1, the present disclosure is not limited to the variation in the phase. As described with reference to
In addition, the data output part 14d may be constituted by two or more clock lines. This may produce an effect similar to that in Embodiment 4 (description with reference to
As to the operation in Embodiment 7 described above, the following description may also be applied.
In the case where certain image data is used, if the gradation difference between adjacent subpixels is large enough to exceed the threshold, the determination result Result of 1 is obtained as described above, and the coupled image signal DB is output while ensuring the rise or fall of the bit signals of DB not to be synchronized.
For the image data described above, the difference in the maximum gradation values within the image signals is modulated in advance to the threshold or smaller, so that the determination result Result of 0 is obtained and the coupled image signal DB may be output while ensuring the rise and fall of the bit signals of DB to be synchronized with one another.
As such, even if the same image data is used, by controlling only the maximum gradation difference within an image in advance, control for synchronization or non-synchronization may be possible for the rise and fall of bit signals of the coupled image signal DB.
While Embodiment 7 uses, as a threshold, whether or not the gradation levels are inverted between adjacent subpixels in the determination on a phase difference, Embodiment 8 uses, as a threshold, whether or not the gradation levels are inverted between adjacent unit pixels.
Embodiment 8 has the same configuration as that illustrated in
In
Next, 2R has the gradation value (00)2 whereas 3R has the gradation value (11)2, indicating that the gradation values are inverted between 2R and 3R. However, the gradation values are not changed from (00)2 between 2G and 3G, and between 2B and 3B. Moreover, the unit pixels are not displayed with the relationship of inverted gradation levels, such as “black and red.” Accordingly, the determination part 12d sets 0 to the determination result Result. Subsequently, sequential determinations are made as to whether or not the unit pixels have the relationship of inverted gradation levels, and the determination results Result are then output to the timing control unit 13d.
In the signal processing unit 1 according to Embodiment 7, the cycle of CLKE and CLKO is one third of the cycle of RA, GA or BA, and RA, GA and BA are latched to DB using CLKE and CLKO sequentially in the time axis direction. In Embodiment 8, with the use of CLKE and CLKO having the same cycle as that of RA, GA or BA, the number of bits of DB is extended compared to Embodiment 7 and RA, GA and BA are latched in parallel.
As DB is extended to 6 bits, RA[0]-RA[1] are coupled to DB[0]-DB[1], GA[0]-GA[1] are coupled to DB[2]-DB[3], and BA[0]-BA[1] are coupled to DB[4]-DB[5], and therefore the frequency may be reduced to one third of the frequency of DB in
The configuration and operation of Embodiment 8 are the same as those in Embodiment 7 except for the differences described above, and thus the description thereof will not be repeated here.
Each of image signals RA, GA, BA and DB corresponding to RGB subpixels is described as a digital signal composed of two bits for the sake of convenience, which however will not limit the number of bits of a digital signal.
While the display panel 2d used in the display apparatus according to Embodiment 8 of the present disclosure was described with the subpixels of RGB as in Embodiment 7, the subpixels constituting the display apparatus of the present disclosure are not limited thereto. Furthermore, though unit pixels constituted by the subpixels of RGB are arranged in a matrix of four rows and four columns, this arrangement will not limit in any way the number of pixels.
Moreover, the determination part 12d according to Embodiment 8 determines the presence/absence of a phase difference based on whether or not adjacent unit pixels have the relationship of inverted gradation levels, which will not limit the present disclosure. For example, elements described in Embodiments 1 to 7 may also be combined with one another. For example, as in Embodiment 1, the determination part 12d may make a determination by using a gradation difference between adjacent subpixels as a threshold.
Moreover, as described in Embodiment 2, by determining whether or not the region with the inverted gradation levels corresponds to a predetermined or larger number of unit pixels, the appearance rate of the phase shift processing may be suppressed to some extent. Thus, a data error, which has an increased risk of occurrence thereof in the case of an increased drive frequency of the display apparatus, may be reduced.
Furthermore, while the timing control part 13d according to Embodiment 8 performs processing of varying the phase between CLKE and CLKO if the determination result Result is 1, the present disclosure is not limited to the variation in the phase. As described with reference to
As to the operation in Embodiment 8 described above, the following description may also be applied.
In the case where certain image data is used, if the gradation difference between adjacent unit pixels is large enough to exceed the threshold, the determination result Result of 1 is obtained as described above, and the coupled image signal DB is output while ensuring the rise or fall of the bit signals of DB not to be synchronized.
For the image data described above, the difference in the maximum gradation values within the image signals is modulated in advance to the threshold or less, so that the determination result Result of 0 is obtained and the coupled image signal DB may be output while ensuring the rise and fall of the bit signals of DB to be synchronized with one another.
As such, even if the same image data is used, by controlling only the difference between the maximum gradation values within an image in advance, control for synchronization or non-synchronization may be possible for the rise and fall of bit signals of the coupled image signal DB.
It is to be noted that each of Embodiments 2 to 6 may also have a practical pixel layout in which a unit pixel has a trapezoidal-shaped aperture as in Examples 2 or 3.
As described above, by the use of the method of transmitting display data from a signal processing unit to a display panel in the display apparatus according to the present disclosure, even if the drive frequency of the display apparatus is increased, the timings of fall and rise between data outputs are shifted, thereby dispersing the distortion affecting the GND in the time axis direction. This produces an effect of suppressing a drive load as well as a noise affecting the display quality.
While the present disclosure has been described above according to Embodiments 1 to 8, it is not limited to the embodiments described above. Various modifications that can be understood by a person with ordinary skills in the art may also be added to the configuration and details of the present disclosure. The present disclosure also encompasses an appropriate combination of a part or whole of the configurations in different embodiments.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2015-155409 | Aug 2015 | JP | national |
| 2016-080375 | Apr 2016 | JP | national |
This is a Divisional Application of U.S. application Ser. No. 15/226,234, filed Aug. 2, 2016, which claims priority under 35 U.S.C. § 119(a) from Patent Application No. 2015-155409 filed in Japan on Aug. 5, 2015, and Patent Application No. 2016-080375 filed in Japan on Apr. 13, 2016, the entire contents of which are hereby incorporated by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 15226234 | Aug 2016 | US |
| Child | 16107033 | US |
