1. Field of the Invention
The present invention relates to a display apparatus, and more particularly, to a display apparatus having a plurality of controllers, and a video data processing method thereof.
2. Description of the Prior Art
Please refer to
The frame memory 112 is used to store the pixel data of a frame or other video data, therefore a size of the frame memory 112 must be large enough to store these data. For example, when a resolution of the display apparatus 100 is 640*480 (that is, a frame has 640*480 pixel data), the size of the frame memory 112 must be large enough to store 640*480 pixel data as well as other video data. Therefore, the controller has backward compatibility but does not have forward compatibility. That is, the controller 110 designed for a display apparatus with a resolution of 640*480 can be used in a display apparatus with a resolution of 320*240, but cannot be used in a display apparatus with a resolution of 1024*728 due to the insufficient capacity of the frame memory 112.
In addition, although the controller 110 designed for a display apparatus with a resolution of 640*480 can be used in a display apparatus with a resolution of 320*240, a large portion of the frame memory 112 is wasted. Therefore, the controller 110 needs to be re-designed for each resolution, meaning manufacturing costs are correspondingly increased.
It is an objective of the present invention to provide a display apparatus having a plurality of controllers, which has forward compatibility and is therefore able to save manufacturing costs, in order to solve the above-mentioned problems.
According to one embodiment of the present invention, a display apparatus comprises a first controller, a second controller and a display panel. The first controller includes a first memory and is used for receiving a first portion of pixel data of a frame and storing the first portion of the pixel data into the first memory. The second controller, which is external to the first controller and includes a second memory, is used for receiving a second portion of the pixel data of the frame and storing the second portion of the pixel data into the second memory. The display panel is used for receiving at least the first and the second portion of the pixel data outputted from the first and the second controllers, respectively.
According to another embodiment of the present invention, a video data processing method comprises: receiving a first portion of pixel data of a frame and storing the first portion of the pixel data into a first memory of a first controller; receiving a second portion of the pixel data of the frame and storing the second portion of the pixel data into a second memory of a second controller; and transmitting at least the first and the second portion of the pixel data from the first and the second controllers to a display panel, respectively.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Certain terms are used throughout the following description and claims to refer to particular system components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following discussion and in the claims, the terms “including” and “comprising” are used in an open-ended fashion, and thus should be interpreted to mean “including, but not limited to . . . ” The terms “couple” and “couples” are intended to mean either an indirect or a direct electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
Please refer to
In the operations of the display apparatus 200, the first controller 210 receives a clock signal, a first portion of pixel data, a vertical synchronous signal Vsync and a horizontal synchronous signal Hsync (video data shown in
Then, the first portion of the pixel data of the frame are sequentially transmitted to the output buffer 214 (i.e., the pixel data p1, p3, p5, . . . etc.), and the second portion of the pixel data of the frame are sequentially transmitted to the output buffer 224 (i.e., the pixel data p2, p4, . . . etc.). At the same time, the PLL 216 receives a reference clock Clk_ref to generate a synchronous signal Ps, and the first phase-adjust unit 218 phase-adjusts the synchronous signal to generate a first phase-adjusted synchronous signal Ps_1, and the second phase-adjust unit 228 phase-adjusts the synchronous signal to generate a second phase-adjusted synchronous signal Ps_2. The first and second phase-adjusted synchronous signals Ps_1 and Ps_2 are used to trigger the output buffers 214 and 224, respectively, to make the output buffers 214 and 224 synchronously output the first and the second portions of the pixel data to the display panel 230 (Data_A and Data_B shown in
It is noted that the first and second phase-adjust units 218 and 228 are used to phase-adjust the synchronous signal Ps to generate the first and second phase-adjusted synchronous signals Ps_1 and Ps_2, in order to make the first and the second output buffers synchronously output the first and the second portion of the pixel data to the display panel 230. That is, the first and second phase-adjust units 218 and 228 are used to make the first and second phase-adjusted synchronous signals Ps_1 and Ps_2 phase-match. If positions of the first controller 210 and the second controller 220 are close, however, the phase of the synchronous signal Ps received by the first controller 210 may be largely similar to the phase of the synchronous signal Ps received by the second controller 210. Therefore, the first and second phase-adjust units 218 and 228 are not required and can be removed without influencing the functions of the display apparatus 200, and the synchronous signal Ps is used to trigger the output buffers 214 and 224 to synchronously output the first and second portions of the pixel data to the display panel 230.
One advantage of the display apparatus 200 is as follows: assuming a resolution of the display apparatus 200 is 640*480 (VGA), a size of the first memory 212 of the first controller 210 can be designed to be capable of storing 640*240 pixel data, and a size of the second memory 222 of the second controller 220 can also be designed to be capable of storing 640*240 pixel data. Therefore, the first controller 210 can be independently used in a display apparatus with a resolution of 320*240 (QVGA) because the capacity of the first memory 212 is large enough for storing the pixel data of a frame in the display apparatus with the resolution of 320*240. That is, there is no need to re-design a controller for the display apparatus with a resolution of 320*240, and memory space is not wasted.
Another advantage is that, if a controller of a display apparatus with a resolution of 320*240 has been designed and the controller of the display apparatus with the resolution of 320*240 is capable of storing 640*240 pixel data, the controller display apparatus with the resolution of 320*240 can be further used in a display apparatus with a greater resolution. For example, assuming the resolution of the display apparatus 200 is 640*480, the first controller 210 does not need to be designed and can directly use the controller which is originally used in the display apparatus with the resolution of 320*240. That is, because the first controller 210 has been designed for the display apparatus with the resolution of 320*240, only the controller 220 needs to be provided (design of the second controller 220 is much easier than that of the first controller 210), and design of the display apparatus 200 is therefore simplified.
Please refer to
In the operations of the display apparatus 400, the first controller 410 receives a clock signal, a first portion of pixel data, a vertical synchronous signal Vsync and a horizontal synchronous signal Hsync (video data includes pixel data of a frame, the vertical synchronous signal Vsync and the horizontal synchronous signal Hsync) and stores at least the first portion of the pixel data into the first memory 412. The second controller 420 receives the clock signal, a second portion of the pixel data and stores at least the second portion of the pixel data into the second memory 422. The third controller 430 receives the clock signal, a third portion of the pixel data and stores at least the third portion of the pixel data into the third memory 432. In addition, in this embodiment, the first, second and third portions of the pixel data include one-third of the pixel data of the frame, respectively, and more particularly, taking the frame 300 shown in
Then, the first portion of the pixel data of the frame are sequentially transmitted to the output buffer 414 (i.e., the pixel data p1, p4, p7, . . . etc.), the second portion of the pixel data of the frame are sequentially transmitted to the output buffer 424 (i.e., the pixel data p2, p5, p8, . . . etc.), and the third portion of the pixel data of the frame are sequentially transmitted to the output buffer 434 (i.e., the pixel data p3, p6, . . . etc.). At the same time, the PLL 416 receives a reference clock Clk_ref to generate a synchronous signal Ps. The synchronous signal Ps is used to trigger the output buffers 414, 424 and 434, to make the output buffers 414, 424 and 434 synchronously output the first, second and third portions of the pixel data to the display panel 440, respectively (Data_A, Data_B and Data_C shown in
It is noted that the phase-adjust units shown in
In addition, the display apparatuses 200 and 400 can be color-sequential LCOS (Liquid Crystal on Silicon) display apparatuses, and the display panels 230 and 440 are color-sequential LCOS display panels.
Briefly summarized, the display apparatus of the present invention has a plurality of controllers, and each controller is used for receiving a portion of pixel data of a frame and storing the portion of the pixel data into its memory. Then, the pixel data stored in the memories are synchronously transmitted to a display panel. The display apparatus of the present invention can simplify the design of the controller, and manufacture cost is therefore decreased.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.