Patent Application
20160086529
This disclosure relates to the field of displays, and in particular, to image formation processes used by displays.
Electromechanical systems (EMS) include devices having electrical and mechanical elements, actuators, transducers, sensors, optical components such as mirrors and optical films, and electronics. EMS devices or elements can be manufactured at a variety of scales including, but not limited to, microscales and nanoscales. For example, microelectromechanical systems (MEMS) devices can include structures having sizes ranging from about a micron to hundreds of microns or more. Nanoelectromechanical systems (NEMS) devices can include structures having sizes smaller than a micron including, for example, sizes smaller than several hundred nanometers. Electromechanical elements may be created using deposition, etching, lithography, and/or other micromachining processes that etch away parts of substrates and/or deposited material layers, or that add layers to form electrical and electromechanical devices.
The systems, methods and devices of the disclosure each have several innovative aspects, no single one of which is solely responsible for the desirable attributes disclosed herein.
One innovative aspect of the subject matter described in this disclosure can be implemented in an apparatus, including input logic configured to receive image data associated with an image frame, subfield generation logic configured to derive a composite color subfield based on the received image frame, where the derived composite color subfield identifies a composite color intensity value with respect to each of a plurality of display elements in a display for the received image frame, subframe generation logic configured to generate a plurality of at least partially temporally weighted subframes for the derived composite color subfield, where each generated subframe has a default illumination duration, has a default illumination intensity, and indicates states of the respective display elements in the display, an ambient light sensor configured to measure an ambient light level, and control logic configured to, based on a determination that the ambient light level fails to exceed an ambient light threshold, display a first of the generated subframes associated with the composite color subfield during at least two separate illumination periods.
In some implementations, a combined duration of the at least two illumination periods is substantially equal to the default illumination duration associated with the first of the generated subframes. In some implementations, the control logic is further configured to increase illumination intensities of one or more light sources being illuminated during display of the first of the generated subframes during the at least two separate illumination periods to be greater than the default illumination intensity. In some implementations, the control logic is further configured to increase the illumination intensities for the first of the generated subframes as a function of a decrease in the illumination duration for the first of the generated subframe from its default illumination duration.
In some implementations, the subfield generation logic is further configured to generate color subfields for a plurality of component colors. In some implementations, the control logic is configured to, upon determining that the ambient light levels exceed the ambient light threshold, display each of the generated subframes associated with the composite color as individual, temporally contiguous subframes. In some implementations, the determination that the ambient level fails to exceed the ambient light threshold includes a determination that an ambient light-to-display brightness ratio fails to exceed an ambient light-to-display brightness ratio threshold. In some implementations, the plurality of display elements include MEMS shutter-based light modulators.
In some implementations, the apparatus further includes a display, a processor that is capable of communicating with the display, the processor being capable of processing image data, and a memory device that is capable of communicating with the processor. In some implementations, the display further includes a driver circuit capable of sending at least one signal to the display, and a controller capable of sending at least a portion of the image data to the driver circuit. In some implementations, the display further includes an image source module capable of sending the image data to the processor, where the image source module includes at least one of a receiver, transceiver, and transmitter.
Another innovative aspect of the subject matter described in this disclosure can be implemented in a method of forming an image on a display including receiving image data associated with an image frame, deriving a composite color subfield for the received image frame, where the derived composite color subfield identifies a composite color intensity value with respect to each of a plurality of display elements in a display for the received image frame, generating a plurality of at least partially temporally weighted subframes for the derived composite color subfield, where each generated subframe has a default illumination duration, has a default illumination intensity, and indicates states of the respective display elements in the display, measuring an ambient light level, and displaying, based on a determination that the ambient light level fails to exceed an ambient light threshold, a first of the generated subframes associated with the composite color subfield during at least two separate illumination periods.
In some implementations, displaying a first of the generated subframes during at least two separate illumination periods includes displaying the first of the generated subframe such that a combined duration of the at least two illumination periods is substantially equal to the default illumination duration associated with the first of the generated subframes. In some implementations, the method further includes increasing illumination intensities of one or more light sources being illuminated during display of the first of the generated subframes during the at least two separate illumination periods to be greater than the default illumination intensity. In some implementations, increasing illumination intensities of one or more light sources being illuminated during display of the first of the generated subframes as a function of a decrease in the illumination duration of the first of the generated subframes from its default illumination duration.
In some implementations, the method further includes generating color subfields for a plurality of component colors. In some implementations, the method further includes, upon determining that the ambient light levels exceed the ambient light threshold, displaying each of the generated subframes associated with the composite color subfield as individual, temporally contiguous subframes. In some implementations, the determination that the ambient level fails to exceed the ambient light threshold includes a determination that an ambient light-to-display brightness ratio fails to exceed an ambient light-to-display brightness ratio threshold.
Another innovative aspect of the subject matter described in this disclosure can be implemented in a non-transitory computer readable storage medium having instructions encoded thereon, which when executed by a processor cause the processor to perform a method for displaying an image, including receiving image data associated with an image frame, deriving a composite color subfield for the received image frame, where the derived composite color subfield identifies a composite color intensity value with respect to each of a plurality of display elements in a display for the received image frame, generating a plurality of at least partially temporally weighted subframes for the derived composite color subfield, where each generated subframe has a default illumination duration, has a default illumination intensity, and indicates states of the respective display elements in the display, measuring an ambient light level, and displaying, based on a determination that the ambient light level fails to exceed an ambient light threshold, a first of the generated subframes associated with the composite color subfield during at least two separate illumination periods.
In some implementations, displaying a first of the generated subframes during at least two separate illumination periods includes displaying the first of the generated subframe such that a combined duration of the at least two illumination periods is substantially equal to the default illumination duration associated with the first of the generated subframes.
Details of one or more implementations of the subject matter described in this disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, the drawings and the claims. Note that the relative dimensions of the following figures may not be drawn to scale.
Like reference numbers and designations in the various drawings indicate like elements.
The following description is directed to certain implementations for the purposes of describing the innovative aspects of this disclosure. However, a person having ordinary skill in the art will readily recognize that the teachings herein can be applied in a multitude of different ways. The described implementations may be implemented in any device, apparatus, or system that is capable of displaying an image, whether in motion (such as video) or stationary (such as still images), and whether textual, graphical or pictorial. The concepts and examples provided in this disclosure may be applicable to a variety of displays, such as liquid crystal displays (LCDs), organic light-emitting diode (OLED) displays, field emission displays, and electromechanical systems (EMS) and microelectromechanical (MEMS)-based displays, in addition to displays incorporating features from one or more display technologies.
The described implementations may be included in or associated with a variety of electronic devices such as, but not limited to: mobile telephones, multimedia Internet enabled cellular telephones, mobile television receivers, wireless devices, smartphones, Bluetooth® devices, personal data assistants (PDAs), wireless electronic mail receivers, hand-held or portable computers, netbooks, notebooks, smartbooks, tablets, printers, copiers, scanners, facsimile devices, global positioning system (GPS) receivers/navigators, cameras, digital media players (such as MP3 players), camcorders, game consoles, wrist watches, wearable devices, clocks, calculators, television monitors, flat panel displays, electronic reading devices (such as e-readers), computer monitors, auto displays (such as odometer and speedometer displays), cockpit controls and/or displays, camera view displays (such as the display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, microwaves, refrigerators, stereo systems, cassette recorders or players, DVD players, CD players, VCRs, radios, portable memory chips, washers, dryers, washer/dryers, parking meters, packaging (such as in electromechanical systems (EMS) applications including microelectromechanical systems (MEMS) applications, in addition to non-EMS applications), aesthetic structures (such as display of images on a piece of jewelry or clothing) and a variety of EMS devices.
The teachings herein also can be used in non-display applications such as, but not limited to, electronic switching devices, radio frequency filters, sensors, accelerometers, gyroscopes, motion-sensing devices, magnetometers, inertial components for consumer electronics, parts of consumer electronics products, varactors, liquid crystal devices, electrophoretic devices, drive schemes, manufacturing processes and electronic test equipment. Thus, the teachings are not intended to be limited to the implementations depicted solely in the Figures, but instead have wide applicability as will be readily apparent to one having ordinary skill in the art.
In some image formation processes, a controller can form an image by utilizing a set of color subfields and displaying subframes associated with each of the color subfields. In some implementations, the controller can utilize a set of color subfields including colors such as red, green, blue, and composite colors that are formed from the combination of two or more other subfields. For example some composite color subfields (also referred to as “x-channel”) can be a composite of colors red, green, and blue. In some implementations, the controller may determine whether to divide or split the display of certain subframes based on environmental factors such as ambient light with or without concern for flicker. In some implementations, dividing or splitting the display of a subframe can include displaying the same subframe over two or more illumination periods. In some implementations, the controller may determine to divide or split the display of an x-channel subframe based on the ambient light. The controller can monitor the ambient light levels via an ambient light sensor, and compare the ambient light level to an ambient light threshold. If the ambient light levels go below the ambient light threshold, the controller can employ subframe division or splitting.
Particular implementations of the subject matter described in this disclosure can be implemented to realize one or more of the following potential advantages. In general, image formation processes disclosed herein mitigate image artifacts, and improve image quality, by dividing an illumination period of a subframe into two or more illumination periods. In some implementations, dividing the illumination period of a subframe can result in an increase in power consumption. By basing the decision on whether to divide illumination periods of subframes on environmental conditions such as ambient light levels, the image formation process can balance improved image quality with increased power consumption.
In some implementations, each light modulator 102 corresponds to a pixel 106 in the image 104. In some other implementations, the display apparatus 100 may utilize a plurality of light modulators to form a pixel 106 in the image 104. For example, the display apparatus 100 may include three color-specific light modulators 102. By selectively opening one or more of the color-specific light modulators 102 corresponding to a particular pixel 106, the display apparatus 100 can generate a color pixel 106 in the image 104. In another example, the display apparatus 100 includes two or more light modulators 102 per pixel 106 to provide a luminance level in an image 104. With respect to an image, a pixel corresponds to the smallest picture element defined by the resolution of image. With respect to structural components of the display apparatus 100, the term pixel refers to the combined mechanical and electrical components utilized to modulate the light that forms a single pixel of the image.
The display apparatus 100 is a direct-view display in that it may not include imaging optics typically found in projection applications. In a projection display, the image formed on the surface of the display apparatus is projected onto a screen or onto a wall. The display apparatus is substantially smaller than the projected image. In a direct view display, the image can be seen by looking directly at the display apparatus, which contains the light modulators and optionally a backlight or front light for enhancing brightness and/or contrast seen on the display.
Direct-view displays may operate in either a transmissive or reflective mode. In a transmissive display, the light modulators filter or selectively block light which originates from a lamp or lamps positioned behind the display. The light from the lamps is optionally injected into a lightguide or backlight so that each pixel can be uniformly illuminated. Transmissive direct-view displays are often built onto transparent substrates to facilitate a sandwich assembly arrangement where one substrate, containing the light modulators, is positioned over the backlight. In some implementations, the transparent substrate can be a glass substrate (sometimes referred to as a glass plate or panel), or a plastic substrate. The glass substrate may be or include, for example, a borosilicate glass, wine glass, fused silica, a soda lime glass, quartz, artificial quartz, Pyrex, or other suitable glass material.
Each light modulator 102 can include a shutter 108 and an aperture 109. To illuminate a pixel 106 in the image 104, the shutter 108 is positioned such that it allows light to pass through the aperture 109. To keep a pixel 106 unlit, the shutter 108 is positioned such that it obstructs the passage of light through the aperture 109. The aperture 109 is defined by an opening patterned through a reflective or light-absorbing material in each light modulator 102.
The display apparatus also includes a control matrix coupled to the substrate and to the light modulators for controlling the movement of the shutters. The control matrix includes a series of electrical interconnects (such as interconnects 110, 112 and 114), including at least one write-enable interconnect 110 (also referred to as a scan line interconnect) per row of pixels, one data interconnect 112 for each column of pixels, and one common interconnect 114 providing a common voltage to all pixels, or at least to pixels from both multiple columns and multiples rows in the display apparatus 100. In response to the application of an appropriate voltage (the write-enabling voltage, VWE), the write-enable interconnect 110 for a given row of pixels prepares the pixels in the row to accept new shutter movement instructions. The data interconnects 112 communicate the new movement instructions in the form of data voltage pulses. The data voltage pulses applied to the data interconnects 112, in some implementations, directly contribute to an electrostatic movement of the shutters. In some other implementations, the data voltage pulses control switches, such as transistors or other non-linear circuit elements that control the application of separate drive voltages, which are typically higher in magnitude than the data voltages, to the light modulators 102. The application of these drive voltages results in the electrostatic driven movement of the shutters 108.
The control matrix also may include, without limitation, circuitry, such as a transistor and a capacitor associated with each shutter assembly. In some implementations, the gate of each transistor can be electrically connected to a scan line interconnect. In some implementations, the source of each transistor can be electrically connected to a corresponding data interconnect. In some implementations, the drain of each transistor may be electrically connected in parallel to an electrode of a corresponding capacitor and to an electrode of a corresponding actuator. In some implementations, the other electrode of the capacitor and the actuator associated with each shutter assembly may be connected to a common or ground potential. In some other implementations, the transistor can be replaced with a semiconducting diode, or a metal-insulator-metal switching element.
The display apparatus 128 includes a plurality of scan drivers 130 (also referred to as write enabling voltage sources), a plurality of data drivers 132 (also referred to as data voltage sources), a controller 134, common drivers 138, lamps 140-146, lamp drivers 148 and an array of display elements 150, such as the light modulators 102 shown in
In some implementations of the display apparatus, the data drivers 132 are capable of providing analog data voltages to the array of display elements 150, especially where the luminance level of the image is to be derived in analog fashion. In analog operation, the display elements are designed such that when a range of intermediate voltages is applied through the data interconnects 133, there results a range of intermediate illumination states or luminance levels in the resulting image. In some other implementations, the data drivers 132 are capable of applying only a reduced set, such as 2, 3 or 4, of digital voltage levels to the data interconnects 133. In implementations in which the display elements are shutter-based light modulators, such as the light modulators 102 shown in
The scan drivers 130 and the data drivers 132 are connected to a digital controller circuit 134 (also referred to as the controller 134). The controller 134 sends data to the data drivers 132 in a mostly serial fashion, organized in sequences, which in some implementations may be predetermined, grouped by rows and by image frames. The data drivers 132 can include series-to-parallel data converters, level-shifting, and for some applications digital-to-analog voltage converters.
The display apparatus optionally includes a set of common drivers 138, also referred to as common voltage sources. In some implementations, the common drivers 138 provide a DC common potential to all display elements within the array 150 of display elements, for instance by supplying voltage to a series of common interconnects 139. In some other implementations, the common drivers 138, following commands from the controller 134, issue voltage pulses or signals to the array of display elements 150, for instance global actuation pulses which are capable of driving and/or initiating simultaneous actuation of all display elements in multiple rows and columns of the array.
Each of the drivers (such as scan drivers 130, data drivers 132 and common drivers 138) for different display functions can be time-synchronized by the controller 134. Timing commands from the controller 134 coordinate the illumination of red, green, blue and white lamps (140, 142, 144 and 146 respectively) via lamp drivers 148, the write-enabling and sequencing of specific rows within the array of display elements 150, the output of voltages from the data drivers 132, and the output of voltages that provide for display element actuation. In some implementations, the lamps are light emitting diodes (LEDs).
The controller 134 determines the sequencing or addressing scheme by which each of the display elements can be re-set to the illumination levels appropriate to a new image 104. New images 104 can be set at periodic intervals. For instance, for video displays, color images or frames of video are refreshed at frequencies ranging from 10 to 300 Hertz (Hz). In some implementations, the setting of an image frame to the array of display elements 150 is synchronized with the illumination of the lamps 140, 142, 144 and 146 such that alternate image frames are illuminated with an alternating series of colors, such as red, green, blue and white. The image frames for each respective color are referred to as color subframes. In this method, referred to as the field sequential color method, if the color subframes are alternated at frequencies in excess of 20 Hz, the human visual system (HVS) will average the alternating frame images into the perception of an image having a broad and continuous range of colors. In some other implementations, the lamps can employ primary colors other than red, green, blue and white. In some implementations, fewer than four, or more than four lamps with primary colors can be employed in the display apparatus 128.
In some implementations, where the display apparatus 128 is designed for the digital switching of shutters, such as the shutters 108 shown in
In some implementations, the data for an image state is loaded by the controller 134 to the array of display elements 150 by a sequential addressing of individual rows, also referred to as scan lines. For each row or scan line in the sequence, the scan driver 130 applies a write-enable voltage to the write enable interconnect 131 for that row of the array of display elements 150, and subsequently the data driver 132 supplies data voltages, corresponding to desired shutter states, for each column in the selected row of the array. This addressing process can repeat until data has been loaded for all rows in the array of display elements 150. In some implementations, the sequence of selected rows for data loading is linear, proceeding from top to bottom in the array of display elements 150. In some other implementations, the sequence of selected rows is pseudo-randomized, in order to mitigate potential visual artifacts. And in some other implementations, the sequencing is organized by blocks, where, for a block, the data for only a certain fraction of the image is loaded to the array of display elements 150. For example, the sequence can be implemented to address only every fifth row of the array of the display elements 150 in sequence.
In some implementations, the addressing process for loading image data to the array of display elements 150 is separated in time from the process of actuating the display elements. In such an implementation, the array of display elements 150 may include data memory elements for each display element, and the control matrix may include a global actuation interconnect for carrying trigger signals, from the common driver 138, to initiate simultaneous actuation of the display elements according to data stored in the memory elements.
In some implementations, the array of display elements 150 and the control matrix that controls the display elements may be arranged in configurations other than rectangular rows and columns. For example, the display elements can be arranged in hexagonal arrays or curvilinear rows and columns.
The host processor 122 generally controls the operations of the host device 120. For example, the host processor 122 may be a general or special purpose processor for controlling a portable electronic device. With respect to the display apparatus 128, included within the host device 120, the host processor 122 outputs image data as well as additional data about the host device 120. Such information may include data from environmental sensors 124, such as ambient light or temperature; information about the host device 120, including, for example, an operating mode of the host or the amount of power remaining in the host device's power source; information about the content of the image data; information about the type of image data; and/or instructions for the display apparatus 128 for use in selecting an imaging mode.
In some implementations, the user input module 126 enables the conveyance of personal preferences of a user to the controller 134, either directly, or via the host processor 122. In some implementations, the user input module 126 is controlled by software in which a user inputs personal preferences, for example, color, contrast, power, brightness, content, and other display settings and parameters preferences. In some other implementations, the user input module 126 is controlled by hardware in which a user inputs personal preferences. In some implementations, the user may input these preferences via voice commands, one or more buttons, switches or dials, or with touch-capability. The plurality of data inputs to the controller 134 direct the controller to provide data to the various drivers 130, 132, 138 and 148 which correspond to optimal imaging characteristics.
The environmental sensor module 124 also can be included as part of the host device 120. The environmental sensor module 124 can be capable of receiving data about the ambient environment, such as temperature and or ambient lighting conditions. The sensor module 124 can be programmed, for example, to distinguish whether the device is operating in an indoor or office environment versus an outdoor environment in bright daylight versus an outdoor environment at nighttime. The sensor module 124 communicates this information to the display controller 134, so that the controller 134 can optimize the viewing conditions in response to the ambient environment.
In the depicted implementation, the shutter 206 includes two shutter apertures 212 through which light can pass. The aperture layer 207 includes a set of three apertures 209. In
Each aperture has at least one edge around its periphery. For example, the rectangular apertures 209 have four edges. In some implementations, in which circular, elliptical, oval, or other curved apertures are formed in the aperture layer 207, each aperture may have only a single edge. In some other implementations, the apertures need not be separated or disjointed in the mathematical sense, but instead can be connected. That is to say, while portions or shaped sections of the aperture may maintain a correspondence to each shutter, several of these sections may be connected such that a single continuous perimeter of the aperture is shared by multiple shutters.
In order to allow light with a variety of exit angles to pass through the apertures 212 and 209 in the open state, the width or size of the shutter apertures 212 can be designed to be larger than a corresponding width or size of apertures 209 in the aperture layer 207. In order to effectively block light from escaping in the closed state, the light blocking portions of the shutter 206 can be designed to overlap the edges of the apertures 209.
The electrostatic actuators 202 and 204 are designed so that their voltage-displacement behavior provides a bi-stable characteristic to the shutter assembly 200. For each of the shutter-open and shutter-close actuators, there exists a range of voltages below the actuation voltage, which if applied while that actuator is in the closed state (with the shutter being either open or closed), will hold the actuator closed and the shutter in position, even after a drive voltage is applied to the opposing actuator. The minimum voltage needed to maintain a shutter's position against such an opposing force is referred to as a maintenance voltage Vm.
The display module 304 further includes control logic 306, a frame buffer 308, an array of display elements 310, display drivers 312 and a backlight 314. In general, the control logic 306 serves to process image data received from the host device 302 and controls the display drivers 312, array of display elements 310 and backlight 314 to together produce the images encoded in the image data. The functionality of the control logic 306 is described further below in relation to
In some implementations, as shown in
The interface chip 318 can be configured to carry out more routine operations of the display module 304. The operations may include retrieving image subframes from the frame buffer 308 and outputting control signals to the display drivers 312 and the backlight 314 in response to the retrieved image subframe and the output sequence determined by the microprocessor 316. The frame buffer 308 can be any volatile or non-volatile integrated circuit memory, such as DRAM, high-speed cache memory, or flash memory (for example, the frame buffer 308 can be similar to the frame buffer 28 shown in
In some other implementations, the functionality of the microprocessor 316 and the interface chip 318 are combined into a single logic device, which may take the form of a microprocessor, an ASIC, a field programmable gate array (FPGA) or other programmable logic device. For example, the functionality of the microprocessor 316 and the interface chip 318 can be implemented by a processor 21 shown in
The array of display elements 310 can include an array of any type of display elements that can be used for image formation. In some implementations, the display elements can be EMS light modulators. In some such implementations, the display elements can be MEMS shutter-based light modulators similar to those shown in
The display drivers 312 can include a variety of drivers depending on the specific control matrix used to control the display elements in the array of display elements 310. In some implementations, the display drivers 312 include a plurality of scan drivers similar to the scan drivers 130, a plurality of data drivers similar to the data drivers 132, and a set of common drivers similar to the common drivers 138, all shown in
In some implementations, particularly for larger display modules 304, the control matrix used to control the display elements in the array of display elements 310 is segmented into multiple regions. For example, the array of display elements 310 shown in
In some implementations, the display elements in the array of display elements can be utilized in a direct-view transmissive display. In direct-view transmissive displays, the display elements, such as EMS light modulators, selectively block light that originates from a backlight, which is illuminated by one or more lamps. Such display elements can be fabricated on transparent substrates, made, for example, from glass. In some implementations, the display drivers 312 are coupled directly to the glass substrate on which the display elements are formed. In such implementations, the drivers are built using a chip-on-glass configuration. In some other implementations, the drivers are built on a separate circuit board and the outputs of the drivers are coupled to the substrate using, for example, flex cables or other wiring.
The backlight 314 can include a light guide, one or more light sources (such as LEDs), and light source drivers. The light sources can include light sources of multiple primary colors, such as red, green, blue, and in some implementations white. The light source drivers are configured to individually drive the light sources to a plurality of discrete light levels to enable illumination gray scale and/or content adaptive backlight control (CABC) in the backlight. For example, CABC can include dynamically normalizing the intensity values of one or more subfields such that the maximum intensity value in each normalized subfield is scaled to the maximum intensity value output by the display scaling down the illumination levels of the corresponding LEDs accordingly. The light guide distributes the light output by light sources substantially evenly beneath the array of display elements 310. In some other implementations, for example for displays including reflective display elements, the display apparatus 300 can include a front light or other form of lighting instead of a backlight. The illumination of such alternative light sources can likewise be controlled according to illumination grayscale processes that incorporate content adaptive control features. For ease of explanation, the display processes discussed herein are described with respect to the use of a backlight. However, it would be understood by a person of ordinary skill that such processes also may be adapted for use with a front light or other similar form of display lighting.
In some implementations, the display module 304 can include or be coupled to an ambient light sensor 322 and/or a proximity sensor 324. The ambient light sensor 322 can sense a level of background illumination. In some implementations, the ambient light sensor 322 can output a voltage/current, or a digital output corresponding to the ambient light level. Likewise, the proximity sensor 324 can output a voltage/current or a digital output corresponding to the proximity of a viewer to the display module 304. As discussed below, the microprocessor 316 can utilize the ambient light sensor 322 and/or the proximity sensor 324 in determining the ambient light levels and the proximity of the viewer from the display module 304. This information can be used by the microprocessor 316 to control various aspects of the display module 304 to reduce flicker.
The input logic 402 is configured to receive the input image data as a stream of pixel intensity values, and present the pixel intensity values to other modules within the control logic 400. The subfield derivation logic 404 can derive color subfields (e.g., red, green, blue, white, etc.) based on the pixel intensity values. The flicker control logic 406 can detect the potential for flicker and coordinate with the output logic 410 and the subframe generation logic 408 to mitigate that potential. The subframe generation logic 408 can generate subframes for each of the color subfields based on an output sequence and the pixel intensity values. The CABC logic 412 can implement CABC techniques for reducing power consumption. The output logic 410 can coordinate with one or more of the other logic components to determine an appropriate output sequence, and then use the output sequence to display the subframes on the display.
In some implementations, when executed by the microprocessor 316, the components of the control logic 400, along with the interface chip 318, display drivers 312, and backlight 314 (all shown in
Referring to
In some implementations, the method further includes preprocessing the received image frame (stage 504). For example, in some implementations, the image data includes color intensity values for more pixels or fewer pixels than are included in the display apparatus 128. In such cases, the input logic 402, the subfield derivation logic 404, or other logic incorporated into the controller 400 can scale the image data appropriately to the number of pixels included in the display apparatus 128. In some other implementations, the image frame data is received having been encoded assuming a given display gamma. In some implementations, if such gamma encoding is detected, logic within the controller 400 applies a gamma correction process to adjust the pixel intensity values to be more appropriate for the gamma of the display apparatus 128. For example, image data is often encoded based on the gamma of a typical liquid crystal (LCD) display. To address this common gamma encoding, the controller 400 may store a gamma correction lookup table (LUT) from which it can quickly retrieve appropriate intensity values given a set of LCD gamma encoded pixel values. In some implementations, the LUT includes corresponding RGB intensity values having a 16 bit-per-color resolution, though other color resolutions may be used in other implementations.
In some implementations, image frame preprocessing (stage 504) includes a dithering stage. In some implementations, the process of de-gamma encoding an image results in 16 bit-per-color pixel values, even though the display apparatus 128 may not be configured for displaying such a large number of bits per color. A dithering process can help distribute any quantization error associated with converting these pixel values down to a color resolution available to the display, such as 4, 5, 6, or 8 bits per color.
In some implementations, the image preprocessing (stage 504) can include the subfield derivation logic 404 selecting a set of color subfields for displaying the image frame. In some implementations, the selected color subfields can include, frame independent contributing colors (FICCs) such as, without limitations, the colors red (R), green (G), blue (B), white (W), yellow (Y), magenta (M), cyan (C), or one or more combinations thereof. FICCs are selected independently of the image content or data associated with the image frame. In some implementations, the FICCs can include composite colors that are formed from the combination of two or more other FICCs. In some implementations, the selection of color subfields can include selecting a frame specific contributing color (FSCC). FSCCs are typically determined based on the image data associated with the current and/or one or more previous image frames. In some implementations, the subfield derivation logic 404 can be utilized to determine intensity values for each of the pixels in an FSCC color subfield and to adjust the intensities of the FICCs for each pixel of the display based on the determined FSCC intensity values.
As mentioned above, the FSCCs can be selected based on the image data associated with an image frame. In some implementations, the FSCC can be selected based on converting received image data into XYZ tristimulus values, identifying a color corresponding to the median (or mean) of the tristimulus values, and setting the FSCC to, or based on, the identified color. In some implementations, the identified color is compared to a set of available FSCCs, and the FSCC is set to the available FSCC that is closest to the identified color. In some implementations, the FSCC can be selected between white and any color that is near to the boundaries of the available color gamut utilized for the display. In some other implementations, the FSCC can be selected based on the dominant hue within the image frame. In some implementations, the FSCC can be selected from one of, or a combination of, the following colors: white, yellow, cyan, magenta, etc.
In some implementations, the image preprocessing (stage 504) can include updating the subfields using CABC. The CABC logic 412, after the FSCC subfields and FICC subfields are derived, can normalize the intensity values in one or more of the subfields such that the maximum intensity value in each normalized subfield is scaled to the maximum intensity value output by the display. For example, in a display capable of outputting 256 gray scale levels, the subfield values are scaled such that the maximum intensity value therein is equal to 255. The illumination levels of the corresponding LEDs can be accordingly scaled down. The scaling factor for the LEDs can be used by the output logic 410 for adjusting the LED illumination levels.
The process 500 further includes generating an output sequence to use in displaying the received image (stage 506). An output sequence for a given image frame includes a series of events for displaying a series of subframes associated with the image frame. In some implementations, the output sequence can include a series of data and control signals to drivers, such as the data drivers 132, scan drivers 130 and lamp drivers 148 shown in
The generation of the output sequence can include several processing stages, which are described in detail below in relation to
The process 500 further includes generating subframes (stage 508). The subframe generation logic 408 can generate a set of subframes based on the output sequence and the intensity values for each subfield color for each pixel. The generated subframes can be loaded into an array of display elements, such as the array 150 of display elements shown in
The process 500 further includes presenting the subframes for display (stage 510). Once the output sequence is generated by the control logic 400 (stage 506) and the subframes for the image frame have been generated (stage 408), the output logic 410 uses the output sequence to display the subframes on the display. The output logic 410 can be configured to control output signals to a remainder of the components of the display apparatus to cause the subframes to be presented to a viewer. For example, if used in the display apparatus 128 shown in
The process 550 includes determining initial numbers, weights, and timings of subframes to be displayed (stage 511). In some implementations, the subframe generation logic 408 can determine the initial numbers, weights and durations of subframes to be used for displaying each FICC and the FSCC subfield. In some implementations, the initial numbers, weights, and the durations of the subframes used for displaying the FICC and the FSCC subfields can be based on the display techniques used. For example, in some grayscale field sequential color technique, the subframes can be binary weighted. According to a binary weighted scheme, each successive subframe for a given FICC or FSCC is assigned a weight that is twice that of the subframe having the next lower weight, for example, 1, 2, 4, 8, 16, 32, etc.
In some implementations, the weights can be assigned to successively weighted subframes based on a non-binary weighing scheme. In some such implementations, the output sequence can include multiple subframes of the same color having the same weight and/or include subframes whose weights are more or less than twice the weight of the subframe having the next lower weight. For example, in some implementations, successive subframes for a given color may have weights such as 80, 32, 16, 8, 4, 1, 2, 32, and 80. Generally, the duration of each subframe can be determined based on the relative weight associated with the subframe. For example, when the subframes are binary weighted as discussed above, assuming a constant illumination level for each subframe, the duration of each successively weighted subframe would be twice the duration of the next lower weighted subframe.
The process 550 includes calculating a critical flicker frequency (CFF) associated with each subframe of each color (stage 512). The CFF for a subframe of a color is the minimum frequency at which the subframe of that color must be illuminated to avoid the perception of flicker by a viewer. The actual frequency at with which a subframe is displayed is referred to herein as the “illumination frequency” of the subframe. In some implementations, the illumination frequency of a subframe is about the same as the frame rate of the display (i.e., the rate at which image frames are displayed by the display apparatus 300). Thus, if the display apparatus 300 displays image frames at a frame rate of 60 Hz, then the illumination frequency of each subframe may also be about 60 Hz. In some such implementations, flicker can be avoided for a subframe if the illumination frequency of the subframe is greater than the CFF.
The flicker control logic 406 (shown in
The CFF model takes into account the width w and height h of the display module 304 from a given diagonal measurement dg and an aspect ratio ar of the display module 304. For example,
The CFF model also takes into account a display visual angle θ subtended by the display module 300 on the viewer's eye. For example, the display visual angle θ can be determined by:
where D represents a display diameter of the display module 304 and can be approximated by the greater of the width w and the height h of the display module 304; and V represents the viewing distance between the display module and the viewer. In some implementations, the viewing distance V can be determined using the proximity sensor 324 (shown in
The CFF model also considers a display luminance Lr of the display module 304 in the OFF state. In some implementations, the display luminance Lr can represent the ambient light levels in relation to the display module 304. In some implementations, Lr may be calculated as follows:
L
r
=r
d
L
a (4)
where rd represents a display reflectance and La represents an adaptation luminance of the display module 304. The display reflectance rd (also know as display reflectivity) is the fraction of incident light power that is reflected from the surface of the display module 304 facing the viewer. The display reflectance rd is typically expressed as a percentage (such as about 10% to about 70%). The adaptation luminance La (also known as “adaptation brightness”) represents the average luminance of objects and surfaces in the immediate vicinity of the viewer and is a function of the ambient light level. The adaptation luminance La can range from about 320 lux to about 500 lux for surfaces illuminated by indoor (e.g., office) lighting, from about 1000 lux to about 25000 Klux for surfaces illuminated by full daylight, and from about 32000 lux to about 1000000 lux for surfaces illuminated by direct sunlight.
As discussed above, the output sequence determination (stage 511) can include identifying the time periods of various subframes for each of the subfield colors. In some implementations, the subfield colors can include red, green, and blue. In some implementations, the subfield colors may also include an “x-channel color,” which can include composite colors, such as white, cyan, magenta, yellow, etc. In some implementations, the x-channel color can be a FSCC, which is discussed above in relation to preprocessing the image frame in stage 504 of
t
R=τRwR; tG=τGwG; tB=τBwB; and tX=τXwX (5)
where tR, tG, tB, and tx, represent the time periods corresponding to subframes of colors red, green, blue, and x, respectively; τR, τG, τB, and τx, represent time period of the least significant subframe; and wR, wG, wB, and wx, represent the relative weights of the corresponding subframe. As an example, if the weight of a subframe for the color red (R) is 16, and the time period for the least significant subframe (having weight equal to 1) for the color red is 6 μs, then the time period for that subframe would be equal to 16×6 μs=96 μs.
The CFF model also incorporates a DC retinal luminance factor, Eobs, for a viewer. To determine the value of Eobs, the flicker control logic 406 determines a pupil diameter dp corresponding to a given display luminance Lt in the ON state from Crawford's formula, as shown below:
d
p=5−2.2 tan h(0.61151+0.447 log10Lt) (6)
In some implementations, the value of the pupil diameter may be kept at a constant value (or a pre-selected range of values) determined, for example, by experimentation. In some implementations, values for dp based on various Lt levels are stored in a LUT accessible by the flicker control module 406.
The CFF model also considers a pupil area Ap corresponding to the pupil diameter dp, as follows:
Subsequently, the DC retinal luminance Eobs is determined as follows:
E
obs=(Lt−Lr)Ap (8)
where, as discussed above, Lt and Lr represent the display luminance in the ON and the OFF states of the display module 304, respectively.
The CFF model also takes into consideration amplitudes of the fundamental components of each subframe of each color. For example, the amplitude AR of a red subframe can be determined as follows:
where, C represents the contrast ratio of the display module 304; tR, as determined above in Equation (5), represents the illumination time for that subframe; and T represents the illumination time of the image frame (i.e., reciprocal of the image frame rate). The amplitude AG, AB, and AX, of the subframes associated with the other colors green, blue, and x can be similarly determined.
With the DC retinal luminance Eobs and the amplitude AR, AG, AB, and AX known, the flicker control module 406 can determine the DC component of the luminance for each subframe. For example, the DC component of the luminance (Eobs(R)) for a red subframe can be determined as follows:
E
obs(R)
=E
obs
A
R
v
R (10)
where, vR represents the relative illumination intensity of the red subframe. In some implementations, the relative illumination intensity of the color red can represent the photopic weight of the color red. In some implementations, for example, the photopic weights for the colors red, green, and blue can be about 20%, about 70%, and about 10%, respectively. In a similar manner, the DC component of the luminances Eobs(G), Eobs(B), and Eobs(x) can be determined.
Finally, the flicker control module 406 determines the CFF for each subframe of each color. For example, the CFF of a subframe of the color red (R) can be determined as follows:
CFF(R)=m+n ln Eobs(R) (11)
where m and n represent regression coefficients determined for the display visual angle θ, determined above in Equation (3). In some implementations, for example, the regression coefficients m and n can be determined for fixed values of the display visual angle θ as described in “Predicting Flicker Thresholds for Video Display Terminals,” J. E. Farrell, Brian L. Benson, and Carl R. Haynie, Proc. SID, vol. 28/4, 1987, pp. 449-453. In some implementations, the regression coefficients m and n for values of θ, other than the fixed values, can be determined using interpolation. In a similar manner, the CFF(G), CFF(B), and CFF(x) for subframes associated with colors G, B, and x, can determined.
Table 1 shows example values of CFFs for various subframes determined by the flicker control module 406 using the CFF model discussed above.
Table 1 shows the values of CFFs determined for 9 subframes each for color subfields Red, Green, and Blue, and for 5 subframes for the x-channel subfield. In this example, the x-channel subfield corresponds to the color white. The 9 subframes for colors Red, Green, and Blue have weights: 80, 32, 16, 8, 4, 1, 2, 32, and 80, while the 5 subframes for the x-channel color have weights 80, 32, 16, 32, and 80. The values shown in Table 1 represent only one example for the values determined using the CFF model based on example values for display dimensions, viewing distance, color gamut, ambient light levels, frame rate, etc.
Referring back to
If the flicker control module 406 determines that the CFF of one or more subframes exceeds the illumination frequency of the subframe (for example, the green subframes in Table 1 with weights of 80 and 32 and the x-channel subframe with weights of 32), the flicker control module 406 executes one or more flicker mitigating measures (stage 514). In some implementations, the flicker control module 406 may execute one or more flicker mitigating measures only if the CFFs of a certain percentage of the total number of subframes exceed their respective illumination frequencies. For example, if CFFs of 25% or more of the total number of subframes exceed their respective illumination frequencies, then the flicker control module 406 may execute one or more flicker mitigating measures. In some implementations, instead of a percentage, the flicker control module 406 may determine if the CFFs of a certain number of subframes exceed their respective illumination frequencies. For example, if the CFFs of a threshold number (e.g., 1, 2, 4, etc.) of subframes exceed their respective illumination frequencies, then the flicker control module 406 may execute one or more flicker mitigation measures.
If the flicker control module 406 determines that the conditions for executing the flicker mitigating measures are not met, then the process 550 can continue to determine light source intensities (stage 518) and providing the output sequence (stage 520). While the flicker control logic 406 may execute various flicker mitigating measures, three such flicker mitigating measures are shown in
In some implementations, the process 550 may include reducing the brightness of the display module 304 (stage 516a). In some implementations, the flicker perceived for a subframe can depend on a difference in the brightness of the display module 304 and the ambient light levels. Specifically, the perception of flicker for a subframe may increase with an increase in the difference between the brightness of the display module and the ambient light levels, and decrease with the decrease in the difference. For example, in some implementations, Lt and Lr, in Equation (8), may represent the brightness of the display module and the ambient light levels, respectively. An increase in the difference between Lt and Lr can increase the magnitude of the DC retinal luminance Eobs, which, in turn (referring to Equation (11)), can increase the CFFs associated with the subframes. An increase in the CFFs, with the illumination frequencies remaining substantially the same, can increase the perception of flicker for some subframes. Conversely, a decrease in the difference between Lt and Lr can reduce the CFFs, resulting in a decrease in the perception of flicker.
In some implementations, the flicker perceived for a subframe can depend on a ratio of the brightness of the display module 304 and the ambient light levels. Specifically, the perception of flicker for a subframe may increase with an increase in the magnitude of the ratio of the brightness of the display module over the ambient light levels. In some implementations, the process 550, upon determining that the CFF for one or more subframes is greater than their respective illumination frequencies, may decrease the magnitude of the ratio by decreasing the brightness of the display module 304. A decrease in the ratio could, in turn, decrease the perception of flicker of the one or more subframes.
In some implementations, the process 550 may include dividing the display of a subframe (stage 516b). For example, in some implementations, display of one or more of the subframes of a particular color may be temporally divided into two or more divided-subframes. The divided-subframes can result in an increase in the effective display frequency of the subframe. This increase in the effective display frequency of the subframe increases the illumination frequency for that subframe, which, in turn, decreases the perception of flicker of that subframe.
In
Displaying divided-subframes 606a and 606b increases the frequency with which the subframe 606 is displayed. In some cases, this illumination frequency is increased beyond the CFF for the subframe 606, thereby decreasing, and in some cases eliminating, the perception of flicker of the subframe 606. In some implementations, the flicker control logic 416 may execute the divided subframes flicker mitigation measure prior to executing any other flicker mitigation measure.
In some implementations, the measures for mitigating flicker can include displaying a subframe for a reduced time period (stage 516c). In some implementations, the subframe time period can be reduced along with a proportional increase in the intensity of the light. The increase in the intensity of light is performed so that the total light output of the subframe remains unchanged despite the reduction in the subframe time period. In some implementations, this increase in the intensity of light may contribute toward decreasing the perception of flicker for that subframe.
Referring again to the process 550 in
In some implementations, due to a change in the color gamut for reducing flicker, the control logic 400 may recalculate the FICCs and FSCC subfields that were determined during preprocessing the image frame (stage 504). As a result, after selecting a different color gamut (stage 516d), the process 500 may again preprocess the image frame with the different color gamut to determine new values for the FICCs and the FSCC subfields. In some implementations, the process 550 may also re-determine the number, weights, and timings of the subframes (stage 510), calculate the CFF for each subframe (stage 512), and re-calculate the critical flicker frequency (CFF) associated with each subframe of each color (stage 514). If the change in the gamut results in the CFF of the subframe to fall below the illumination frequency of the subframe, then the process 550 can continue to determine light source intensities (stage 518) and provide the output sequence (stage 520). However, if the CFF of the subframe remains above the illumination frequency, one or more of the other flicker mitigation measures may be employed to reduce flicker.
The process 550 further includes determining light source intensities (stage 518). In some implementations, the light source intensities (or LED intensities) can be a function of the color gamut used to form the image, the color of the FSCC (if any) and any scaling factor determined by the CABC logic 412 discussed above. In some implementations, the light source intensities can also be a function of a reduction in brightness introduced as a flicker mitigating measure at stage 516a.
The process 550 includes providing the output sequence (stage 520). In some implementations, the output sequence is provided to the output logic 410, which can utilize the output sequence to generate the appropriate driver signals to display the subframes. In instances where the flicker mitigation measures are not implemented, the output sequence provided to the output logic 410 can be the initial output sequence determined during stage 511. That is, the output sequence can include, in part, the initially determined numbers, weights, and timings of subframes. In instances where the flicker mitigating measures are executed, the numbers, weights, and timings of the subframes may be modified (as described above in relation to stage 516). In such instances, the output sequence provided to the output logic 410 can include the modified numbers, weights, and timings of the subframes. The output sequence can also include the intensity levels of the light sources during each subframe.
After generating the output sequence, the output logic 410 can present the subframes in a manner discussed above in relation to stage 510.
In some implementations, the flicker control logic 406 may not execute the process stages 512, 514 and 516 shown in
If the flicker control module 406 determines that the user has increased the brightness levels of the display module 304 over a certain brightness threshold level, or by more than a threshold amount, the flicker control module 406 can, for the next received image frame, calculate the CFFs for each subframe and (stage 512) and determine whether the CFFs of any of the subframes are over the threshold (stage 514). Generally, an increase in the brightness of the display module 304, while the ambient light levels remain unchanged, may cause an increase in the CFF of one or more subframes. Thus, if the flicker control module 406 determines that CFFs of one or more subframes are over their respective illumination frequencies, the flicker control module may execute one or more flicker mitigating measures (stage 516). In some implementations, the flicker control module 406 may carry out flicker mitigating measures for only the brightest color subfields, such as the x-color subfield or the green color subfield. In some implementations, if higher brightness is desired by the user, the flicker control module 304 does not utilize reducing the display module brightness (stage 514a) as a flicker mitigating measure. Instead, the flicker control module 406 may choose to either divide the display of the flicker prone subframes or to reduce the time period of the flicker prone subframes (stage 516b) as a flicker mitigating measure.
Dividing the display of a subframe increases the number of times the subframe is loaded into the display elements, resulting in an increase in the power consumed to address and load the subframes into the display elements. The increase in the power consumed for addressing and loading the subframes can, in turn, result in an increase in the overall power consumption of the display device. In some such implementations, if the resulting power consumption increases over a threshold power value, the flicker control module 406 may choose not to divide subframe(s) (stage 516b) as a flicker mitigating measure. Instead, the flicker control module 406 may select a different color gamut that not only reduces flicker but also maintains the overall power consumption of the display device below the threshold power value.
If the flicker control module 406 determines that the user has reduced the brightness level of the display module 304 below a certain brightness threshold level, the flicker control module 406 may refrain from executing stages 512, 514, and 516, and instead, execute power saving measures. For example, in some implementations, the flicker control module 406 may increase the durations of one or more subframes and reduce the illumination intensities of the corresponding light sources to reduce power consumption in a manner such that the total light output during each of the one or more subframes remains substantially unchanged. In some other implementations, the flicker control logic 406 can increase the amount of spatial dithering. In some other implementations, the flicker control logic 406 can drop one or more subframes, and utilize the additional time made available by the dropped subframes to increase the durations of one or more remaining subframes. Increasing durations of the remaining subframes, can provide power savings by allowing reduction in illumination intensities of one or more light sources. In some other implementations, the flicker control module 406 may save power by reducing the image frame rate. In some implementations, while the power saving measures are being executed, the flicker control logic 406 may continue monitoring the CFFs of the subframes to ensure that the power saving measures employed do not inadvertently cause flicker.
In some implementations, the flicker control module 406 may base execution of stages 512, 514, and 516 on the proximity of the user from the display module 304. For example, as shown in
In some implementations, the flicker control module 406 may base execution of stages 512, 514, and 516 on the ambient light levels. For example, the flicker control logic module 406, under conditions where the CFFs have been determined to be previously below the illumination frequencies of all subframes, may execute the process stages 512, 514, and 516 if the ambient light levels decrease below a certain ambient light threshold or by more than a threshold amount. For example, the flicker control module 406 can monitor the ambient light levels received from the ambient light sensor 322 (shown in
In some implementations, the flicker control logic 406 can determine the CFFs of one or more subframes only if the ambient light levels reduce below an ambient light level threshold for a given brightness level of the display module 304. In some implementations, the ambient light level threshold can be experimentally determined. In some implementations, if the ambient light levels exceed the ambient light threshold for a given brightness level of the display module 304, the flicker control logic 406 can cease determining CFFs for one or more subframes. In some implementations, the flicker control logic 406 can execute power saving measures if the ambient light levels exceed the ambient light threshold. Generally, if the ambient light levels are substantially greater than the brightness levels of the display module 304, such as when the display device 100 is located outdoors in daylight, the perception of flicker is reduced. Thus, the flicker control logic 406 can cease determining the CFFs and execute power saving measures such as increasing the durations of one or more subframes, dropping one or more subframes, reducing the image frame rate, refraining from dividing a subframe, etc. In some implementations, the flicker control logic 406 may periodically determine whether the CFFs of any of the subframes, due to the execution of one or more power saving measures, have increased over the threshold. If the CFFs of any subframes are over their respective illumination frequencies, the flicker control logic 406 may execute flicker mitigating measures (stage 514) and/or limit the extent to which the power saving measures are executed.
The process 700 includes receiving image data associated with an image frame (stage 702). On example of this process stage has been discussed above in relation to
The process 700 further includes determining a plurality of subfields and a plurality of subframes associated with each of the plurality of subfields (stage 704). One example of this process stage has been discussed above in relation to
The process 700 further includes determining at least one critical flicker frequency associated with at least one of the plurality of subframes for each subfield (stage 706). On example of this process stage has been discussed above in relation to
The process 700 also includes comparing the at least one critical flicker frequency with an illumination frequency (stage 708). One example of this process stage has been discussed above in relation to
The process 700 further includes modifying one or more parameters of at least one of the determined plurality of subfields and the plurality of subframes based on determining that the at least one critical flicker frequency is greater than an illumination frequency (stage 710). Examples of this process stage have been discussed above in relation to
In some implementations, the control logic 400 may carry out subframe dividing (as shown in the example in
In general, the image artifacts mitigated by dividing a subframe, such as flicker and CBU, are less prevalent under higher ambient light conditions. As such, the control logic 400, in some implementations, can be configured to determine whether to display image frames using subframe dividing based ambient levels without consideration of critical flicker frequencies of any given subframe. That is, the control logic 400 can determine to use subframe dividing in response to determining that ambient light levels, for example, received from the ambient light meter 322 (shown in
In addition, the benefits of dividing a subframe are to some extent color dependent. That is, the benefits increase in proportion to the relative perceived brightness of the color to the human visual system. For example, the dividing of a white, green, or yellow subframe will have a greater artifact mitigating impact than dividing a red or blue subframe. This benefit is particularly strong for colors that may not be displayed as frequently during an image frame period. For example, as indicated in Table 1 above, in some implementations, the display output sequence includes the display of fewer, higher weighted subframes for the x-channel than for the remaining color channels, such as red, green, or blue. Moreover, the x-channel is typically selected (either as a FICC or FSCC) to be a composite color. A composite color refers to a color formed from a combination of at least two primary colors of the color gamut being used by the display. In contrast, the other color subfields tend to be component color subfields. A component color is a color which is formed primarily from a single primary color of the color gamut being displayed. In addition, the x-channel subfield tends to carry a substantially large portion of the luminance of a given image frame and is often of a color perceived by the human visual system to be relatively brighter than other colors. As such, the decision to divide an x-channel subframe has increased impact on the perception of image artifacts relative to the decision to divide other subframes.
Accordingly, the control logic 400 can be configured to sense ambient light conditions and determine whether to divide the subframes associated with the x-channel subfield based on the ambient light levels. In some such implementations, if the ambient light levels are high (or are high relative to the display brightness), the control logic 400 opts to display each subframe associated with the x-channel as a single, temporally contiguous subframe. On the other hand, if the ambient light levels are low (or are low relative to the display brightness), the control logic 400 opts to divide at least one subframe associated with the x-channel subfield, displaying that subframe, for example, twice during the image frame time period. In some implementations, the control logic 400 can display the subframe associated with the x-channel subfield more than two times. For example, the control logic 400 can display the subframe three or more times during the image frame period.
The process 800 includes receiving image data associated with an image frame (stage 802). Examples of this process stage have been discussed above in relation to
The process 800 further includes deriving a composite color subfield for the received image frame, where the derived composite color subfield includes an intensity value with respect to each of a plurality of display elements in a display for the received image frame (stage 804). One example of this process stage has been discussed above in relation to stage 504 shown in
The process 800 also includes generating a plurality of at least partially temporally weighted subframes for the derived composite color subfield, where each generated subframe has a default illumination duration, has a default illumination intensity, and indicates the states of each of the plurality of display elements in the display (stage 806). One example of this process stage has been discussed above in relation to stage 508 shown in
The process 800 further includes measuring an ambient light level (stage 808), and displaying, based on a determination that the ambient light level fails to exceed an ambient light threshold, a first of the generated subframes associated with the composite color subfield during at least two separate illumination periods (stage 810). As discussed in relation to
In some implementations, the combined durations of the two separate illumination periods can be substantially equal to the default illumination duration. For example, referring again to
If, on the other hand, the ambient light levels are above the ambient light threshold, or if the result of the subtraction is below the difference threshold or if the result of the ratio is less than the ratio threshold value, the control logic 400 refrains from displaying the composite color subframes during the at least two or more illumination periods, and causes each of the composite color subframes to be displayed as single, temporally contiguous subframes. For example, referring again to
The display device 40 includes a housing 41, a display 30, an antenna 43, a speaker 45, an input device 48 and a microphone 46. The housing 41 can be formed from any of a variety of manufacturing processes, including injection molding, and vacuum forming. In addition, the housing 41 may be made from any of a variety of materials, including, but not limited to: plastic, metal, glass, rubber and ceramic, or a combination thereof. The housing 41 can include removable portions (not shown) that may be interchanged with other removable portions of different color, or containing different logos, pictures, or symbols.
The display 30 may be any of a variety of displays, including a bi-stable or analog display, as described herein. The display 30 also can be configured to include a flat-panel display, such as plasma, electroluminescent (EL) displays, OLED, super twisted nematic (STN) display, LCD, or thin-film transistor (TFT) LCD, or a non-flat-panel display, such as a cathode ray tube (CRT) or other tube device. In addition, the display 30 can include a mechanical light modulator-based display, as described herein.
The components of the display device 40 are schematically illustrated in
The network interface 27 includes the antenna 43 and the transceiver 47 so that the display device 40 can communicate with one or more devices over a network. The network interface 27 also may have some processing capabilities to relieve, for example, data processing requirements of the processor 21. The antenna 43 can transmit and receive signals. In some implementations, the antenna 43 transmits and receives RF signals according to the IEEE 16.11 standard, including IEEE 16.11(a), (b), or (g), or the IEEE 802.11 standard, including IEEE 802.11a, b, g, n, and further implementations thereof. In some other implementations, the antenna 43 transmits and receives RF signals according to the Bluetooth® standard. In the case of a cellular telephone, the antenna 43 can be designed to receive code division multiple access (CDMA), frequency division multiple access (FDMA), time division multiple access (TDMA), Global System for Mobile communications (GSM), GSM/General Packet Radio Service (GPRS), Enhanced Data GSM Environment (EDGE), Terrestrial Trunked Radio (TETRA), Wideband-CDMA (W-CDMA), Evolution Data Optimized (EV-DO), 1×EV-DO, EV-DO Rev A, EV-DO Rev B, High Speed Packet Access (HSPA), High Speed Downlink Packet Access (HSDPA), High Speed Uplink Packet Access (HSUPA), Evolved High Speed Packet Access (HSPA+), Long Term Evolution (LTE), AMPS, or other known signals that are used to communicate within a wireless network, such as a system utilizing 3G, 4G or 5G technology. The transceiver 47 can pre-process the signals received from the antenna 43 so that they may be received by and further manipulated by the processor 21. The transceiver 47 also can process signals received from the processor 21 so that they may be transmitted from the display device 40 via the antenna 43.
In some implementations, the transceiver 47 can be replaced by a receiver. In addition, in some implementations, the network interface 27 can be replaced by an image source, which can store or generate image data to be sent to the processor 21. The processor 21 can control the overall operation of the display device 40. The processor 21 receives data, such as compressed image data from the network interface 27 or an image source, and processes the data into raw image data or into a format that can be readily processed into raw image data. The processor 21 can send the processed data to the driver controller 29 or to the frame buffer 28 for storage. Raw data typically refers to the information that identifies the image characteristics at each location within an image. For example, such image characteristics can include color, saturation and gray-scale level.
The processor 21 can include a microcontroller, CPU, or logic unit to control operation of the display device 40. The conditioning hardware 52 may include amplifiers and filters for transmitting signals to the speaker 45, and for receiving signals from the microphone 46. The conditioning hardware 52 may be discrete components within the display device 40, or may be incorporated within the processor 21 or other components.
The driver controller 29 can take the raw image data generated by the processor 21 either directly from the processor 21 or from the frame buffer 28 and can re-format the raw image data appropriately for high speed transmission to the array driver 22. In some implementations, the driver controller 29 can re-format the raw image data into a data flow having a raster-like format, such that it has a time order suitable for scanning across the display array 30. Then the driver controller 29 sends the formatted information to the array driver 22. Although a driver controller 29, such as an LCD controller, is often associated with the system processor 21 as a stand-alone Integrated Circuit (IC), such controllers may be implemented in many ways. For example, controllers may be embedded in the processor 21 as hardware, embedded in the processor 21 as software, or fully integrated in hardware with the array driver 22.
The array driver 22 can receive the formatted information from the driver controller 29 and can re-format the video data into a parallel set of waveforms that are applied many times per second to the hundreds, and sometimes thousands (or more), of leads coming from the display's x-y matrix of display elements. In some implementations, the array driver 22 and the display array 30 are a part of a display module. In some implementations, the driver controller 29, the array driver 22, and the display array 30 are a part of the display module.
In some implementations, the driver controller 29, the array driver 22, and the display array 30 are appropriate for any of the types of displays described herein. For example, the driver controller 29 can be a conventional display controller or a bi-stable display controller (such as a mechanical light modulator display element controller). Additionally, the array driver 22 can be a conventional driver or a bi-stable display driver (such as a mechanical light modulator display element controller). Moreover, the display array 30 can be a conventional display array or a bi-stable display array (such as a display including an array of mechanical light modulator display elements). In some implementations, the driver controller 29 can be integrated with the array driver 22. Such an implementation can be useful in highly integrated systems, for example, mobile phones, portable-electronic devices, watches or small-area displays.
In some implementations, the input device 48 can be configured to allow, for example, a user to control the operation of the display device 40. The input device 48 can include a keypad, such as a QWERTY keyboard or a telephone keypad, a button, a switch, a rocker, a touch-sensitive screen, a touch-sensitive screen integrated with the display array 30, or a pressure- or heat-sensitive membrane. The microphone 46 can be configured as an input device for the display device 40. In some implementations, voice commands through the microphone 46 can be used for controlling operations of the display device 40.
The power supply 50 can include a variety of energy storage devices. For example, the power supply 50 can be a rechargeable battery, such as a nickel-cadmium battery or a lithium-ion battery. In implementations using a rechargeable battery, the rechargeable battery may be chargeable using power coming from, for example, a wall socket or a photovoltaic device or array. Alternatively, the rechargeable battery can be wirelessly chargeable. The power supply 50 also can be a renewable energy source, a capacitor, or a solar cell, including a plastic solar cell or solar-cell paint. The power supply 50 also can be configured to receive power from a wall outlet.
In some implementations, control programmability resides in the driver controller 29 which can be located in several places in the electronic display system. In some other implementations, control programmability resides in the array driver 22. The above-described optimization may be implemented in any number of hardware and/or software components and in various configurations.
As used herein, a phrase referring to “at least one of” a list of items refers to any combination of those items, including single members. As an example, “at least one of: a, b, or c” is intended to cover: a, b, c, a-b, a-c, b-c, and a-b-c.
The various illustrative logics, logical blocks, modules, circuits and algorithm processes described in connection with the implementations disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. The interchangeability of hardware and software has been described generally, in terms of functionality, and illustrated in the various illustrative components, blocks, modules, circuits and processes described above. Whether such functionality is implemented in hardware or software depends upon the particular application and design constraints imposed on the overall system.
The hardware and data processing apparatus used to implement the various illustrative logics, logical blocks, modules and circuits described in connection with the aspects disclosed herein may be implemented or performed with a general purpose single- or multi-chip processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, or, any conventional processor, controller, microcontroller, or state machine. A processor also may be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. In some implementations, particular processes and methods may be performed by circuitry that is specific to a given function.
In one or more aspects, the functions described may be implemented in hardware, digital electronic circuitry, computer software, firmware, including the structures disclosed in this specification and their structural equivalents thereof, or in any combination thereof. Implementations of the subject matter described in this specification also can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a computer storage media for execution by, or to control the operation of, data processing apparatus.
If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. The processes of a method or algorithm disclosed herein may be implemented in a processor-executable software module which may reside on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that can be enabled to transfer a computer program from one place to another. A storage media may be any available media that may be accessed by a computer. By way of example, and not limitation, such computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that may be used to store desired program code in the form of instructions or data structures and that may be accessed by a computer. Also, any connection can be properly termed a computer-readable medium. Disk and disc, as used herein, includes compact disc (CD), laser disc, optical disc, digital versatile disc (DVD), floppy disk, and blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media. Additionally, the operations of a method or algorithm may reside as one or any combination or set of codes and instructions on a machine readable medium and computer-readable medium, which may be incorporated into a computer program product.
Various modifications to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other implementations without departing from the spirit or scope of this disclosure. Thus, the claims are not intended to be limited to the implementations shown herein, but are to be accorded the widest scope consistent with this disclosure, the principles and the novel features disclosed herein.
Additionally, a person having ordinary skill in the art will readily appreciate, the terms “upper” and “lower” are sometimes used for ease of describing the figures, and indicate relative positions corresponding to the orientation of the figure on a properly oriented page, and may not reflect the proper orientation of any device as implemented.
Certain features that are described in this specification in the context of separate implementations also can be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation also can be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Further, the drawings may schematically depict one more example processes in the form of a flow diagram. However, other operations that are not depicted can be incorporated in the example processes that are schematically illustrated. For example, one or more additional operations can be performed before, after, simultaneously, or between any of the illustrated operations. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products. Additionally, other implementations are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results.
