Patent Application
20240324338
This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application Nos. 10-2023-0039176 and 10-2023-0089047 filed on Mar. 24, 2023 and Jul. 10, 2023, respectively, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entirety.
One or more embodiments relate to a display apparatus, and more particularly, to a display apparatus capable of displaying a high-quality image.
In general, in a display apparatus such as an organic light-emitting display apparatus, thin-film transistors are located in each (sub-)pixel to control the luminance of each (sub-)pixel. These thin-film transistors control the luminance of a corresponding (sub-)pixel according to a predefined source, such as a transmitted data signal.
Conventional display apparatuses have problems in that they may not display high-quality images in some portions in a display area.
One or more embodiments provide a display apparatus capable of displaying a high-quality image. However, the embodiments are examples, and do not limit the scope of the disclosure.
Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments.
According to one aspect of the disclosure, a display apparatus includes a substrate including a component area and a display area around the component area, a driving voltage line extending in a first direction across the display area, a first horizontal connection line extending in a second direction intersecting the first direction and toward the component area, a first auxiliary horizontal connection line spaced apart from the first horizontal connection line, located between the first horizontal connection line and the component area, and extending in the second direction, and a transfer line extending in the second direction toward the component area, and including a plurality of protrusions protruding in the first direction, wherein at least one of the plurality of protrusions is electrically connected to the first auxiliary horizontal connection line.
One of the plurality of protrusions may be electrically connected to the first auxiliary horizontal connection line.
The at least one protrusion may be located farther from the component area than an end of the transfer line.
The transfer line and the first auxiliary horizontal connection line may be disposed on a same layer.
The transfer line and the first auxiliary horizontal connection line may be integrally formed as a single body.
The driving voltage line may be disposed on the transfer line.
The driving voltage line may be electrically connected to one of the plurality of protrusions of the transfer line through a contact hole.
The display apparatus may further include a plurality of pixel circuits located in the display area in rows extending in the second direction, wherein, when n is a natural number of 2 or more, the first auxiliary horizontal connection line located in an nth row is electrically connected to the transfer line located in an n−1th row.
The display apparatus may further include a vertical connection line extending across the display area in the first direction and electrically connected to the first horizontal connection line.
The vertical connection line and the driving voltage line may be disposed on a same layer.
The display apparatus may further include a second horizontal connection line extending across the display area in the second direction, wherein the substrate further includes a peripheral area outside the display area, wherein a first end of the second horizontal connection line is located in the peripheral area on one side of the display area, and a second end of the second horizontal connection line is located in the peripheral area on the other side of the display area.
At least one of the first end and the second end of the second horizontal connection line may be electrically connected to a constant voltage line in the peripheral area.
Both ends of the first horizontal connection line may be located in the display area.
The one end of the first horizontal connection line that is farther from the component area than the other end may be located in the display area.
The display apparatus may further include a first additional horizontal connection line spaced apart from the first horizontal connection line, located between the first horizontal connection line and the peripheral area, and extending in the second direction.
An end of the first additional horizontal connection line away from the component area may be located in the peripheral area on a side of the display area.
The end of the first additional horizontal connection line may be electrically connected to a constant voltage line in the peripheral area.
According an aspect of the disclosure, a display apparatus includes a substrate, a driving voltage line extending across the display area in the first direction, a first component area and a second component area spaced apart from each other in a second direction intersecting a first direction, a display area around the first component area and the second component area, a horizontal connection line extending across the display area in the second direction and located between the first component area and the second component area, and a transfer line extending in the second direction to cross the display area and be located between the first component area and the second component area, corresponding to the horizontal connection line, and including a plurality of protrusions protruding in the first direction, wherein at least one of the plurality of protrusions is electrically connected to the horizontal connection line.
One of the plurality of protrusions may be electrically connected to the horizontal connection line.
The transfer line and the horizontal connection line may be disposed on a same layer.
The transfer line and the first auxiliary horizontal connection line may be integrally formed as a single body.
The driving voltage line may be disposed over the transfer line.
The driving voltage line may be electrically connected to one of the plurality of protrusions of the transfer line through a contact hole.
The display apparatus may further include a plurality of pixel circuits located in the display area in rows extending in the second direction, wherein, when n is a natural number of 2 or more, the horizontal connection line located in an nth row is electrically connected to the transfer line located in an n−1th row.
Other aspects, features, and advantages of the disclosure will become more apparent from the detailed description, the claims, and the drawings.
The above and other aspects, features, and advantages of certain embodiments will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:
Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the figures, to explain aspects of the present description. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Throughout the disclosure, the expression “at least one of a, b or c” indicates only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.
As the disclosure allows for various changes and numerous embodiments, certain embodiments will be illustrated in the drawings and described in the detailed description. Effects and features of the disclosure, and methods for achieving them will be clarified with reference to embodiments described below in detail with reference to the drawings. However, the disclosure is not limited to the following embodiments and may be embodied in various forms.
Hereinafter, embodiments will be described in detail with reference to the accompanying drawings, wherein the same or corresponding elements are denoted by the same reference numerals throughout and a redundant description is omitted.
It will be understood that when a component, such as a layer, a film, a region, or a plate, is referred to as being “on” another component, the component may be directly on the other component or intervening components may be present therebetween. Also, sizes of components in the drawings may be exaggerated or reduced for convenience of explanation. For example, because sizes, shapes, and thicknesses of elements in the drawings are arbitrarily selected for convenience of explanation, the disclosure is not limited thereto.
In the following embodiments, the x-axis, the y-axis and the z-axis are not limited to three axes of the rectangular coordinate system, and may be interpreted in a broader sense. For example, the x-axis, the y-axis, and the z-axis may be perpendicular to one another, or may represent different directions that are not perpendicular to one another. A positive direction along each of the axes (x-direction, y-direction) indicates the direction as shown by the arrow in the coordinate system. A negative direction along each of the axes (−x-direction, −y-direction) indicates a direction that is opposite the direction of the arrows in the coordinate system.
Although the terms “first,” “second,” etc. may be used to describe various elements, these elements should not be limited to any order by these terms. These terms are only used to distinguish one element from another.
It will be further understood that the terms “comprises” or “comprising” used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.
“A and/or B” is used herein to select only A, select only B, or select both A and B. “At least one of A and B” is used to select only A, select only B, or select both A and B.
It will be understood that when a layer, region, or component is referred to as being “connected,” the layer, the region, or the component may be directly connected or may be indirectly connected with intervening layers, regions, or components therebetween. For example, when layers, regions, or components are referred to as being “electrically connected,” the layers, the regions, or the components may be directly electrically connected, or may be indirectly electrically connected with intervening layers, regions, or components therebetween.
The display apparatus 1 may include a display area DA and a peripheral area PA outside the display area DA. In a plan view, the display area DA may have a substantially rectangular shape as shown in
Pixels including various display elements such as an organic light-emitting diode (OLED) may be located in the display area DA. The pixels may be arranged in any of various forms such as a stripe arrangement, a pentile arrangement, or a mosaic arrangement in an x-axis direction and a y-axis direction, to display an image.
A component area CA may be located in an area that is at least partially surrounded by the display area DA. The component area CA is not part of the display area DA and the two areas are mutually exclusive. The component area CA may be defined by an opening of a substrate 100 (see
An intermediate area MA may be located between the display area DA and the component area CA. The intermediate area MA may have a closed-loop shape entirely surrounding the component area CA in plan view.
The display panel 10 may include an image generating layer 20, an input sensing layer 40, and an optical functional layer 50.
The image generating layer 20 may include display elements (or light-emitting elements) that emit light to display an image. The display element may include a light-emitting diode, for example, an organic light-emitting diode including an organic emission layer. In another embodiment, the display element may be an inorganic light-emitting diode including an inorganic material. The inorganic light-emitting diode may include a PN diode including inorganic semiconductor-based materials. When a voltage is applied to a PN junction diode in a forward direction, holes and electrons may be injected, and energy generated by recombination of the holes and electrons may be converted into light energy to emit light of a certain color. The inorganic light-emitting diode may have a width of several to hundreds of micrometers, or several to hundreds of nanometers.
However, the disclosure is not limited thereto. For example, the image generating layer 20 may include a quantum dot layer. That is, light having a wavelength belonging to a specific wavelength band generated in an emission layer included in the image generating layer 20 may be converted into light having a preset wavelength by the quantum dot layer.
The input sensing layer 40 may obtain coordinate information according to an external input, for example, a touch event. The input sensing layer 40 may include a sensing electrode (or a touch electrode) and trace lines connected to the sensing electrode. The input sensing layer 40 may detect an external input by using a mutual capacitance method and/or a self-capacitance method.
The input sensing layer 40 may be located on the image generating layer 20. The input sensing layer 40 may be formed directly on the image generating layer 20, or may be separately formed and then may be attached to the image generating layer 20 through an adhesive layer such as an optically clear adhesive. In the former case, the input sensing layer 40 may be continuously formed after the image generating layer 20 is formed, and in this case, the adhesive layer may not be located between the input sensing layer 40 and the image generating layer 20. For reference, although the input sensing layer 40 is located between the image generating layer 20 and the optical functional layer 50 in
The optical functional layer 50 may include an anti-reflection layer. The anti-reflection layer may reduce a reflectance of light (external light) incident on the display panel 10 through the cover window 60. The anti-reflection layer may include a phase retarding film and a polarizing film. Alternatively, the anti-reflection layer may include a black matrix and color filters. In the latter case, the color filters may be arranged in consideration of a color of light emitted from the image generating layer 20.
The display panel 10 may include an opening 10OP to increase a transmittance of the component area CA. Because the display panel 10 includes the opening 10OP, the substrate 100, which is an element of the image generating layer 20 included in the display panel 10, may also have such an opening as described above. The opening 10OP may include a first opening 20OP passing through the image generating layer 20, a second opening 40OP passing through the input sensing layer 40, and a third opening 50OP passing through the optical functional layer 50. That is, the first opening 20OP passing through the image generating layer 20, the second opening 40OP passing through the input sensing layer 40, and the third opening 50OP passing through the optical functional layer 50 may overlap each other, to form the opening 10OP of the display panel 10.
The cover window 60 may be located on the display panel 10, specifically, on the optical functional layer 50. The cover window 60 may be attached to the optical functional layer 50 through an adhesive layer such as an optically clear adhesive (OCA). The cover window 60 may cover the first opening 20OP passing through the image generating layer 20, the second opening 40OP passing through the input sensing layer 40, and the third opening 50OP passing through the optical functional layer 50. The cover window 60 may include glass or plastic. When the cover window 60 includes glass, the cover window 60 may include ultra-thin glass. When the cover window 60 includes plastic, the cover window 60 may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.
The component area CA may be a component area (e.g., a sensor area, a camera area, a speaker area, etc.) in which the component 70 for adding various functions to the display apparatus 1 is located.
The component 70 that is an electronic element may be located to correspond to the component area CA (in a −z direction). The component 70 may be a camera or a sensor that is an electronic element using light or sound. Examples of the sensor may include a proximity sensor for measuring a distance and an illuminance sensor for measuring brightness. The electronic element using light may use light of any of various wavelength bands such as visible light, infrared light, or ultraviolet light. The component area CA may allow light and/or sound to be output from the component 70 to the outside or may allow external light and/or sound to extend toward the component 70.
A plurality of pixels P are located in the display area DA. Each of the pixels P may include a display element ED such as an organic light-emitting diode OLED. Each of the pixels P includes a pixel circuit PC that controls the display element ED. The pixel circuit PC may overlap the display element ED. Each pixel P may emit, for example, red light, green light, blue light, or white light. The display area DA may be covered by a sealing member to be protected from external air or moisture.
When necessary, the intermediate area MA surrounding the component area CA may be located between the display area DA and the component area CA. In some embodiments, pixels P may be located even in the intermediate area MA. In this case, the number of pixels P per unit area in the intermediate area MA may be less than the number of pixels P per unit area in the display area DA.
The pixel circuits PC included in the pixels P in the display area DA may be respectively electrically connected to outer circuits located in the peripheral area PA. In the peripheral area PA, a first scan driving circuit SDR1, a second scan driving circuit SDR2, a terminal unit PAD, a driving voltage supply line 11, and a common voltage supply line 13 may be located.
The first scan driving circuit SDR1 may be located next to a side of the display area DA (in a −x direction). The second scan driving circuit SDR2 may be symmetrical to the first scan driving circuit SDR1 with respect to the display area DA, in position and shape. The first scan driving circuit SDR1 may be connected to some of the pixel circuits PC through a scan line SL to apply a scan signal. The second scan driving circuit SDR2 may be connected to others of the pixel circuits PC through a scan line (not shown) to apply a scan signal. The first scan driving circuit SDR1 may be connected to some of the pixel circuits PC through an emission control line EL to apply an emission control signal. The second scan driving circuit SDR2 may be connected to others of the pixel circuits PC through an emission control line (not shown) to apply an emission control signal.
The terminal unit PAD may be located on the substrate 100. The pad unit PAD is not covered by an insulating layer, and is connected to a display circuit board 30. A display driver 32 may be located on the display circuit board 30.
The display driver 32 may generate a control signal transmitted to the first scan driving circuit SDR1 and the second scan driving circuit SDR2. Also, the display driver 32 may generate a data signal, and the generated data signal may be transmitted to the pixel circuit PC through a fan-out wiring FW and a data line DL connected to the fan-out wiring FW.
The display driver 32 may supply a driving voltage ELVDD to the driving voltage supply line 11, and may supply a common voltage ELVSS to the common voltage supply line 13. The driving voltage ELVDD may be applied to the pixel circuit PC through a driving voltage line PL that is connected to the driving voltage supply line 11 and extends substantially in a first direction (y-axis direction) to cross the display area DA. The common voltage ELVSS may be applied to a counter electrode of the display element ED electrically connected to the common voltage supply line 13.
The driving voltage supply line 11 may be located below the display area DA, and may extend in a second direction (x-axis direction) intersecting the first direction (the y-axis direction). A plurality of driving voltage lines PL crossing the display area DA may be located over the display area DA and may be electrically connected to an additional driving voltage supply line (not shown) extending in the second direction (the x-axis direction). The common voltage supply line 13 may loop around three sides of the display area DA and leave the fourth side open.
A 1-1th data line D1-1 located in the display area DA to be in −y direction from the component area CA extends in the first direction (the y-axis direction) toward the component area CA. The 1-1th data line D1-1 may be electrically connected to a column of pixel circuits arranged in the first direction (the y-axis direction) to be located where the 1-1th data line D1-1 passes, to transmit a data signal to the pixel circuits.
Likewise, a 2-1th data line D2-1 located in the display area DA to be in −y direction from the component area CA extends in the first direction (the y-axis direction) toward the component area CA. The 2-1th data line D2-1 may be electrically connected to a column of pixel circuits arranged in the first direction (the y direction) to be located where the 2-1th data line D2-1 passes, to transmit a data signal to the pixel circuits. This is the same for a 3-1th data line D3-1.
A 1-2th data line D1-2 located in the display area DA to be in +y direction from the component area CA extends in the first direction (the y-axis direction) toward the component area CA. The 1-2 data line D1-2 may be electrically connected to a column of pixel circuits arranged in the first direction (the y-axis direction) to be located where the 1-2th data line D1-2 passes, to transmit a data signal to the pixel circuits. The pixel circuits electrically connected to the 1-2th data line D1-2 and the pixel circuits electrically connected to the 1-1th data line D1-1 may be located in the same column. That is, an extension axis of the 1-2th data line D1-2 in the first direction (the y-axis direction) may match an extension axis of the 1-1th data line D1-1 in the first direction (the y-axis direction).
Likewise, a 2-2th data line D2-2 located in the display area DA to be in +y direction from the component area CA extends in the first direction (the y-axis direction) toward the component area CA. The 2-2th data line D2-2 may be electrically connected to a column of pixel circuits arranged in the first direction (the y-axis direction) to be located where the 2-2th data line D2-2 passes, to transmit a data signal to the pixel circuits. The pixel circuits electrically connected to the 2-2th data line D2-2 and the pixel circuits electrically connected to the 2-1th data line D2-1 may be located in the same column. That is, an extension axis of the 2-2th data line D2-2 in the first direction (the y-axis direction) may match an extension axis of the 2-1th data line D2-1 in the first direction (the y-axis direction). This is the same for a 3-2th data line D3-2 and a 3-1th data line D3-1.
The 1-1th data line D1-1 and the 1-2th data line D1-2 may be electrically connected to each other. In detail, the 1-1th data line D1-1 and the 1-2th data line D1-2 may be electrically connected to each other through a 1-1th horizontal connection line HCL1-1, a first vertical connection line VCL1, and a 1-2th horizontal connection line HCL1-2.
The 1-1th horizontal connection line HCL1-1 is located in the display area DA to be located in the −y direction with respect to the center of the component area CA, and extends in the second direction (the x-axis direction) to cross the display area DA and extend toward the component area CA. A portion of the 1-1th horizontal connection line HCL1-1 close to the component area CA may be electrically connected to the 1-1th data line D1-1 in a portion A in
As such, the display apparatus according to the present embodiment may transmit a data signal to pixels belonging to the same column extending in the first direction (the y-axis direction) and electrically connected to the 1-1th data line D1-1 and the 1-2th data line D1-2, through the 1-1th data line D1-1 and the 1-2th data line D1-2 that are electrically connected to each other.
The 2-1th data line D2-1 and the 2-2th data line D2-2 may also be electrically connected to each other. In detail, the 2-1th data line D2-1 and the 2-2th data line D2-2 may be electrically connected to each other through a 2-1th horizontal connection line HCL2-1, a second vertical connection line VCL2, and a 2-2th horizontal connection line HCL2-2.
The 2-1th horizontal connection line HCL2-1 is located in the display area DA to be located in the −y direction with respect to the center of the component area CA, and extends in the second direction (the x-axis direction) intersecting the first direction. A portion of the 2-1th horizontal connection line HCL2-1 close to the component area CA may be electrically connected to the 2-1th data line D2-1. The second vertical connection line VCL2 may be electrically connected to a portion of the 2-1th horizontal connection line HCL2-1 away from the component area CA, and may extend in the first direction (the y-axis direction). The 2-2th horizontal connection line HCL2-2 is located in the display area DA to be located in the +y direction with respect to the center of the component area CA, and extends in the second direction (the x-axis direction) intersecting the first direction. A portion of the 2-2th horizontal connection line HCL2-2 away from the component area CA may be electrically connected to the second vertical connection line VCL2. A portion of the 2-2th horizontal connection line HCL2-2 close to the component area CA may be electrically connected to the 2-2th data line D2-2.
As such, the display apparatus according to the present embodiment may transmit a data signal to pixels belonging to the same column extending in the first direction (the y-axis direction) and electrically connected to the 2-1th data line D2-1 and the 2-2th data line D2-2, through the 2-1th data line D2-1 and the 2-2th data line D2-2 that are electrically connected to each other.
In the same manner, the 3-1th data line D3-1 and the 3-2th data line D3-2 may be electrically connected to each other. In detail, the 3-1th data line D3-1 and the 3-2th data line D3-2 may be electrically connected to each other through a 3-1th horizontal connection line HCL3-1, a third vertical connection line VCL3, and a 3-2th horizontal connection line HCL3-2.
For reference, the 1-1th data line D1-1, the 2-1th data line D2-1, and the 3-1th data line D3-1 may be sequentially arranged from the center of the component area CA in the −x direction. Accordingly, the third vertical connection line VCL3, the second vertical connection line VCL2, and the first vertical connection line VCL1 may be sequentially arranged to be farther from the center of the component area CA in the −x direction as shown in
As shown in
A 1-1th auxiliary horizontal connection line HCL1-1a extending in the second direction (the x-axis direction) may be located between the 1-1th horizontal connection line HCL1-1 and the component area CA. The 1-1th auxiliary horizontal connection line HCL1-1a may be spaced apart from the 1-1th horizontal connection line HCL1-1. In addition, a 1-1th additional horizontal connection line HCL1-1b extending in the second direction (the x-axis direction) may be located between the 1-1th horizontal connection line HCL1-1 and the peripheral area PA. The 1-1th additional horizontal connection line HCL1-1b may also be spaced apart from the 1-1th horizontal connection line HCL1-1. The 1-1th auxiliary horizontal connection line HCL1-1a and the 1-1th additional horizontal connection line HCL1-1b may be located in the same row as the 1-1th horizontal connection line HCL1-1.
As described above, the 1-1th horizontal connection line HCL1-1 extending in the second direction (the x-axis direction) electrically connects the 1-1th data line D1-1 to the 1-2th data line D1-2. However, it is preferable that most pixels located in a row through which the 1-1th horizontal connection line HCL1-1 passes have the same or similar structure in order to implement a display apparatus for displaying a high-quality image. Accordingly, unlike the 1-1th horizontal connection line HCL1-1 electrically connected to the 1-1th data line D1-1, the 1-1th auxiliary horizontal connection line HCL1-1a and the 1-1th additional horizontal connection line HCL1-1b, which are not connected to a data line, may be spaced apart from the 1-1th horizontal connection line HCL1-1 and located in the same row as the 1-1th horizontal connection line HCL1-1. Accordingly, because most of pixels located in a row through which the 1-1th horizontal connection line HCL1-1 passes have the same or similar structure, a display apparatus for displaying a high-quality image may be implemented.
This is the same for other horizontal connection lines. For example, a 2-1th auxiliary horizontal connection line HCL2-1a that is spaced apart from the 2-1th horizontal connection line HCL2-1 and extending in the second direction (the x-axis direction) may be located between the 2-1th horizontal connection line HCL2-1 and the component area CA. In addition, a 2-1th additional horizontal connection line HCL2-1b that is spaced apart from the 2-1th horizontal connection line HCL2-1 and extending in the second direction (the x-axis direction) may be located between the 2-1th horizontal connection line HCL2-1 and the peripheral area PA. The 2-1th auxiliary horizontal connection line HCL2-1a and the 2-1th additional horizontal connection line HCL2-1b may be located in the same row as the 2-1th horizontal connection line HCL2-1.
As such, to have a relationship similar to that between the 1-1th horizontal connection line HCL1-1, the 1-1th auxiliary horizontal connection line HCL1-1a, and the 1-1th additional horizontal connection line HCL1-1b, the 3-1th horizontal connection line HCL3-1, a 3-1th auxiliary horizontal connection line HCL3-1a, and a 3-1th additional horizontal connection line HCL3-1b may exist, the 3-2th horizontal connection line HCL3-2, a 3-2th auxiliary horizontal connection line HCL3-2a, and a 3-2th additional horizontal connection line HCL3-2b may exist, the 2-2th horizontal connection line HCL2-2, a 2-2th auxiliary horizontal connection line HCL2-2a, and a 2-2th additional horizontal connection line HCL2-2b may exist, and the 1-2th horizontal connection line HCL1-2, a 1-2th auxiliary horizontal connection line HCL1-2a, and a 1-2th additional horizontal connection line HCL1-2b may exist, as shown in
This may be the same for vertical connection lines. Although not shown in
The pixel circuit PC may include a plurality of thin-film transistors (e.g., T1 through T7) and a storage capacitor Cst as shown in
The plurality of thin-film transistors (e.g., T1 through T7) may include a driving transistor T1, a switching transistor T2, a compensation transistor T3, a first initialization transistor T4, an operation control transistor T5, an emission control transistor T6, and a second initialization transistor T7.
The organic light-emitting diode OLED may include a pixel electrode and a counter electrode. The pixel electrode of the organic light-emitting diode OLED may be connected to the driving transistor T1 via the emission control transistor T6 to receive driving current, and the counter electrode may receive a second power supply voltage ELVSS. The organic light-emitting diode OLED may generate light having a luminance corresponding to the driving current.
Some of the plurality of thin-film transistors (e.g., T1 through T7) may be n-channel MOSFETs (NMOSs) and the rest may be p-channel MOSFETs (PMOSs). For example, the compensation transistor T3 and the first initialization transistor T4 from among the plurality of thin-film transistors (e.g., T1 through T7) may be NMOSs and the rest may be PMOSs. Alternatively, the compensation transistor T3, the first initialization transistor T4, and the second initialization transistor T7 from among the plurality of thin-film transistors (e.g., T1 through T7) may be NMOSs and the rest may be PMOSs. Alternatively, all of the plurality of thin-film transistors (e.g., T1 through T7) may be NMOSs or PMOSs. The plurality of thin-film transistors (e.g., T1 through T7) may include amorphous silicon or polysilicon. When necessary, a thin-film transistor that is an NMOS may include an oxide semiconductor. For convenience, the following will be described assuming that the compensation transistor T3 and the first initialization transistor T4 are NMOSs including an oxide semiconductor and the rest are PMOSs.
The signal lines may include a first scanline SL1 configured to transmit a first scan signal Sn, a second scan line SL2 configured to transmit a second scan signal Sn′, a previous scan line SLp configured to transmit a previous scan signal Sn-1 to the first initialization transistor T4, a next scan line SLn configured to transmit a next scan signal Sn+1 to the second initialization transistor T7, the emission control line EL configured to transmit an emission control signal En to the operation control transistor T5 and the emission control transistor T6, and the data line DL crossing the first scan line SL1 and configured to transmit a data signal Dm. The data line DL may be any one of the 1-1th data line D1-1, the 1-2th data line D1-2, the 2-1th data line D2-1, the 2-2th data line D2-2, the 3-1th data line D3-1, the 3-2th data line D3-2, the fourth data line D4, the fifth data line D5, and the sixth data line D6 described with reference to
The driving voltage line PL may transmit the driving voltage ELVDD to the driving transistor T1, the first initialization voltage line VL1 may transmit a first initialization voltage Vint1 for initializing the driving transistor T1, and the second initialization voltage line VL2 may transmit a second initialization voltage Vint2 for initializing a first electrode of the organic light-emitting diode OLED.
A driving gate electrode of the driving transistor T1 may be connected to the storage capacitor Cst through a second node N2, any one of a source region and a drain region of the driving transistor T1 may be connected to the driving voltage line PL via the operation control transistor T5 through a first node N1, and the other of the source region and the drain region of the driving transistor T1 may be electrically connected to the first electrode (pixel electrode) of the organic light-emitting diode OLED via the emission control transistor T6 through a third node N3. The driving transistor T1 may receive the data signal Dm according to a switching operation of the switching transistor T2 and may supply driving current to the organic light-emitting diode OLED. That is, the driving transistor T1 may control the amount of current flowing from the first node N1 electrically connected to the driving voltage line PL to the organic light-emitting diode OLED, in response to a voltage applied to the second node N2 which varies according to the data signal Dm.
A switching gate electrode of the switching transistor T2 may be connected to the first scan line SL1 that transmits the first scan signal Sn, any one of a source region and a drain region of the switching transistor T2 may be connected to the data line DL, and the other of the source region and the drain region of the switching transistor T2 may be connected to the driving transistor T1 through the first node N1 and may be connected to the driving voltage line PL via the operation control transistor T5. The switching transistor T2 may transmit the data signal Dm from the data line DL to the first node N1, in response to a voltage applied to the first scan line SL1. The switching transistor T2 may be turned on according to the first scan signal Sn received through the first scan line SL1, and may perform a switching operation of transmitting the data signal Dm transmitted through the data line DL to the driving transistor T1 through the first node N1.
A compensation gate electrode of the compensation transistor T3 may be connected to the second scan line SL2. Any one of a source region and a drain region of the compensation transistor T3 may be connected to the first electrode of the organic light-emitting diode OLED via the emission control transistor T6 through the third node N3. The other of the source region and the drain region of the compensation transistor T3 may be connected to a first capacitor electrode CE1 of the storage capacitor Cst and the driving gate electrode of the driving transistor T1 through the second node N2. The compensation transistor T3 may be turned on according to the second scan signal Sn′ received through the second scan line SL2 and may diode-connect the driving transistor T1.
A first initialization gate electrode of the first initialization transistor T4 may be connected to the previous scan line SLp. Any one of a source region and a drain region of the first initialization transistor T4 may be connected to the first initialization voltage line VL1. The other of the source region and the drain region of the first initialization transistor T4 may be connected to a first capacitor electrode CE1 of the storage capacitor Cst and the driving gate electrode of the driving transistor T1 through the second node N2. The first initialization transistor T4 may apply the first initialization voltage Vint1 from the first initialization voltage line VL1 to the second node N2, in response to a voltage applied to the previous scan line SLp. That is, the first initialization transistor T4 may be turned on according to the previous scan signal Sn−1 received through the previous scan line SLp and may perform an initialization operation of initializing a voltage of the driving gate electrode of the driving transistor T1 by transmitting the first initialization voltage Vint1 to the driving gate electrode of the driving transistor T1.
An operation control gate electrode of the operation control transistor T5 may be connected to the emission control line EL, any one of a source region and a drain region of the operation control transistor T5 may be connected to the driving voltage line PL, and the other of the source region and the drain region of the operation control transistor T5 may be connected to the driving transistor T1 and the switching transistor T2 through the first node N1.
An emission control gate electrode of the emission control transistor T6 may be connected to the emission control line EL, any one of a source region and a drain region of the emission control transistor T6 may be connected to the driving transistor T1 and the compensation transistor T3 through the third node N3, and the other of the source region and the drain region of the emission control transistor T6 may be electrically connected to the first electrode (pixel electrode) of the organic light-emitting diode OLED.
The operation control transistor T5 and the emission control transistor T6 may be simultaneously turned on according to the emission control signal En received through the emission control line EL, so that the driving voltage ELVDD is transmitted to the organic light-emitting diode OLED and the driving current flows through the organic light-emitting diode OLED.
A second initialization gate electrode of the second initialization transistor T7 may be connected to the next scan line SLn, any one of a source region and a drain region of the second initialization transistor T7 may be connected to the first electrode (pixel electrode) of the organic light-emitting diode OLED, and the other of the source region and the drain region of the second initialization transistor T7 may be connected to the second initialization voltage line VL2 and may receive the second initialization voltage Vint2. The second initialization transistor T7 is turned on according to the next scan signal Sn+1 received through the next scan line SLn, and initializes the first electrode (pixel electrode) of the organic light-emitting diode OLED. The next scan line SLn may be the same as the first scan line SL1. In this case, the scan line may function as the first scan line SL1 or may function as the next scan line SLn, by transmitting the same electrical signal with a time difference. That is, the next scan line SLn may be a first scan line of a pixel that is adjacent to the pixel P of
The second initialization transistor T7 may be connected to the first scan line SL1 as shown in
The storage capacitor Cst may include the first capacitor electrode CE1 and a second capacitor electrode CE2. The first capacitor electrode CE1 of the storage capacitor Cst is connected to the driving gate electrode of the driving transistor T1 through the second node N2, and the second capacitor electrode CE2 of the storage capacitor Cst is connected to the driving voltage line PL. The storage capacitor Cst may store a charge corresponding to a difference between a driving gate electrode voltage of the driving transistor T1 and the driving voltage ELVDD.
A specific operation of each pixel P according to an embodiment is as follows.
During an initialization period, when the previous scan signal Sn-1 is applied through the previous scan line SLp, the first initialization transistor T4 is turned on in response to the previous scan signal Sn-1, and the driving transistor T1 is initialized by the first initialization voltage Vint1 supplied from the first initialization voltage line VL1.
During a data programming period, when the first scan signal Sn and the second scan signal Sn′ are supplied through the first scan line SL1 and the second scan line SL2, the switching transistor T2 and the compensation transistor T3 are turned on in response to the first scan signal Sn and the second scan signal Sn′. In this case, the driving transistor T1 is diode-connected by the turned-on compensation transistor T3, and is forward biased. Next, a compensation voltage Dm+Vth (Vth is a negative (−) value) obtained by subtracting a threshold voltage Vth of the driving transistor T1 from the data signal Dm supplied from the data line DL is applied to the driving gate electrode G1 of the driving transistor T1. The driving voltage ELVDD and the compensation voltage Dm+Vth are applied to both ends of the storage capacitor Cst, and a charge corresponding to a voltage difference between both ends is stored in the storage capacitor Cst.
During a light emission period, the operation control transistor T5 and the emission control transistor T6 are turned on by the emission control signal En supplied from the emission control line EL. Driving current according to a voltage difference between a voltage of the driving gate electrode G1 of the driving transistor T1 and the driving voltage ELVDD is generated, and the driving current is supplied to the organic light-emitting diode OLED through the emission control transistor T6.
As described above, some of the plurality of thin-film transistors (e.g., T1 through T7) may include an oxide semiconductor. For example, the compensation transistor T3 and the first initialization transistor T4 may include an oxide semiconductor.
Because polysilicon has high reliability, intended current may be controlled to flow accurately. Accordingly, the driving transistor T1 which directly affects a luminance of a display apparatus may include a semiconductor layer including polysilicon having high reliability, and thus, a high-resolution display apparatus may be realized. Because an oxide semiconductor has high carrier mobility and low leakage current, voltage drop is not large even when a driving time is long. That is, in the case of an oxide semiconductor, because a color change in an image due to voltage drop is not large even during low-frequency driving, low-frequency driving is possible. Accordingly, the compensation transistor T3 and the first initialization transistor T4 may include an oxide semiconductor, and thus, leakage current may be prevented and the display apparatus with reduced power consumption may be realized.
Because an oxide semiconductor is sensitive to light, the amount of current may be changed by external light. External light may be absorbed or reflected by locating a metal layer under the oxide semiconductor. Accordingly, as shown in
As shown in the drawings, the display apparatus may include a first pixel P1 and a second pixel P2 that are adjacent to each other. The first pixel P1 and the second pixel P2 may be symmetrical to each other with respect to a virtual line (not shown) as depicted in
A buffer layer 111 (see
The first semiconductor layer 1100 as shown in
Because the driving transistor T1, the switching transistor T2, the operation control transistor T5, the emission control transistor T6, and the second initialization transistor T7 may be PMOSs as described above, in this case, the thin-film transistors are located along the first semiconductor layer 1100 as shown in
A first gate insulating layer 113 (see
A first gate layer 1200 as shown in
The first gate line 1210 may extend in the second direction (the x-axis direction). The first gate line 1210 may be the first scan line SL1 or the next scan line SLn of
The first gate electrode 1220 may have an isolated shape. The first gate electrode 1220 is the driving gate electrode of the driving transistor T1. For reference, a portion of the first semiconductor layer 1100 including a part overlapping the first gate electrode 1220 may be referred to as a driving semiconductor layer.
The second gate line 1230 may extend in the second direction (the x-axis direction). The second gate line 1230 may correspond to the emission control line EL of
The shielding layer 1200 may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the first gate layer 1200 may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (AI), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The first gate layer 1200 may have a multi-layer structure. For example, the first gate layer 1200 may have a two-layer structure including Mo/Al or a three-layer structure including Mo/Al/Mo.
A second gate insulating layer 115 (see
A second gate layer 1300 may be located on the second gate insulating layer 115. The second gate layer 1300 may include a third gate line 1310, a fourth gate line 1320, a capacitor upper electrode 1330, and a first initialization voltage line 1340 (i.e., the first initialization voltage line VL1 of
The third gate line 1310 may extend in the second direction (the x-axis direction). The third gate line 1310 may correspond to the previous scan line SLp of
The fourth gate line 1320 may extend in the first direction (the x-axis direction), and may have an isolated shape as shown in
The third gate line 1310 and the fourth gate line 1320 may be located under the second semiconductor layer 1400 described below with reference to
The capacitor upper electrode 1330 may overlap the first gate electrode 1220, and may extend in the first direction (the x-axis direction). The capacitor upper electrode 1330 may correspond to the second capacitor electrode CE2 of
The first initialization voltage line 1340 corresponding to the first initialization voltage line VL1 of
The second gate layer 1300 may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the second gate layer 1300 may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (AI), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The second gate layer 1300 may have a multi-layer structure. For example, the second gate layer 1300 may have a two-layer structure including Mo/Al or may have a three-layer structure including Mo/Al/Mo.
A first interlayer insulating layer 117 (see
The second semiconductor layer 1400 as shown in
A third gate insulating layer 118 (see
The third gate layer 1500 as shown in
The fifth gate line 1520 may extend in the first direction (the x-axis direction), and may have an isolated shape. When viewed in the direction (the z-axis direction) perpendicular to the substrate 100, the fifth gate line 1520 may overlap the third gate line 1310. The fifth gate line 1520 may be electrically connected to the third gate line 1310 through a contact hole 1520CNT formed in an insulting layer between the fifth gate line 1520 and the third gate line 1310. Accordingly, the fifth gate line 1520 may correspond to the previous scan line SLp of
The sixth gate line 1530 may extend in the first direction (the x-axis direction). When viewed in the direction (the z-axis direction) perpendicular to the substrate 100, the sixth gate line 1530 may overlap the fourth gate line 1320. A portion of the sixth gate line 1530 overlapping the second semiconductor layer 1400 may be a compensation upper gate electrode of the compensation transistor T3. The sixth gate line 1530 may be electrically connected to the fourth gate line 1320. For example, the sixth gate line 1530 may be electrically connected to the fourth gate line 1320 through a contact hole 1530CNT formed in an insulating layer between the sixth gate line 1530 and the fourth gate line 1320. Accordingly, the sixth gate line 1530 may correspond to the second scan line SL2 of
The first transfer line 1540 may be electrically connected to the first gate electrode 1220 that is the driving gate electrode, through a contact hole 1540CNT passing through an opening 1330-OP of the capacitor upper electrode 1330. The first transfer line 1540 may transmit the first initialization voltage Vint1 transmitted through the first initialization transistor T4 to the first gate electrode 1220.
The third gate layer 1500 may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the third gate layer 1500 may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The third gate layer 1500 may have a multi-layer structure. For example, the third gate layer 1500 may have a two-layer structure including Mo/Al or may have a three-layer structure including Mo/Al/Mo.
The second interlayer insulating layer 119 (see
A first connection electrode layer 1600 as shown in
The vertical connection line 1610 may extend in the second direction (the x-axis direction). The 1-1th horizontal connection line H1-1, the 1-2th horizontal connection line H1-2, and 1-2th auxiliary horizontal connection line HCL1-2a, etc., described with reference to
The second transfer line 1620 may be electrically connected to the first semiconductor layer 1100 through a contact hole 1620CNT. The data signal Dm from a data line 1810 described below with reference to
The second initialization voltage line 1630 may extend in the first direction (the x-axis direction). The second initialization voltage line 1630 corresponding to the second initialization voltage line VL2 of
The third transfer line 1640 may electrically connect the second semiconductor layer 1400 and the first transfer line 1540 through contact holes 1640CNT1 and 1640CNT2 formed on a side and the other side. Because the first transfer line 1540 is electrically connected to the first gate electrode 1220 that is the driving gate electrode, the third transfer line 1640 may electrically connect a first initialization semiconductor layer that is a part of the second semiconductor layer 1400 to the driving gate electrode. The first initialization voltage Vint1 may be transmitted to the first gate electrode 1220 that is the driving gate electrode through the second semiconductor layer 1400, the third transfer line 1640, and the first transfer line 1540.
The fourth transfer line 1650 may electrically connect the second semiconductor layer 1400 and the first semiconductor layer 1100 through contact holes 1650CNT1 and 1650CNT2 formed on a side and the other side. That is, the fourth transfer line 1650 may electrically connect the compensation transistor T3 to the driving transistor T1.
The fifth transfer line 1660 may extend in the second direction (the x-axis direction). The driving voltage ELVDD that is a constant voltage from a driving voltage line 1830 described below with reference to
The sixth transfer line 1670 may be electrically connected to the first semiconductor layer 1100 through a contact hole 1670CNT. The sixth transfer line 1670 may transmit driving current or the second initialization voltage Vint2 from the first semiconductor layer 1100 to the organic light-emitting diode OLED.
The seventh transfer line 1680 may be electrically connected to the second semiconductor layer 1400 through the contact holes 1680CNT2 and 1680CNT3. The seventh transfer line 1680 may be electrically connected to the first initialization voltage line 1340 of
The first connection electrode layer 1600 may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the first connection electrode layer 1600 may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (AI), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The first connection electrode layer 1600 may have a multi-layer structure. For example, the first connection electrode layer 1600 may have a two-layer structure including Ti/Al or may have a three-layer structure including Ti/Al/Ti.
A third interlayer insulating layer 121 (see
A second connection electrode layer 1800 as shown in
The data line 1810 may extend in the first direction (the y-axis direction). The data line 1810 may correspond to the data line DL of
The data line 1810 may be electrically connected to the second transfer line 1620 through a contact hole 1810CNT, and the data signal Dm from the data line 1810 may be transmitted to the first semiconductor layer 1100 through the second transfer line 1620 and applied to the switching transistor T2.
The vertical connection line 1820 may extend substantially in the first direction (the y-axis direction). The vertical connection line 1820 may be any one of the first vertical connection line VCL1, the second vertical connection line VCL2, and the third vertical connection line VCL3 described with reference to
The driving voltage line 1830 may extend substantially in the first direction (the y-axis direction). The driving voltage line 1830 may correspond to the driving voltage line PL of
The tenth transfer line 1840 may be electrically connected to the sixth transfer line 1670 through a contact hole 1840CNT1, and may receive, from the sixth transfer line 1670, driving current or the second initialization voltage Vint2 from the first semiconductor layer 1100. Also, the tenth transfer line 1840 may transmit driving current or the second initialization voltage Vint2 from the first semiconductor layer 1100 to the first pixel (pixel electrode) of the organic light-emitting diode OLED through a contact hole 1840CNT2 formed in an insulating layer located over the tent transfer line 1840.
The second connection electrode layer 1800 may include a metal, an alloy, a conductive metal oxide, or a transparent conductive material. For example, the second connection electrode layer 1800 may include silver (Ag), an alloy containing silver, molybdenum (Mo), an alloy containing molybdenum, aluminum (AI), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The second connection electrode layer 1800 may have a multi-layer structure. For example, the second connection electrode layer 1800 may have a two-layer structure including Ti/Al or may have a three-layer structure including Ti/Al/Ti.
A planarization insulating layer 125 as shown in
As shown in
The pixel electrode 210 may be a (semi-)transmissive electrode or a reflective electrode. For example, the pixel electrode 310 may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (AI), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof, and a transparent or semi-transparent electrode layer located on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO or ZnO2), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). For example, the pixel electrode 210 may have a three-layer structure including ITO/Ag/ITO.
A pixel-defining film 127 may be located on the planarization insulating layer 125. The pixel-defining film 127 may increase a distance between an edge of the pixel electrode 210 and the counter electrode 230 over the pixel electrode 210, to prevent an arc or the like from occurring on the edge of the pixel electrode 210.
The pixel-defining film 127 may be formed of at least one organic insulating material selected from the group consisting of polyimide, polyamide, acrylic resin, BCB, and phenolic resin, by using spin coating or the like.
At least a part of the intermediate layer 220 of the organic light-emitting diode OLED may be located in an opening OP formed by the pixel-defining film 127. An emission area EA of the organic light-emitting diode OLED may be defined by the opening OP.
The intermediate layer 220 may include an emission layer. The emission layer may include an organic material including a fluorescent or phosphorescent material that emits red, green, blue, or white light. The emission layer may be formed of a low molecular weight organic material or a high molecular weight organic material, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) may be selectively located under and over the emission layer.
The emission layer may be patterned to correspond to each of the pixel electrodes 310. However, various modifications may be made. For example, layers other than the emission layer included in the intermediate layer 220 may be integrally formed as a single body over the plurality of pixel electrodes 210.
The counter electrode 230 may be a light-transmitting electrode or a reflective electrode. For example, the counter electrode 230 may be a transparent or semitransparent electrode, and may include Li, Ca, LiF, Al, Ag, Mg, or a compound thereof. Also, the counter electrode 230 may further include a transparent conductive oxide (TCO) film such as ITO, IZO, ZnO, ZnO2, or In2O3 located on a metal thin film. The counter electrode 330 may be integrally formed as a single body over the entire display area DA, and may be located over the intermediate layer 220 and the pixel-defining film 127.
The organic light-emitting diode OLED may be covered by a thin-film encapsulation layer (not shown) or may be covered by a sealing substrate. In an embodiment, the thin-film encapsulation layer may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. For example, the thin-film encapsulation layer may include a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer between the first and second inorganic encapsulation layers.
Each of the first inorganic encapsulation layer and the second inorganic encapsulation layer may include at least one inorganic insulating material such as silicon oxide (SiO2), silicon nitride (SiNX), silicon oxynitride (SiOXNY), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), and may be formed by using chemical vapor deposition (CVD) or the like. The organic encapsulation layer may include a polymer-based material. Examples of the polymer-based material may include a silicone-based resin, an acrylic resin (e.g., polymethyl methacrylate or polyacrylic acid), an epoxy resin, polyimide, and polyethylene.
Each of the first inorganic encapsulation layer, the organic encapsulation layer, and the second inorganic encapsulation layer may be integrally formed as a single body to cover the display area DA.
When necessary, a bottom metal layer BML may be located under the first pixel circuit PC1 and the second pixel circuit PC2. The bottom metal layer BML may be located between the substrate 100, and the first pixel circuit PC1 and the second pixel circuit PC2 to overlap the first pixel circuit PC1 and the second pixel circuit PC2, in order to protect the first pixel circuit PC1 and the second pixel circuit PC2. The bottom metal layer BML may prevent or minimize external light or an electric field formed in the substrate from reaching and affecting the first pixel circuit PC1 and the second pixel circuit PC2.
The portion A of
In the portion B of
In the portion C of
As shown in
The fifth transfer line 1660 located adjacent to the 1-2th horizontal connection line HCL1-2 and the 1-2th auxiliary horizontal connection line HCL1-2a to correspond to the 1-2th horizontal connection line HCL1-2 and the 1-2th auxiliary horizontal connection line HCL1-2a extends in the second direction (the x-axis direction) to cross the display area DA and extend toward the component area CA as shown in
As described above, the driving voltage line 1830 may be electrically connected to the fifth transfer line 1660 through the contact hole 1830CNT, to apply a constant voltage that is substantially the same as or similar to the driving voltage ELVDD to the fifth transfer line 1660. Because the fifth transfer line 1660 is electrically connected to the 1-2th auxiliary horizontal connection line HCL1-2a through a protrusion, a constant voltage that is substantially the same as or similar to the driving voltage ELVDD may be applied to the 1-2th auxiliary horizontal connection line HCL1-2a. Accordingly, the 1-2 auxiliary horizontal connection line HCL1-2a may be effectively prevented from being floated and increasing electrical instability in nearby pixels. Accordingly, a display apparatus capable of displaying a high-quality image that is not distorted even around the component area CA may be realized. This may be the same for the 2-2th auxiliary horizontal connection line HCL2-2a, the 3-2th auxiliary horizontal connection line HCL3-2a, the 3-1th auxiliary horizontal connection line HCL3-1a, the 2-1th auxiliary horizontal connection line HCL2-1a, and the 1-1th auxiliary horizontal connection line HCL1-1a. This is the same for the following embodiments and modifications thereof. For convenience, the 1-2th auxiliary horizontal connection line HCL1-2a will be described.
A protrusion of the fifth transfer line 1660 connected to the 1-2th auxiliary horizontal connection line HCL1-2a may be located farther from the component area CA than an end of the fifth transfer line 1660 close to the component area CA (in the +x direction), as shown in
As described with reference to
As described with reference to
As shown in
This is because the second initialization voltage line 1630 extending in the second direction (the x-axis direction) is located between the 1-2th auxiliary horizontal connection line HCL1-2a located in the nth row (RN) and the fifth transfer line 1660 located in the nth row (RN), and thus, a connection structure for electrically connecting them is complicated. In the display apparatus according to the present embodiment, when n is a natural number of 2 or more, because an auxiliary horizontal connection line located in the nth row is electrically connected to the fifth transfer line 1660 located in the n−1th row, a connection structure may be simplified.
Even in a portion other than the portion around the component area CA of the display apparatus, such as in a central portion of the display area DA as shown in
Accordingly, a first end of the horizontal connection line may be located in the peripheral area PA next to the display area DA in the −x direction, and a second end may be located in the peripheral area PA next to the display area DA in the +x direction. In addition, at least one of the first end and the second end of the horizontal connection line may be electrically connected to a constant voltage line in the peripheral area PA. For example, at least one of the first end and the second end of the horizontal connection line may be electrically connected to the common voltage supply line 13 of
The 1-1th additional horizontal connection line HCL1-1b, the 2-1th additional horizontal connection line HCL2-1b, the 3-1th additional horizontal connection line HCL3-1b, the 3-2th additional horizontal connection line HCL3-2b, the 2-2th additional horizontal connection line HCL2-2b, and the 1-2th additional horizontal connection line HCL1-2b located around the component area CA may not be used to transmit a data signal. Accordingly, in the case of each of the 1-1th additional horizontal connection line HCL1-1b, the 2-1th additional horizontal connection line HCL2-1b, the 3-1th additional horizontal connection line HCL3-1b, the 3-2th additional horizontal connection line HCL3-2b, the 2-2th additional horizontal connection line HCL2-2b, and the 1-2th additional horizontal connection line HCL1-2b, an end away from the component area CA may be located in the peripheral area PA next to a side of the display area DA. This end may be electrically connected to a constant voltage line in the peripheral area PA. For example, this end may be electrically connected to the common voltage supply line 13 as shown in
For reference, in the case of each of the 1-1th horizontal connection line HCL1-1, the 2-1th horizontal connection line HCL2-1, the 3-1th horizontal connection line HCL3-1, the 3-2th horizontal connection line HCL3-2, the 2-2th horizontal connection line HCL2-2, and the 1-2th horizontal connection line HCL1-2 functioning to transmit a data signal as described above, one of a first end and the second end farther from the component area CA is located in the display area DA as shown in
Although the display apparatus includes one component area CA as shown in
In addition, the fifth transfer lines 1660 extending in the second direction (the x-axis direction) are also located between the first component area CA1 and the second component area CA2 to cross the display area DA. The fifth transfer lines 1660 may correspond to the horizontal connection lines 1610 in a one-to-one manner. In this case, the fifth transfer lines 1660 include a plurality of protrusions 1660a and 1660a′ protruding in the first direction (the y-axis direction), and at least one of the protrusions 1660a and 1660a′ is electrically connected to the corresponding horizontal connection line 1610. In
As described with reference to
A protrusion of the fifth transfer line 1660 connected to the horizontal connection line 1610 may be located farther from the second component area CA2 than an end of the fifth transfer line 1660 close to the second component area CA2 (in the +x direction) as shown in
As described with reference to
As described with reference to
As shown in
This is because the second initialization voltage line 1630 extending in the second direction (the x-axis direction) is located between the horizontal connection line 1610 located in the nth row (RN) and the fifth transfer line 1660 located in the nth row (RN), and thus, a connection structure for electrically connecting them is complicated. In the display apparatus according to the present embodiment, when n is a natural number of 2 or more, because the horizontal connection line 1610 located in the nth row is electrically connected to the fifth transfer line 1660 located in the n−1th row, a connection structure may be simplified.
Although each pixel located in the display area DA includes seven transistors and one capacitor as shown in
The bias transistor T8 may be connected between the first node N1 and the bias voltage line VBL. The bias transistor T8 may be turned on according to the next scan signal Sn+1 received through the next scan line SLn, to apply the bias voltage VOBS to the first node N1 and pre-set a voltage suitable for a subsequent operation of the driving transistor T1 to the first node N1. In this regard, the next scan line SLn may be referred to as a bias gate line. For other points, the description of the equivalent circuit diagram of
According to an embodiment as described above, a display apparatus capable of displaying a high-quality image may be realized. However, the scope of the disclosure is not limited by this effect.
It should be understood that embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by one of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0039176 | Mar 2023 | KR | national |
| 10-2023-0089047 | Jul 2023 | KR | national |
