Patent Application
20230422559
The present application claims priority to and the benefit of Korean Patent Application No. 10-2022-0077807, filed on Jun. 24, 2022, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.
Aspects of one or more embodiments relate to a display apparatus.
Some layers of a display apparatus, for example, an intermediate layer between a pixel electrode and a counter electrode, may be commonly provided in a plurality of display elements. Accordingly, when a current is supplied to one display element, the current may be supplied to other neighboring display elements through the layers commonly provided in the display elements, and thus, the color purity of the display apparatus may be deteriorated. To address this matter, a display apparatus may include a separator and the like.
The above information disclosed in this Background section is only for enhancement of understanding of the background and therefore the information discussed in this Background section does not necessarily constitute prior art.
Aspects of one or more embodiments relate to display apparatuses, and for example, to display apparatuses which may reduce a leakage current and effectively transmit electrical signals to a plurality of counter electrodes.
In a display apparatus according to the related art, in a process of transmitting electrical signals to a plurality of counter electrodes, the electrical signals may not be effectively transmitted to the counter electrodes.
A display apparatus according to some embodiments may reduce a leakage current and also effectively transmit electrical signals to a plurality of counter electrodes. However, such characteristics are merely examples of some characteristics according to some embodiments, and the scope of embodiments according to the present disclosure is not limited thereby.
Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments of the disclosure.
According to some embodiments of the present disclosure, a display apparatus includes a first pixel electrode and a second pixel electrode spaced apart from each other on a substrate, a pixel defining layer having a first opening exposing a central portion of the first pixel electrode and a second opening exposing a central portion of the second pixel electrode, a separator above the pixel defining layer, and when viewed from a direction perpendicular to the substrate (e.g., in the plan view), spaced between the first opening and the second opening, a connection electrode interposed between the pixel defining layer and the separator, a first intermediate layer on the first pixel electrode, a second intermediate layer on the second pixel electrode and spaced apart from the first intermediate layer, a first counter electrode on the first intermediate layer and electrically connected to the connection electrode, and a second counter electrode on the second intermediate layer, spaced apart from the first counter electrode, and electrically connected to the connection electrode.
According to some embodiments, when viewed from the direction perpendicular to the substrate (e.g., in a plan view), the width of a portion of the first counter electrode overlapping the connection electrode may be greater than the width of a portion of the first intermediate layer overlapping the connection electrode.
According to some embodiments, the connection electrode may be in contact with the first counter electrode.
According to some embodiments, when viewed from the direction perpendicular to the substrate (e.g., in the plan view), the width of a portion of the second counter electrode overlapping the connection electrode may be greater than the width of a portion of the second intermediate layer overlapping the connection electrode.
According to some embodiments, the connection electrode may be in contact with the second counter electrode.
According to some embodiments, the display apparatus may further include a remaining counter electrode on the separator.
According to some embodiments, the first counter electrode, the second counter electrode, and the remaining counter electrode may include the same material.
According to some embodiments, the display apparatus may further include a remaining intermediate layer interposed between the separator and the remaining counter electrode.
According to some embodiments, the first intermediate layer, the second intermediate layer, and the remaining intermediate layer may include the same material.
According to some embodiments, the connection electrode may include a material different from the first pixel electrode and the second pixel electrode.
According to some embodiments, the connection electrode may include a material having resistance lower than a material included in the first pixel electrode and the second pixel electrode.
According to some embodiments, when viewed from the direction perpendicular to the substrate (e.g., in the plan view), the separator surrounds the first opening and the second opening, display apparatus.
According to some embodiments, when viewed from the direction perpendicular to the substrate (e.g., in the plan view), the connection electrode may surround the first opening and the second opening.
According to some embodiments, the side surface of the separator may include a reversely tapered inclined surface.
According to some embodiments, the display apparatus may further include a remaining counter electrode on the separator, and the remaining counter electrode may not cover the side surface of the separator.
According to some embodiments, the remaining counter electrode may be spaced apart from the first counter electrode and the second counter electrode.
According to some embodiments, the remaining counter electrode may not be electrically connected to the first counter electrode and the second counter electrode.
According to some embodiments, the display apparatus may further include a remaining intermediate layer interposed between the separator and the remaining counter electrode, and the remaining intermediate layer may not cover the side surface of the separator.
According to some embodiments, the remaining intermediate layer may be spaced apart from the first intermediate layer and the second intermediate layer.
According to some embodiments, the remaining intermediate layer may not be electrically connected to the first intermediate layer and the second intermediate layer.
The above and other aspects, features, and characteristics of certain embodiments of the disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:
Reference will now be made in more detail to aspects of some embodiments, which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present embodiments may have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the embodiments are merely described below, by referring to the figures, to explain aspects of some embodiments of the present description.
Various modifications may be applied to the present embodiments, and particular embodiments will be illustrated in the drawings and described in the detailed description section. The characteristics of embodiments according to the present disclosure, and a method to achieve the same, will be clearer referring to the detailed descriptions below with the drawings. However, the present embodiments may be implemented in various forms, not by being limited to the embodiments presented below.
Hereinafter, aspects of some embodiments will be described in more detail with reference to the accompanying drawings, and in the description with reference to the drawings, the same or corresponding constituents are indicated by the same reference numerals and redundant descriptions thereof are omitted.
In the following embodiments, it will be understood that when a layer, region, or component is referred to as being “formed on” another layer, region, or component, it can be directly or indirectly formed on the other layer, region, or component. That is, for example, intervening layers, regions, or components may be present. Sizes of components in the drawings may be exaggerated for convenience of explanation. For example, because sizes and thicknesses of components in the drawings are arbitrarily illustrated for convenience of explanation, the following embodiments are not limited thereto.
In the following embodiments, the x-axis, the y-axis and the z-axis are not limited to three axes of the rectangular coordinate system, and may be interpreted in a broader sense. For example, the x-axis, the y-axis, and the z-axis may be perpendicular to one another, or may represent different directions that are not perpendicular to one another.
In the following embodiments, it will be understood that although the terms “first,” “second,” etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are only used to distinguish one component from another.
In the following embodiments, the expression of singularity in the specification includes the expression of plurality unless clearly specified otherwise in context.
In the following embodiments, it will be further understood that the terms “comprises” and/or “comprising” used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.
In the specification, the expression such as “A and/or B” may include A, B, or A and B. Furthermore, the expression such as “at least one of A and B” may include A, B, or A and B.
Each of the pixels PX of the display apparatus 1 is an area where light of a certain color is emitted, and the display apparatus 1 may provide an image by using light emitted from the pixels PX. For example, each of the pixels PX may emit red light, green light, or blue light.
The display area DA may have, as illustrated in
The peripheral area PA may be a non-display area where the pixels PX are not arranged. A driver and the like for supplying electrical signals or power to the pixels PX may be arranged in the peripheral area PA. Pads to which various electronic elements, printed circuit boards, or the like ma be electrically connected may be arranged in the peripheral area PA. The pads are spaced apart from each other in the peripheral area PA, and may be electrically connected to printed circuit boards or integrated circuit devices.
The pixel circuit PC may include a first transistor T1, a second transistor T2, and a storage capacitor Cst. The second transistor T2, as a switching transistor, is connected to a scan line SL and a data line DL, and turned on in response to a switching signal input from the scan line SL to transmit a data signal input from the data line DL to the first transistor T1. One end of the storage capacitor Cst is electrically connected to the second transistor T2 and the other end thereof is electrically connected to a driving voltage line PL, and the storage capacitor Cst may store a voltage corresponding to a difference between a voltage received from the second transistor T2 and a driving power voltage ELVDD supplied through the driving voltage line PL.
The first transistor T1, as a driving transistor, is connected to the driving voltage line PL and the storage capacitor Cst, and may control the magnitude of a driving current flowing from the driving voltage line PL to the organic light-emitting diode OLED, corresponding to a voltage value stored in the storage capacitor Cst. The organic light-emitting diode OLED may emit light having a certain luminance, in response to the driving current. A counter electrode of the organic light-emitting diode OLED may receive an electrode power voltage ELVSS.
Although
As illustrated in
A first pixel electrode 210-1 of the first pixel PX1, a second pixel electrode 210-2 of the second pixel PX2, and a third pixel electrode 210-3 of the third pixel PX3 may be arranged in the display area DA. For example, the first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3 may be spaced apart from one another on a plane. The first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3 may have different sizes, as illustrated in
The pixel defining layer 215 is located above the first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3, and may include a first opening OP1, a second opening OP2, and a third opening OP3. The first opening OP1 may expose a central portion of the first pixel electrode 210-1, the second opening OP2 may expose a central portion of the second pixel electrode 210-2, and the third opening OP3 may expose a central portion of the third pixel electrode 210-3. The first opening OP1, the second opening OP2, and the third opening OP3 may have different sizes, as illustrated in
According to some embodiments, emission layers for emitting light may be located in each of the first opening OP1, the second opening OP2, and the third opening OP3 of the pixel defining layer 215. Counter electrodes may be arranged on the emission layers. A stack structure of the pixel electrode, the emission layer, and the counter electrode may form one organic light-emitting diode OLED. One opening of the pixel defining layer 215 may correspond to one organic light-emitting diode OLED, and define one emission area.
For example, a emission layer for emitting green light is arranged in the first opening OP1, and the first pixel PX1 may include a first emission area EA1 defined by the first opening OP1. Similarly, a emission layer for emitting red light is arranged in the second opening OP2, and the second pixel PX2 may include a second emission area EA2 defined by the second opening OP2. Similarly, an emission layer for emitting blue light is arranged in the third opening OP3, and the third pixel PX3 may include a third emission area EA3 defined by the third opening OP3. However, the disclosure is not limited thereto. For example, a emission layer for emitting blue light or green light may be arranged in the first opening OP1, the second opening OP2, and the third opening OP3. In this case, the display apparatus 1 may include a light-emitting panel and a color panel stacked in a thickness direction, for example, a z-axis direction, and blue light or green light emitted from the emission layer of the light-emitting panel may be converted into green light, red light, and blue light while passing through the color panel, or may transmit through the color panel.
The first opening OP1 and the second opening OP2 may be located adjacent to each other in a second direction, for example, a y-axis direction, crossing a first direction, for example, an x-axis direction, and the first opening OP1 and the third opening OP3 may be located adjacent to each other in the first direction, for example, the x-axis direction. As illustrated in
The separator SP may be located on the pixel defining layer 215. For example, when viewed from a direction perpendicular to the substrate 100 (e.g., in a plan view), for example, the z-axis direction, the separator SP may be located on the pixel defining layer 215 to surround the openings of the pixel defining layer 215, for example, the first opening OP1, the second opening OP2, and the third opening OP3. In other words, the separator SP may have a mesh structure. For example, the first opening OP1 may be located in a first separator hole SPH1 defined by the separator SP surrounding the first opening OP1 on a plane. Similarly, the second opening OP2 may be located in a second separator hole SPH2 defined by the separator SP on a plane, and the third opening OP3 may be located in a third separator hole SPH3 defined by the separator SP on a plane. Accordingly, the separator SP may be located between neighboring openings (or pixels).
Although
Although
The connection electrode CNE may be located below the separator SP. In other words, the connection electrode CNE may be interposed between the separator SP and the pixel defining layer 215. For example, when viewed from the direction perpendicular to the substrate 100 (e.g., in a plan view), for example, the z-axis direction, the connection electrode CNE may be located on the pixel defining layer 215 to overlap the separator SP.
The connection electrode CNE may have the same shape, for example, a mesh structure, as the pixel defining layer 215. Accordingly, when viewed from the direction perpendicular to the substrate 100 (e.g., in a plan view), for example, the z-axis direction, the connection electrode CNE may surround the openings of the pixel defining layer 215, for example, the first opening OP1, the second opening OP2, and the third opening OP3. For example, the first opening OP1 may be located in a first connection electrode hole CNEH1 defined by the connection electrode CNE surrounding the first opening OP1 on a plane. Similarly, the second opening OP2 may be located in a second connection electrode hole CNEH2 defined by the connection electrode CNE on a plane, and the third opening OP3 may be located in the third separator hole SPH3 defined by the connection electrode CNE on a plane. Accordingly, the connection electrode CNE may be located between the neighboring openings (or pixels). The first connection electrode hole CNEH1 may be smaller than or equal to the first separator hole SPH1. Similarly, the second connection electrode hole CNEH2 may be smaller than or equal to the second separator hole SPH2, and a third connection electrode hole CNEH3 may be smaller than or equal to the third separator hole SPH3.
Although
Although
As illustrated in
The pixels PX including a plurality of display elements and the pixel circuit PC may be arranged on the substrate 100. In
The pixel circuit PC may be located on the substrate 100. As the structure of the pixel circuit PC of each of the pixels PX is the same, one pixel circuit PC is mainly described. The pixel circuit PC may include a plurality of thin film transistors TFT and the storage capacitor Cst. For convenience of illustration,
A buffer layer 201 including an inorganic material, such as a silicon oxide, a silicon nitride, a silicon oxynitride, and/or the like may be interposed between the thin film transistor TFT and the substrate 100. The buffer layer 201 may increase smoothness of an upper surface of the substrate 100, or prevent or reduce infiltration of impurities from the substrate 100 and the like into a semiconductor layer Act of the thin film transistor TFT.
As illustrated in
TFT may include a gate electrode GE, a source electrode SE, and/or a drain electrode DE. The gate electrode GE may include various conductive materials and have various layered structures including, for example, a Mo layer and an Al layer. Alternatively, the gate electrode GE may include a TiNx layer, an Al layer, and/or a Ti layer. The source electrode SE and the drain electrode DE may also include various conductive materials and have various layered structures including, for example, a Ti layer, an Al layer, and/or a Cu layer.
To secure insulation between the semiconductor layer Act and the gate electrode GE, a gate insulating layer 203 including an inorganic material, such as a silicon oxide, a silicon nitride, a silicon oxynitride, and/or like may be interposed between the semiconductor layer Act and the gate electrode GE. Although
In addition, a first interlayer insulating layer 205 including an inorganic material, such as a silicon oxide, a silicon nitride, a silicon oxynitride, and/or like may be located above the gate electrode GE. The first interlayer insulating layer 205 may have a single layer or multilayer structure including the material described above. As such, an insulating film including an inorganic material may be formed by a chemical vapor deposition (CVD) method or an atomic layer deposition (ALD) method. This also applies to embodiments and modified examples thereof which are described below.
The storage capacitor Cst may include a first electrode CE1 and a second electrode CE2, which overlap each other with the first interlayer insulating layer 205 therebetween. The storage capacitor Cst may overlap the thin film transistor TFT. In this connection, although
A second interlayer insulating layer 207 including an inorganic material, such as a silicon oxide, a silicon nitride, a silicon oxynitride, and/or like, may be located above the second electrode CE2 of the storage capacitor Cst. The second interlayer insulating layer 207 may have a single layer or multilayer structure including the material described above.
The source electrode SE and the drain electrode DE may be located on the second interlayer insulating layer 207. The data line DL may be located on the same layer, and may include the same material, as the source electrode SE and the drain electrode DE. The source electrode SE, the drain electrode DE, and the data line DL may include an excellent conductive material. The source electrode SE and the drain electrode DE may each include a conductive material including Mo, Al, Cu, Ti, and the like, and may have a multilayer or single layer structure including the above materials. For example, the source electrode SE, the drain electrode DE, and the data line DL may each have a multilayer structure of Ti/Al/Ti.
The disclosure is not limited thereto. For example, the thin film transistor TFT may include any one of the source electrode SE and the drain electrode DE, or may include none of the source electrode SE and the drain electrode DE. For example, one thin film transistor TFT does not include the drain electrode DE, the other thin film transistor TFT connected to the one thin film transistor TFT does not include the source electrode SE, and the semiconductor layers Act of the two thin film transistors may be connected to each other. Such a connection structure may have the same effect as a structure in which the one thin film transistor TFT further includes the source electrode SE, the other thin film transistor TFT further includes the drain electrode DE, and the source electrode SE of the one thin film transistor TFT is connected to the drain electrode DE of the other thin film transistor TFT.
As illustrated in
The first organic light-emitting diode OLED1, the second organic light-emitting diode OLED2, and the third organic light-emitting diode OLED3 may be spaced apart from one another on the planarization layer 208. For example, the first organic light-emitting diode OLED1 and the second organic light-emitting diode OLED2 that are adjacent to each other in the second direction, for example, the y-axis direction, crossing the first direction, for example, the x-axis direction, may be located on the planarization layer 208, and the third organic light-emitting diode OLED3 may be located on the planarization layer 208 to be adjacent to the first organic light-emitting diode OLED1 in the first direction, for example, the x-axis direction. The first organic light-emitting diode OLED1, the second organic light-emitting diode OLED2, and the third organic light-emitting diode OLED3 may respectively emit light of different colors. For example, the first organic light-emitting diode OLED1 may emit green light, the second organic light-emitting diode OLED2 may emit red light, and the third organic light-emitting diode OLED3 may emit blue light.
The first organic light-emitting diode OLED1 may include the first pixel electrode 210-1, a first intermediate layer 220-1, and a first counter electrode 230-1. The second organic light-emitting diode OLED2 may include the second pixel electrode 210-2, a second intermediate layer 220-2, and a second counter electrode 230-2. The third organic light-emitting diode OLED3 may include the third pixel electrode 210-3, a third intermediate layer 220-3, and a third counter electrode 230-3.
The first pixel electrode 210-1 and the second pixel electrode 210-2 may be spaced apart from each other on the planarization layer 208. For example, the second pixel electrode 210-2 may be arranged adjacent to the first pixel electrode 210-1 in the second direction, for example, the y-axis direction, on the planarization layer 208. The third pixel electrode 210-3 may be arranged on the planarization layer 208 apart from the first pixel electrode 210-1. For example, the third pixel electrode 210-3 may be arranged adjacent to the first pixel electrode 210-1 in the first direction, for example, the x-axis direction, on the planarization layer 208.
The first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3 may each include a light-transmissive conductive layer including a conductive oxide, such as ITO, In2O3, IZO, or the like, which is light-transmissive, and a reflective layer including a metal, such as Al, Ag, or the like. For example, the first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3 may each have a three-layer structure of ITO/Ag/ITO.
The first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3 may each be in contact with any one of the source electrode SE and the drain electrode DE, as illustrated in
The pixel defining layer 215 may be located on the planarization layer 208. The pixel defining layer 215 having an opening corresponding to each of the pixels PX, that is, an opening exposing the central portion of at least pixel electrode may define each of the pixels PX. For example, the pixel defining layer 215 may have the first opening OP1, the second opening OP2, and the third opening OP3. The first opening OP1 may expose the central portion of the first pixel electrode 210-1, the second opening OP2 may expose the central portion of the second pixel electrode 210-2, and the third opening OP3 may expose the central portion of the third pixel electrode 210-3. Furthermore, as in the case illustrated in
The first intermediate layer 220-1 may be located on the first pixel electrode 210-1. The second intermediate layer 220-2 may be located on the second pixel electrode 210-2, and the third intermediate layer 220-3 may be located on the third pixel electrode 210-3. The first intermediate layer 220-1, the second intermediate layer 220-2, and the third intermediate layer 220-3 may be spaced apart from one another on a plane. In other words, the second intermediate layer 220-2 may be spaced apart from the first intermediate layer 220-1 on a plane, and the third intermediate layer 220-3 may be spaced apart from the first intermediate layer 220-1 and the second intermediate layer 220-2 on a plane.
The first intermediate layer 220-1, the second intermediate layer 220-2, and the third intermediate layer 220-3 may each include a low molecular weight or polymer material. When each of the first intermediate layer 220-1, the second intermediate layer 220-2, and the third intermediate layer 220-3 includes a low molecular weight material, the first intermediate layer 220-1, the second intermediate layer 220-2, and the third intermediate layer 220-3 may each have a stack structure of a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), an electron injection layer (EIL), and the like, in a single or composite structure, and may be formed by a vacuum deposition method.
When each of the first intermediate layer 220-1, the second intermediate layer 220-2, and the third intermediate layer 220-3 includes a polymer material, the first intermediate layer 220-1, the second intermediate layer 220-2, and the third intermediate layer 220-3 may each have a structure including the HTL and the EML. In this case, the HTL may include poly-(3,4-ethylenedioxythiophene) (PEDOT), and the EML may include a polymer material based on polyphenylene vinylene (PPV), polyfluorene, and the like. The first intermediate layer 220-1, the second intermediate layer 220-2, and the third intermediate layer 220-3 may each be formed by a screen printing method, an inkjet printing method, a laser induced thermal imaging (LITI) method, and the like.
As illustrated in
As illustrated in
The first-1 common layer 221-1 may be interposed between the first pixel electrode 210-1 and the first lower emission layer 222L-1. The first-1 common layer 221-1 may have a single layer or multilayer structure. For example, when the first-1 common layer 221-1 includes a polymer material, the first-1 common layer 221-1, as the HTL that is a single layer structure, may include PEDOT, polyaniline (PANI), N, N′-diphenyl-N,N′-bis(3-methylphenyl)-1,1′-bi-phenyl-4,4′-diamine (TPD), or N,N′-di(naphthalen-1-yl)-N,N′-diphenyl-benzidine (NPB). When the first-1 common layer 221-1 includes a low molecular weight material, the first-1 common layer 221-1 may include the HIL and the HTL.
The second-1 common layer 227-1 may be located on the first upper emission layer 222U-1. The second-1 common layer 227-1 may not always be provided. For example, when each of the first-1 common layer 221-1 and the first emission layer 222-1 includes a polymer material, the second-1 common layer 227-1 may be formed. The second-1 common layer 227-1 may have a single layer or multilayer structure. The second-1 common layer 227-1 may include the ETL and/or the EIL. The first counter electrode 230-1 may be located on the second-1 common layer 227-1.
The first intermediate layer 220-1 may further include a first charge generation layer 224-1. The first charge generation layer 224-1 may be located between the first lower emission layer 222L-1 and the first upper emission layer 222U-1. The first charge generation layer 224-1 may supply electric charges to a first stack including the first lower emission layer 222L-1 and a second stack including the first upper emission layer 222U-1.
The first intermediate layer 220-1 may further include a third-1 common layer 223-1 and a fourth-1 common layer 225-1. The third-1 common layer 223-1 may be located between the first lower emission layer 222L-1 and the first charge generation layer 224-1. The fourth-1 common layer 225-1 may be located between the first charge generation layer 224-1 and the first upper emission layer 222U-1. The third-1 common layer 223-1 may include the ETL, and the fourth-1 common layer 225-1 may include the HTL.
For example, the first intermediate layer 220-1 may include the first-1 common layer 221-1, the first lower emission layer 222L-1, the third-1 common layer 223-1, the first charge generation layer 224-1, the fourth-1 common layer 225-1, the first upper emission layer 222U-1, and the second-1 common layer 227-1.
As illustrated in
As illustrated in
The first-2 common layer 221-2 may be interposed between second pixel electrode 210-2 and the second lower emission layer 222L-2. The second-2 common layer 227-2 may be located on the second upper emission layer 222U-2. The second intermediate layer 220-2 may further include a second charge generation layer 224-2, and the second charge generation layer 224-2 may be located between the second lower emission layer 222L-2 and the second upper emission layer 222U-2. The second intermediate layer 220-2 may further include a third-2 common layer 223-2 and a fourth-2 common layer 225-2. For example, the second intermediate layer 220-2 may include the first-2 common layer 221-2, the second lower emission layer 222L-2, the third-2 common layer 223-2, the second charge generation layer 224-2, the fourth-2 common layer 225-2, the second upper emission layer 222U-2, and the second-2 common layer 227-2.
As the descriptions with respect to the first-1 common layer 221-1, the third-1 common layer 223-1, the first charge generation layer 224-1, the fourth-1 common layer 225-1, and the second-1 common layer 227-1 may be respectively applied to the first-2 common layer 221-2, the third-2 common layer 223-2, the second charge generation layer 224-2, the fourth-2 common layer 225-2, and the second-2 common layer 227-2, redundant descriptions in this connection are omitted.
As illustrated in
As illustrated in
The first-3 common layer 221-3 may be interposed between the third pixel electrode 210-3 and the third lower emission layer 222L-3. The second-3 common layer 227-3 may be located on the third upper emission layer 222U-3. The third intermediate layer 220-3 may further include a third charge generation layer 224-3, and the third charge generation layer 224-3 may be located between the third lower emission layer 222L-3 and the third upper emission layer 222U-3. The third intermediate layer 220-3 may further include a third-3 common layer 223-3 and a fourth-3 common layer 225-3. For example, the third intermediate layer 220-3 may include the first-3 common layer 221-3, the third lower emission layer 222L-3, the third-3 common layer 223-3, the third charge generation layer 224-3, the fourth-3 common layer 225-3, the third upper emission layer 222U-3, and the second-3 common layer 227-3.
As the descriptions with respect to the first-1 common layer 221-1, the third-1 common layer 223-1, the first charge generation layer 224-1, the fourth-1 common layer 225-1 and the second-1 common layer 227-1 may be respectively applied to the first-3 common layer 221-3, the third-3 common layer 223-3, the third charge generation layer 224-3, the fourth-3 common layer 225-3, and the second-3 common layer 227-3, redundant descriptions in this connection are omitted.
The first-1 common layer 221-1, the first-2 common layer 221-2, and the first-3 common layer 221-3 may be simultaneously formed of the same material in the same process. For example, when the material for forming the first-1 common layer 221-1, the first-2 common layer 221-2, and the first-3 common layer 221-3 may be deposited on the entire surface of the substrate 100. The third-1 common layer 223-1, the third-2 common layer 223-2, and the third-3 common layer 223-3 may be simultaneously formed of the same material in the same process, and the first charge generation layer 224-1, the second charge generation layer 224-2, and the third charge generation layer 224-3 may be simultaneously formed of the same material in the same process. For example, when the material for forming the third-1 common layer 223-1, the third-2 common layer 223-2, and the third-3 common layer 223-3 may be deposited on the entire surface of the substrate 100, and the material for forming the first charge generation layer 224-1, the second charge generation layer 224-2, and the third charge generation layer 224-3 may be deposited on the entire surface of the substrate 100.
The fourth-1 common layer 225-1, the fourth-2 common layer 225-2, and the fourth-3 common layer 225-3 may be simultaneously formed of the same material in the same process, and the second-1 common layer 227-1, the second-2 common layer 227-2, and the second-3 common layer 227-3 may be simultaneously formed of the same material in the same process. For example, when the material for forming the fourth-1 common layer 225-1, the fourth-2 common layer 225-2, and the fourth-3 common layer 225-3 may be deposited on the entire surface of the substrate 100, and the material for forming the second-1 common layer 227-1, the second-2 common layer 227-2, and the second-3 common layer 227-3 may be deposited on the entire surface of the substrate 100.
The first counter electrode 230-1 may be located on the first intermediate layer 220-1. The second counter electrode 230-2 may be located on the second intermediate layer 220-2, and the third counter electrode 230-3 may be located on the third intermediate layer 220-3. In other words, the first intermediate layer 220-1 may be interposed between the first pixel electrode 210-1 and the first counter electrode 230-1, the second intermediate layer 220-2 may be interposed between the second pixel electrode 210-2 and the second counter electrode 230-2, and the third intermediate layer 220-3 may be interposed between the third pixel electrode 210-3 and the third counter electrode 230-3. The first counter electrode 230-1, the second counter electrode 230-2, and the third counter electrode 230-3 may be spaced apart from one another on a plane. In other words, the second counter electrode 230-2 may be spaced apart from the first counter electrode 230-1 on a plane, and the third counter electrode 230-3 may be spaced apart from the first counter electrode 230-1 and the second counter electrode 230-2 on a plane.
The first counter electrode 230-1, the second counter electrode 230-2, and the third counter electrode 230-3 may each include a light-transmissive conductive layer including ITO, In2O3, or IZO, and also include a semi-transmissive film including a metal, such as Al, Ag, or the like. For example, the first counter electrode 230-1, the second counter electrode 230-2, and the third counter electrode 230-3 may each include a semi-transmissive film including Mg or Ag. According to some embodiments, a capping layer may be located on the first counter electrode 230-1, the second counter electrode 230-2, and the third counter electrode 230-3. For example, the capping layer may include a material selected from among an organic material, an inorganic material, and mixtures thereof, and may be provided in a single layer or multilayer. A LiF layer may be located on the capping layer according to some embodiments. The first counter electrode 230-1, the second counter electrode 230-2, and the third counter electrode 230-3 may be simultaneously formed of the same material in the same process. For example, when the material for forming the first counter electrode 230-1, the second counter electrode 230-2, and the third counter electrode 230-3 may be deposited on the entire surface of the substrate 100.
The separator SP may be located above the pixel defining layer 215. For example, when viewed from the direction perpendicular to the substrate 100 (e.g., in a plan view), the separator SP may be arranged between the first opening OP1 and the second opening OP2. As described above with reference to
A remaining intermediate layer 220a and a remaining counter electrode 230a may be located on the separator SP.
The first remaining common layer 221a, the first-1 common layer 221-1, the first-2 common layer 221-2, and the first-3 common layer 221-3 may be simultaneously formed of the same material in the same process. For example, when the material for forming the first-1 common layer 221-1, the first-2 common layer 221-2, and the first-3 common layer 221-3 are deposed on the entire surface of the substrate 100, a layer formed on the separator SP may be the first remaining common layer 221a. The third remaining common layer 223a, the third-1 common layer 223-1, the third-2 common layer 223-2, and the third-3 common layer 223-3 may be simultaneously formed of the same material in the same process. For example, when the material for forming the third-1 common layer 223-1, the third-2 common layer 223-2, and the third-3 common layer 223-3 is deposited on the entire surface of the substrate 100, a layer formed above the separator SP may be the third remaining common layer 223a. For example, the third remaining common layer 223a may be formed on the first remaining common layer 221a.
The remaining charge generation layer 224a, the first charge generation layer 224-1, the second charge generation layer 224-2, and the third charge generation layer 224-3 may be simultaneously formed of the same material in the same process. For example, when the material for forming the first charge generation layer 224-1, the second charge generation layer 224-2, and the third charge generation layer 224-3 is deposited on the entire surface of the substrate 100, a layer formed above the separator SP may be the remaining charge generation layer 224a. For example, the remaining charge generation layer 224a may be formed on the third remaining common layer 223a. The fourth remaining common layer 225A, the fourth-1 common layer 225-1, the fourth-2 common layer 225-2, and the fourth-3 common layer 225-3 may be simultaneously formed of the same material in the same process. For example, when the material for forming the fourth-1 common layer 225-1, the fourth-2 common layer 225-2, and the fourth-3 common layer 225-3 is deposited on the entire surface of the substrate 100, a layer formed on the separator SP may be the fourth remaining common layer 225A. For example, the fourth remaining common layer 225A may be formed on the remaining charge generation layer 224a.
The second remaining common layer 227a, the second-1 common layer 227-1, the second-2 common layer 227-2, and the second-3 common layer 227-3 may be simultaneously formed of the same material in the same process. For example, when the material for forming the second-1 common layer 227-1, the second-2 common layer 227-2, and the second-3 common layer 227-3 is deposited on the entire surface of the substrate 100, a layer formed above the separator SP may be the second remaining common layer 227a. For example, the second remaining common layer 227a may be formed on the fourth remaining common layer 225A. The remaining counter electrode 230a, the first counter electrode 230-1, the second counter electrode 230-2, and the third counter electrode 230-3 may be simultaneously formed of the same material in the same process. For example, when the material for forming the first counter electrode 230-1, the second counter electrode 230-2, and the third counter electrode 230-3 is deposited on the entire surface of the substrate 100, a layer formed above the separator SP may be the remaining counter electrode 230a. For example, the remaining counter electrode 230a may be formed on the second remaining common layer 227a.
The separator SP may include an organic insulating material. For example, the separator SP may include BCB, polyimide, HMDSO, PMMA, polystyrene, polymer derivatives having a phenolic group, acrylic polymer, imide-based polymer, aryl ether-based polymer, amide-based polymer, fluorine-based polymer, p-xylene-based polymer, vinyl alcohol-based polymer, mixtures thereof, or the like.
A side surface Spa of the separator SP may include a reversely tapered inclined surface. The side surface SPa of the separator SP including the reversely tapered inclined surface may mean that the width of a portion of the separator SP in a direction opposite to the substrate 100 (+z direction) is greater than the width of a portion of the separator SP in a direction close to the substrate 100 (−z direction). The separator SP having a side surface that is a reversely tapered inclined surface may be formed by using negative photoresist. The photoresist may be classified into positive photoresist and negative photoresist. The positive photoresist may mean photoresist having an increasing solubility to a developer by exposure, and the negative photoresist may mean photoresist having a decreasing solubility to a developer by exposure.
Accordingly, when positive photoresist that is partially exposed is developed, a pattern in which an exposed portion is removed is generated, and when negative photoresist that is partially exposed is developed, a pattern in which a portion that is not exposed is removed is generated. Thus, when a layer on which negative photoresist is applied is exposed by using a mask, not only a portion located below a transmitting portion of the mask, but also a portion adjacent to a lower portion of the transmitting portion, may be exposed. For example, the portion adjacent to the lower portion of the transmitting portion may have a gradually increasing solubility to a developer from an upper end located in a direction close to a light source toward a lower end located in a direction opposite to the light source. Accordingly, the pattern having a reversely tapered inclined surface may be formed.
As the side surface Spa of the separator SP includes a reversely tapered inclined surface, the remaining intermediate layer 220a and the remaining counter electrode 230a may not cover the side surface SPa of the separator SP. Accordingly, the remaining intermediate layer 220a may not be connected to the first intermediate layer 220-1 and the second intermediate layer 220-2, and the remaining counter electrode 230a may not be connected to the first counter electrode 230-1 and second counter electrode. In other words, the remaining intermediate layer 220a may be spaced apart from the first intermediate layer 220-1 and the second intermediate layer 220-2, and the remaining counter electrode 230a may be spaced apart from the first counter electrode 230-1 and second counter electrode. The remaining intermediate layer 220a may not also be connected to the third intermediate layer 220-3, and the remaining counter electrode 230a may not also be connected to the third counter electrode 230-3. In other words, the remaining intermediate layer 220a may be spaced apart from the third intermediate layer 220-3, and the remaining counter electrode 230a may be spaced apart from the third counter electrode 230-3.
Accordingly, the remaining intermediate layer 220a may not be electrically connected to the first intermediate layer 220-1 and the second intermediate layer 220-2, and the remaining counter electrode 230a may not be electrically connected to the first counter electrode 230-1 and second counter electrode. The remaining intermediate layer 220a may not also be electrically connected to the third intermediate layer 220-3, and the remaining counter electrode 230a may not also be electrically connected to the third counter electrode 230-3.
As described above, the first intermediate layer 220-1 of the first organic light-emitting diode OLED1, the second intermediate layer 220-2 of the second organic light-emitting diode OLED2, and the third intermediate layer 220-3 of the third organic light-emitting diode OLED3 may include layers simultaneously formed of the same material in the same process. For example, such layers may be formed by depositing a material for forming the corresponding layers on the entire surface of a substrate. When the separator SP does not exist on the pixel defining layer 215, those layers may be integrally formed in the first organic light-emitting diode OLED1, the second organic light-emitting diode OLED2, and the third organic light-emitting diode OLED3. Accordingly, a leakage current may flow between the first organic light-emitting diode OLED1 and the second organic light-emitting diode OLED2 through those layers.
For example, when a current is supplied only to the first organic light-emitting diode OLED1 that emits green light, a current may be supplied to the second organic light-emitting diode OLED2 via a layer integrally formed with the first-1 common layer 221-1 of the first organic light-emitting diode OLED1, for example, the first-2 common layer 221-2. Alternatively, a current may be supplied to the second organic light-emitting diode OLED2 via a layer integrally formed with the third-1 common layer 223-1, for example, the third-2 common layer 223-2, or a current may be supplied to the second organic light-emitting diode OLED2 via a layer integrally formed with the first charge generation layer 224-1, for example, the second charge generation layer 224-2. Alternatively, a current may be supplied to the second organic light-emitting diode OLED2 via a layer integrally formed with the fourth-1 common layer 225-1, for example, the fourth-2 common layer 225-2, or a current may be supplied to the second organic light-emitting diode OLED2 via a layer integrally formed with the second-1 common layer 227-1, for example, the second-2 common layer 227-2.
As a result, as not only the first organic light-emitting diode OLED1 emits green light, but also the second organic light-emitting diode OLED2 emits red light, display quality may be deteriorated. For example, color purity is lowered. A phenomenon that a current is supplied to the second organic light-emitting diode OLED2 via a layer integrally formed with the first-1 common layer 221-1 of the first organic light-emitting diode OLED1 may also occur in the third organic light-emitting diode OLED3.
However, in the case of the display apparatus 1 according to some embodiments, as described above, the separator SP may be located above the planarization layer 208. Accordingly, even when some of the layers included in the first intermediate layer 220-1, some of the layers included in the second intermediate layer 220-2, and some of the layers included in the third intermediate layer 220-3 are simultaneously formed of the same material in the same process, those layers may not be integrally formed in the first organic light-emitting diode OLED1, the second organic light-emitting diode OLED2, and the third organic light-emitting diode OLED3. In other words, the remaining intermediate layer 220a may be arranged between the first intermediate layer 220-1 and the second intermediate layer 220-2, and the remaining intermediate layer 220a may not be in contact with the first intermediate layer 220-1 and the second intermediate layer 220-2. Accordingly, the first intermediate layer 220-1 and the second intermediate layer 220-2 may be spaced apart from each other.
For example, the first remaining common layer 221a may not be in contact with the first-1 common layer 221-1 and the first-2 common layer 221-2, and the third remaining common layer 223a may not be in contact with the third-1 common layer 223-1 and the third-2 common layer 223-2. The remaining charge generation layer 224a may not be in contact with the first charge generation layer 224-1 and the second charge generation layer 224-2, the fourth remaining common layer 225A may not be in contact with the fourth-1 common layer 225-1 and the fourth-2 common layer 225-2, and the second remaining common layer 227a may not be in contact with the second-1 common layer 227-1 and the second-2 common layer 227-2.
Accordingly, a current may not leak between the first organic light-emitting diode OLED1 and the second organic light-emitting diode OLED2 through those layers. As the separator SP is arranged between the first opening OP1 and the third opening OP3 on a plane, an effect of preventing current leakage between the first organic light- emitting diode OLED1 and the second organic light-emitting diode OLED2 may be obtained between the first organic light-emitting diode OLED1 and the third organic light-emitting diode OLED3.
The connection electrode CNE may be interposed between the pixel defining layer 215 and the separator SP. In other words, the connection electrode CNE may be located on the pixel defining layer 215. Accordingly, the connection electrode CNE may be located on a layer different from the first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3. When the connection electrode CNE is located on the same layer as the first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3, for example, on the planarization layer 208, an area occupied by the first pixel electrode 210-1, the second pixel electrode 210-2, and/or the third pixel electrode 210-3 may be reduced. Accordingly, the first emission area EA1, the second emission area EA2, and/or the third emission area EA3 may be reduced. However, in the case of the display apparatus 1 according to some embodiments, the connection electrode CNE may be located on a layer different from the first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3. Accordingly, the area occupied by the first pixel electrode 210-1, the second pixel electrode 210-2, and/or the third pixel electrode 210-3 may not be reduced. Accordingly, the first emission area EA1, the second emission area EA2, and the third emission area EA3 of desired sizes may be formed.
The connection electrode CNE may include a material different from the materials included in the first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3. For example, the connection electrode CNE may include a material having resistance lower than the material included in the first pixel electrode 210-1, the second pixel electrode 210-2, and the third pixel electrode 210-3. For example, the connection electrode CNE may include Cu. As described below, the connection electrode CNE may electrically connect a plurality of counter electrodes to each other, and as the counter electrodes are electrically connected to each other, electrical signals may be effectively transmitted to the counter electrodes via the connection electrode CNE. As the resistance, that is, electrical resistance, of the connection electrode CNE that electrically connect the counter electrodes to each other, is low, the electrical signals may be effectively transmitted to the counter electrodes.
When viewed from the direction perpendicular to the substrate 100 (e.g., in a plan view), the connection electrode CNE may be arranged between the first opening OP1 and the second opening OP2. As described above with reference to
The first intermediate layer 220-1 may be located above the connection electrode CNE. For example, the first intermediate layer 220-1 may be located on a part of an upper surface of the connection electrode CNE adjacent to one side surface of the connection electrode CNE. As described above, some of the layers included in the first intermediate layer 220-1, for example, the first-1 common layer 221-1, the third-1 common layer 223-1, the first charge generation layer 224-1, the fourth-1 common layer 225-1, or the second-1 common layer 227-1 may be formed by respectively depositing the materials for forming those layers on the entire surface of the substrate 100. Accordingly, when viewed from the direction perpendicular to the substrate 100 (e.g., in a plan view), the first intermediate layer 220-1 may overlap not only the first pixel electrode 210-1, but also the pixel defining layer 215 and the connection electrode CNE.
The first counter electrode 230-1 may be located above the connection electrode CNE. For example, as the first counter electrode 230-1 may be located on the first intermediate layer 220-1, the first counter electrode 230-1 may be located on a part of the first intermediate layer 220-1 located on the connection electrode CNE. Like some of the layers included in the first intermediate layer 220-1 described above, the first counter electrode 230-1 may be formed by depositing the material for forming the first counter electrode 230-1 on the entire surface of the substrate 100. Accordingly, when viewed from the direction perpendicular to the substrate 100 (e.g., in a plan view), the first counter electrode 230-1 may overlap not only the first pixel electrode 210-1, but also the pixel defining layer 215 and the connection electrode CNE.
The descriptions with respect to the position relation between the connection electrode CNE, and the first intermediate layer 220-1 and the first counter electrode 230-1, may be applied to the position relation between the connection electrode CNE, and the second intermediate layer 220-2 and the second counter electrode 230-2. Also, the descriptions with respect to the position relation between the connection electrode CNE, and the first intermediate layer 220-1 and the first counter electrode 230-1, may be applied to the position relation between the connection electrode CNE, and the third intermediate layer 220-3 and the third counter electrode 230-3. Accordingly, redundant descriptions in this connection are omitted.
When viewed from the direction perpendicular to the substrate 100 (e.g., in a plan view), a width 220-1OW of a portion of the first intermediate layer 220-1 overlapping the connection electrode CNE may be different from a width 230-1OW of a portion of the first counter electrode 230-1 overlapping the connection electrode CNE. As illustrated in
Similarly, when viewed from the direction perpendicular to the substrate 100 (e.g., in a plan view), a width 220-2OW of a portion of the second intermediate layer 220-2 overlapping the connection electrode CNE may be different from a width 230-2OW of a portion of the second counter electrode 230-2 overlapping the connection electrode CNE. As illustrated in
As the descriptions with respect to the width 220-2OW of the portion of the second intermediate layer 220-2 overlapping the connection electrode CNE and the width 230-2OW of the portion of the second counter electrode 230-2 overlapping the connection electrode CNE may be respectively applied to the width of a portion of the third intermediate layer 220-3 overlapping the connection electrode CNE and the width of a portion of the third counter electrode 230-3 overlapping the connection electrode CNE, redundant descriptions in this connection are omitted.
Generally, as the counter electrodes included in the display elements are integrally formed across the entire surface of the display area DA, the counter electrodes included in the display elements may be electrically connected to each other. The same electrical signal may be supplied to the display elements through the counter electrodes that are integrally formed. For example, the same electrode power voltage ELVSS may be supplied to the display element through the counter electrodes that are integrally formed. Accordingly, the counter electrodes that are integrally formed may serve as a wiring for supplying the electrode power voltage ELVSS to the display elements.
When the layers commonly provided in the intermediate layers included in the display elements are cut off or separated from each other by using the separator SP, the counter electrodes included in the display elements may be cut off or separated from each other. Accordingly, the counter electrodes included in the display elements may not be electrically connected to each other.
However, the display apparatus 1 according to one or more embodiments may include the connection electrode CNE that is electrically connected to the first counter electrode 230-1 and the second counter electrode 230-2. In other words, as the counter electrodes included in the display elements are electrically connected to the connection electrode CNE, the counter electrodes included in the display elements may be electrically connected to each other. Accordingly, in the case of the display apparatus 1 according to one or more embodiments, even when the layers commonly provided in the intermediate layers included in the display elements are cut off or separated from each other by using the separator SP, the counter electrodes included in the display elements may be electrically connected to each other. Accordingly, the electrical signals may be effectively transmitted to the counter electrodes.
Furthermore, in the case of the display apparatus 1 according to one or more embodiments, the connection electrode CNE may surround the counter electrodes. For example, while located on the pixel defining layer 215, the connection electrode CNE may surround, on a plane, a plurality of openings included in the pixel defining layer 215. The counter electrodes may be located in the openings. The counter electrodes may be located not only in the openings, but also on the pixel defining layer 215 and the connection electrode CNE. For example, a plurality of holes included in the connection electrode CNE having a mesh structure, for example, the first connection electrode hole CNEH1, the second connection electrode hole CNEH2, and the third connection electrode hole CNEH3 may be filled by a plurality of counter electrodes, for example, the first counter electrode 230-1, the second counter electrode 230-2, and the third counter electrode 230-3. This may have the same effect as in the case in which the counter electrodes included in the display elements are not cut off or separated from each other. Accordingly, the electrical signals may be effectively transmitted to the counter electrodes.
As the organic light-emitting diode OLEDS may be easily damaged by external moisture, oxygen, or the like, the organic light-emitting diode OLEDS may be protected by covering the organic light-emitting diode OLEDS with an encapsulation layer. The encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer, and cover the display area DA and extend to the outside of the display area DA.
As described above, according to one or more embodiments described as above, a display apparatus may be implemented which may reduce a leakage current and also relatively effectively transmit electrical signals to a plurality of counter electrodes. The scope of embodiments according to the present disclosure is not limited by the effect.
It should be understood that embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments. While one or more embodiments have been described with reference to the figures, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims, and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0077807 | Jun 2022 | KR | national |
