Patent Application
20240212624
The present disclosure relates to, but is not limited to, the field of display technology, and more particularly, to a display apparatus.
An Organic Light Emitting Diode (OLED for short) and a Quantum dot Light Emitting Diode (QLED for short) are active light emitting display apparatuses and have advantages of self-luminescence, a wide viewing angle, a high contrast ratio, low power consumption, an extremely high response speed, lightness and thinness, flexibility, and a low cost, etc. With constant development of display technologies, a flexible display that uses an OLED or a QLED as a light emitting device and performs signal control by a Thin Film Transistor (TFT for short) has become a mainstream product in the field of display at present.
The following is a summary of subject matters described herein in detail. The summary is not intended to limit the protection scope of claims.
In a first aspect, the present disclosure provides a display apparatus including a display panel, a timing controller, a source driver, and a gate driver; the display panel includes: a first boundary and a second boundary which are oppositely disposed and a third boundary and a fourth boundary which are oppositely disposed, the gate driver is located on a side of the first boundary away from the second boundary and/or on a side of the second boundary away from the first boundary, the source driver is located on a side of the third boundary away from the fourth boundary or on a side of the fourth boundary away from the third boundary, the display apparatus is divided into a first region and a second region along a centerline of the display apparatus, and the centerline of the display apparatus extends in a same direction as the extension of the first boundary and intersects the extension of the third boundary;
In some possible implementations, it further includes at least one printed circuit board and multiple flexible circuit boards, wherein the source driver is located on the flexible circuit board or the display panel;
In some possible implementations, the first timing connector is further configured to transmit a third signal, which includes a second power supply signal configured to supply power to the display panel.
In some possible implementations, the second timing connector is further configured to transmit a fourth signal, which includes a clock embedded differential signal protocol.
In some possible implementations, when the quantity of gate drivers is one, the gate driver is located in the first region or the second region; and
In some possible implementations, when the quantity of gate drivers is two, the two gate drivers are respectively located in the first region and the second region; and
In some possible implementations, the quantity of the first timing connector and the second timing connector are both one; and
In some possible implementations, the quantity of the printed circuit boards is one, and the printed circuit boards is substantially symmetrical along a centerline of the display apparatus;
In some possible implementations, the quantity of the first timing connectors and the second timing connectors are both two;
In some possible implementations, the quantity of the printed circuit boards is two, the two printed circuit boards are substantially symmetrical along a centerline of the display apparatus, and the two printed circuit boards are respectively a first printed circuit board and a second printed circuit board; at least one printed circuit board includes a first circuit connector and a second circuit connector;
In some possible implementations, for a first timing connector and a second timing connector located in a same region, when the amount of data that may be transmitted by the second timing connector is less than a sum of the amount of data of a second signal and the amount of data of a fourth signal, the second timing connector is configured to transmit a first signal segment, and the first timing connector is configured to transmit a second signal segment; and the second signal includes a first signal segment and a second signal segment, the data amount of the first signal segment is smaller than the data amount of the second signal segment.
In some possible implementations, the display panel includes multiple sub-pixels, wherein at least one sub-pixel includes a drive circuit including a drive transistor;
In some possible implementations, the timing controller further includes a third timing connector, which is disposed between the first timing connector and the second timing connector;
In some possible implementations, the quantity of the first timing connector, the second timing connector, and the third timing connector is each two;
In some possible implementations, the second printed circuit board and the third printed circuit board further include a fourth circuit connector and a fifth circuit connector; the fourth circuit connector is located on a side of the fifth circuit connector away from a centerline of the display apparatus;
In some possible implementations, the first timing connector is further configured to transmit a fourth signal and a sixth signal, wherein the sixth signal includes a third power supply signal.
In some possible implementations, the timing controller further includes a fourth timing connector configured to transmit a fourth signal and a sixth signal, wherein the sixth signal includes a third power supply signal.
In some possible implementations, the quantity of the first timing connector, the second timing connector, the third timing connector, and the fourth timing connector is each two;
In some possible implementations, the quantity of the printed circuit boards is four, and the four printed circuit boards are respectively a first printed circuit board, a second printed circuit board, a third printed circuit board, and a fourth printed circuit board;
In some possible implementations, for at least one printed circuit board, the printed circuit board further includes a third circuit connector;
In some possible implementations, the third circuit connector is configured to transmit a fifth signal.
In some possible implementations, the third timing connector is further configured to transmit a third signal.
Other aspects may be understood upon reading and understanding the drawings and the detailed description.
The accompanying drawings are used for providing understanding of technical solutions of the present disclosure, and form a part of the specification. They are used for explaining the technical solutions of the present disclosure together with the implementations of the present disclosure, but do not form a limitation on the technical solutions of the present disclosure.
To make objectives, technical solutions, and advantages of the present disclosure clearer, the implementations of the present disclosure will be described in detail with reference to the accompanying drawings. It is to be noted that implementation modes may be implemented in multiple different forms. Those of ordinary skills in the art may easily understand such a fact that implementations and contents may be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be explained as being limited to contents described in following implementation modes only. The implementations in the present disclosure and features in the implementations may be combined randomly with each other without conflict. In order to keep following description of the implementations of the present disclosure clear and concise, detailed descriptions about part of known functions and known components are omitted in the present disclosure. The drawings of the implementations of the present disclosure only involve structures involved in the implementations of the present disclosure, and other structures may refer to usual designs.
In the drawings, a size of each constituent element, a thickness of a layer, or a region is exaggerated sometimes for clarity. Therefore, one mode of the present disclosure is not necessarily limited to the size, and shapes and sizes of various components in the drawings do not reflect actual scales. In addition, the drawings schematically illustrate ideal examples, and one implementation of the present disclosure is not limited to the shapes, numerical values, or the like shown in the drawings.
The ordinal numbers “first”, “second”, “third” and the like in this specification are used to avoid confusion between constituent elements, but not to constitute limitations on quantities.
In the specification, for convenience, wordings indicating directional or positional relationships, such as “middle”, “upper”, “lower”, “front”, “back”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, and “outside”, are used for illustrating positional relationships between constituent elements with reference to the drawings, and are merely for facilitating the description of the specification and simplifying the description, rather than indicating or implying that a referred apparatus or element must have a particular orientation and be constructed and operated in the particular orientation. Therefore, they cannot be understood as limitations on the present disclosure. The positional relationships between the constituent elements may be changed as appropriate according to directions for describing the constituent elements. Therefore, appropriate replacements may be made according to situations without being limited to the wordings described in the specification.
In the specification, unless otherwise specified and defined explicitly, terms “mount”, “mutually connect”, and “connect” should be understood in a broad sense. For example, a connection may be a fixed connection, or a detachable connection, or an integrated connection. It may be a mechanical connection or an electrical connection. It may be a direct mutual connection, or an indirect connection through middleware, or internal communication between two components. Those of ordinary skill in the art may understand specific meanings of these terms in the present disclosure according to specific situations.
In the specification, a transistor refers to a component which at least includes three terminals, i.e., a gate electrode, a drain electrode and a source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain) and the source electrode (source electrode terminal, source region, or source), and a current may flow through the drain electrode, the channel region, and the source electrode. It is to be noted that, in the specification, the channel region refers to a region through which the current mainly flows.
In the specification, a first electrode may be the drain electrode, and a second electrode may be the source electrode. Or, the first electrode may be the source electrode, and the second electrode may be the drain electrode. In cases that transistors with opposite polarities are used, a current direction changes during operation of a circuit, or the like, functions of the “source electrode” and the “drain electrode” are sometimes interchangeable. Therefore, the “source electrode” and the “drain electrode” are interchanged in the specification.
In the specification, “electrical connection” includes a case that constituent elements are connected together through an element with a certain electrical effect. The “element with the certain electrical effect” is not particularly limited as long as electrical signals may be sent and received between the connected constituent elements. Examples of the “element with the certain electrical effect” not only include electrodes and wirings, but also include switch elements such as transistors, resistors, inductors, capacitors, other elements with various functions, etc.
In the specification, “parallel” refers to a state in which an angle formed by two straight lines is above −10° and below 10°, and thus also includes a state in which the angle is above −5° and below 5°. In addition, “perpendicular” refers to a state in which an angle formed by two straight lines is above 80° and below 100°, and thus also includes a state in which the angle is above 85° and below 95°.
In the specification, a “film” and a “layer” are interchangeable. For example, a “conductive layer” may be replaced with a “conductive film” sometimes. Similarly, an “insulating film” may be replaced with an “insulating layer” sometimes.
In the present disclosure, “about” refers to that a boundary is defined not so strictly and numerical values within process and measurement error ranges are allowed.
For a display apparatus includes a display panel and a timing controller, the cost of the display apparatus is high due to the unreasonable arrangement of the timing controller.
In an exemplary implementation, a timing controller 200 may include a first timing connector TCN1 and a second timing connector TCN2. The first timing connector TCN1, the second timing connector TCN2 and the gate driver 400 are located in a same region, and the first timing connector TCN1 is located on a side of the second timing connector TCN2 close to the gate driver 400.
In an exemplary implementation, a first timing connector TCN1 may be configured to transmit a first signal S1. The first signal S1 may include a first power supply signal which may be configured to supply power to a gate driver and a first control signal which may be configured to control the gate driver to output a scan signal.
In an exemplary implementation, a second timing connector TCN2 is configured to transmit a second signal S2. Wherein, the second signal includes a second control signal configured to control a source driver to output a data signal.
In one exemplary implementation, the display apparatus may be, for example, a mobile terminal, television, monitor, laptop, digital photo frame, navigator, electronic paper, or any other product or component with a display function.
In an exemplary implementation, in a display phase, a timing controller 200 generates a first data signal DATA, a source control signal SCS, and a gate control signal GCS through a compensation algorithm based on externally inputted multicolor data (e.g. RGB data), a timing control signal, and a received sense data signal.
In an exemplary implementation, a timing controller may provide signals to a source driver through a mini low voltage differential signal interface.
In an exemplary implementation, a first control signal is a gate control signal and a second control signal is a source control signal.
In an exemplary implementation, a first control signal may include a Start Vertical (STV) of a gate, a Clock Pulse Vertical (CPV) of the gate, and an Output Enable (OE) of the gate.
In an exemplary implementation, a second control signal may include a source start pulse, a source shift clock, and a source output enable signal.
In an exemplary implementation, a timing controller 200 transmits a first data signal DATA and a source control signal SCS to a source driver 300 and a gate control signal GCS to a gate driver 400.
In an exemplary implementation as shown in
In an exemplary implementation, a first data signal DATA may carry a control command and at least one display data signal.
In an exemplary implementation, a second control signal may include a first data signal DATA.
In an exemplary implementation, a source driver 300 is further configured to convert each display data signal into a data voltage signal (i.e., a gray scale signal) and transmit the converted data voltage signal to a corresponding data line DL.
In an exemplary implementation, a source driver 300 is further configured to simultaneously transmit a reference clock signal ACLK and a sense data signal ADATA to a timing controller 200 under the control of the control command carried by a first data signal DATA1, so that the timing controller 200 receives the sense data signal ADATA under the control of the reference clock signal ACLK. For example, the timing controller may receive the sense data signal ADATA on a rising edge or a falling edge of the reference clock signal ACLK. Wherein, the sense data signal ADATA is obtained by analog-to-digital conversion of the analog voltage signal from the sense line SL by the source driver 300.
In an exemplary implementation, a sense data signal ADATA may reflect an optical characteristic (e.g. an start voltage of an OLED) or an electrical characteristic (e.g. a threshold voltage of a drive transistor) of a sub-pixel in the display panel.
In an exemplary implementation, a source driver 300 is further configured to generate a reference clock signal based on a clock frequency of the reference clock signal. For example, the first data signal DATA may carry the clock frequency of the reference clock signal.
In an exemplary implementation, a source driver 300 is further configured to receive a base clock signal transmitted by a timing controller 200; the clock frequency of the reference clock signal may be determined according to the base clock signal. The clock frequency of the base clock signal is the clock frequency of the reference clock signal.
In an exemplary implementation, a base clock signal may be a TTL (transistor-transistor-logic) signal or a differential signal.
In an exemplary implementation, the source driver 300 receives a first data signal carrying control command, and under the control of the control command, the source driver 300 simultaneously transmits the reference clock signal and the sense data signal to the timing controller. In this manner, the timing controller 200 can receive the sense data signal in time under the control of the reference clock signal, thereby improving the accuracy of the sense data signal received by the timing controller 200.
In an exemplary implementation, the timing controller 200 may differentially transmit the first data signal DATA to the source driver 300.
In an exemplary implementation, the source driver 300 may differentially transmit the reference clock signal ACLK and the sense data signal ADATA to the timing controller 200. Transmitting signals in a differential manner can improve the speed of signal transmission and the accuracy of the sense data signal received by the timing controller.
In an exemplary implementation, the source driver 300 may include a data parser, a clock generator, and an analog-to-digital converter. The data parser is configured to parse the control command from the first data signal DATA and transmit the control command to the clock signal generator and the analog-to-digital converter. The clock signal generator is configured to generate a reference clock signal according to a clock frequency of the reference clock signal and to transmit the reference clock signal to a timing controller under control of a control command.
In an exemplary implementation, the data parser is further configured to parse at least one display data signal DATA from the first data signal DATA1. The digital-to-analog converter is configured to convert at least one display data signal DATA into an analog voltage signal under the control of a source control signal transmitted by a timing controller, and to transmit the converted analog voltage signal to a corresponding data line DL. For example, at least one display data signal DATA includes 10 display data signals DATA. After each display data signal DATA is converted into an analog voltage signal, the converted analog voltage signals are respectively transmitted to corresponding data lines DL, such as DL1, DL2 . . . DL10.
In an exemplary implementation, a source driver 300 is further configured to receive a base clock signal transmitted by a timing controller, and the clock signal generator may determine the clock frequency of the reference clock signal based on the base clock signal
In an exemplary implementation, an analog-to-digital converter is configured to convert an analog voltage signal from a sense line into a sense data signal ADATA (digital signal) and to transmit the sense data signal ADATA to a timing controller under control of a control command.
In an exemplary implementation, the clock signal generator transmits the reference clock signal to the timing controller at the same time as the analog-to-digital converter transmits the sense data signal ADATA to the timing controller. For example, the control command carries the signal transmission trigger time, and the clock signal generator starts timing after receiving the control command, and transmits the reference clock signal to the timing controller when the timing reaches the signal transmission trigger time. Similarly, the analog-to-digital converter starts timing after receiving the control command CM, and transmits the sense data signal ADATA to the timing controller when the timing reaches the signal transmission trigger time.
In an exemplary implementation, the display panel may be an OLED display panel or a QLED display panel, and the present disclosure does not limit this in any way.
The display apparatus provided by the implementation of the present disclosure includes a display panel, a timing controller, a source driver and a gate driver; the display panel includes: a first boundary and a second boundary which are oppositely disposed and a third boundary and a fourth boundary which are oppositely disposed, the gate driver is located on a side of the first boundary away from the second boundary and/or on a side of the second boundary away from the first boundary, the source driver is located on a side of the third boundary away from the fourth boundary or on a side of the fourth boundary away from the third boundary, the display apparatus is divided into a first region and a second region along a centerline of the display apparatus, and the centerline of the display apparatus extends in a same direction as the extension of the first boundary and intersects the extension of the third boundary. The timing controller includes a first timing connector and a second timing connector, wherein the first timing connector, the second timing connector and the gate driver are located in the same region, and the first timing connector is located on a side of the second timing connector close to the gate driver. The first timing connector is configured to transmit a first signal, the second timing connector is configured to transmit a second signal. The first signal includes: a first power supply signal and a first control signal, wherein the first power supply signal is configured to supply power to the gate driver, and the first control signal is configured to control the gate driver to output a scan signal. The second signal includes a second control signal, which is configured to control the source driver to output a data signal. A connector for supplying a signal to a gate driver in a timing controller in a display apparatus provided by an implementation of the present disclosure is close to the gate drive and a connector for supplying a signal to a source driver is close to the source driver. A first timing connector, a second timing connector and the gate driver are located in the same region, thereby optimizing the layout of the connector of the timing controller and saving the cost of the timing controller and the display apparatus.
In an exemplary implementation, as shown in
In an exemplary implementation, a light emitting device may be an OLED device or a QLED device.
In an exemplary implementation, the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3 and the fourth sub-pixel P4 all include a pixel drive circuit and a light emitting device. The pixel drive circuit in the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3 and the fourth sub-pixel P4 are respectively connected to the gate line and the data line. The pixel drive circuit is configured to, under the control of the gate line, receive the data voltage transmitted by the data line, and output a corresponding current to the light emitting device.
In an exemplary implementation, the light emitting devices in the first sub-pixel P1, the second sub-pixel P2, the third sub-pixel P3, and the fourth sub-pixel P4 are respectively connected to the pixel drive circuits of the sub-pixels where the light emitting devices are located. The light emitting device is configured to emit light with a corresponding brightness in response to a current output by the pixel drive circuit of the sub-pixel where the light emitting device is located.
In an exemplary implementation, a pixel unit P may include a Red (R) sub-pixel, a Green (G) sub-pixel, and a Blue (B) sub-pixel, or may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, which is not limited in the present disclosure. In an exemplary implementation, the sub-pixels in the pixel unit may be rectangular, rhombic, pentagonal or hexagonal in shape. When the pixel unit includes three sub-pixels, the three sub-pixels may be arranged side by side horizontally, side by side vertically, or in a form of delta, and when the pixel unit includes four sub-pixels, the four sub-pixels may be arranged side by side horizontally, side by side vertically, or in a shape of a square, which is not limited in the present disclosure.
In an exemplary implementation, the first transistor T1 is a switch transistor, the second transistor T2 is a drive transistor, and the third transistor T3 is a sense transistor. A gate electrode of the first transistor T1 is coupled to a first gate line GL1, a first electrode of the first transistor T1 is coupled to a data line DL, and a second electrode of the first transistor T1 is coupled to a gate electrode of the second transistor T2. The first transistor T1 is used for receiving the data signal transmitted by the data line DL under the control of the first gate line Gn, so that the gate electrode of the second transistor T2 receives the data signal. The gate electrode of the second transistor T2 is coupled to the second electrode of the first transistor T1, a first electrode of the second transistor T2 is coupled to the first power supply line VDD, a second electrode of the second transistor T2 is coupled to a first electrode of an OLED, and the second transistor T2 is configured to generate a corresponding current at the second electrode under the control of the data signal received by the gate electrode of the second transistor. A gate electrode of the third transistor T3 is coupled to the second gate line GL2, a first electrode of the third transistor T3 is connected to the sense line SL, a second electrode of the third transistor T3 is coupled to the second electrode of the second transistor T2. The third transistor T3 is configured to extract a threshold voltage Vth and the mobility of the second transistor T2 in response to compensation timing to compensate the threshold voltage Vth. The first electrode of the OLED is coupled to the second electrode of the second transistor T2, a second electrode of the OLED is coupled to the second power supply line VSS, and the OLED is configured to emit light with corresponding brightness in response to the current of the second electrode of the second transistor T2. A first electrode of the storage capacitor CST is coupled to the gate electrode of the second transistor T2, a second electrode of the storage capacitor CST is coupled to the second electrode of the second transistor T2, and the storage capacitor CST is configured to store a potential of the gate electrode of the second transistor T2.
In an exemplary implementation, a signal of the first power supply line VDD is a high-level signal continuously provided, and a signal of the second power supply line VSS is a low-level signal. The first transistor T1 to the third transistor T3 may be P-type transistors or may be N-type transistors. Use of a same type of transistors in a pixel drive circuit may simplify a process flow, reduce process difficulties of a display panel, and improve a product yield.
In an exemplary implementation, the first transistor T1 to the third transistors T3 may adopt low temperature polysilicon thin film transistors, or oxide thin film transistors, or low temperature polysilicon thin film transistors and oxide thin film transistors. An active layer of a low temperature poly silicon thin film transistor is made of Low Temperature Poly Silicon (LTPS for short), and an active layer of an oxide thin film transistor is made of an oxide. The low temperature poly silicon thin film transistor has advantages of a high mobility, fast charging, and the like, and the oxide thin film transistor has advantages of a low leakage current and the like. In an exemplary implementation, a low temperature poly silicon thin film transistor and an oxide thin film transistor may be integrated on one display panel to form a Low Temperature Polycrystalline Oxide (LTPO for short) display panel, so that advantages of the two may be utilized, high Pixel Per Inch (PPI for short) and low-frequency drive may be achieved, power consumption may be reduced, and display quality may be improved.
In an exemplary implementation, the light emitting device may be an Organic light emitting Diode (OLED), including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) that are stacked.
In an exemplary implementation, the base substrate 101 may be a flexible base substrate, or may be a rigid base substrate. A drive circuit layer 102 of each sub-pixel may include multiple transistors and a storage capacitor that form a pixel drive circuit.
In an exemplary implementation, the organic emitting layer may include a Hole Injection Layer (HIL for short), a Hole Transport Layer (HTL for short), an Electron Block Layer (EBL for short), an Emitting Layer (EML for short), a Hole Block Layer (HBL for short), an Electron Transport Layer (ETL for short), and an Electron Injection Layer (EIL for short) that are stacked. In an exemplary implementation, hole injection layers of all sub pixels may be connected together to form a common layer, electron injection layers of all the sub pixels may be connected together to form a common layer, hole transport layers of all the sub pixels may be connected together to form a common layer, electron transport layers of all the sub pixels may be connected together to form a common layer, hole block layers of all the sub pixels may be connected together to form a common layer, emitting layers of adjacent sub pixels may be overlapped slightly, or may be isolated from each other, and electron block layers of adjacent sub pixels may be overlapped slightly, or may be isolated from each other.
In an exemplary implementation, the printed circuit board 500 may be located between the flexible circuit board 600 and the timing controller 200 and is connected to the timing controller 200 and at least one flexible circuit board 600.
In an exemplary implementation, the flexible circuit board 600 may be located between the printed circuit board 500 and the display panel 100 and is connected to the display panel 100.
In an exemplary implementation, as shown in
In an exemplary implementation, the second power signal supplies power to a first power line and a second power line in the display panel.
In an exemplary implementation, the third signal S3 and the first signal S1 are transmitted by the first timing connector TCN1, which can reduce the quantity of connectors in the timing controller and reduce the cost of the display apparatus.
In an exemplary implementation, as shown in
In an exemplary implementation, the fourth signal S4 and a second signal S2 are transmitted by the second timing connector TCN2, which can reduce the quantity of connectors in the timing controller and reduce the cost of the display apparatus.
In an exemplary implementation, a clock embedded differential signal protocol may transmit clock embedded differential image data. Clock embedded differential signal protocol can include three components: clock training, configuration and RGB data transmission.
In an exemplary implementation, as shown in
In an exemplary implementation, as shown in
In an exemplary implementation, structure A includes two integrally formed structural components, and structure A is substantially symmetrical along a centerline L of the display apparatus, meaning that the two structural components are separately located on both sides of the centerline L of the display apparatus, and the areas of the two structural components may be the same or may be different. When the areas of the two structural component parts of the structure A are different, the difference in the areas of the structural component parts located on both sides of the centerline L of the display apparatus is smaller than the threshold area difference value. The threshold area difference is determined according to the size and structure of the display apparatus.
In an exemplary implementation, as shown in
In an exemplary implementation, as shown in
In an exemplary implementation, as shown in
In an exemplary implementation, the first circuit connector PCN1 may be located on a side of the second circuit connector PCN2 close to the gate driver.
In an exemplary implementation, the first circuit connector PCN1 and the second circuit connector PCN2 are located on a side of the printed circuit board 500 close to the timing controller 200.
In an exemplary implementation, the timing controller in the display apparatus shown in
In an exemplary implementation, as shown in
In an exemplary implementation, the first timing connector TCN1 and the second timing connector TCN2 may be located on a side of the timing controller 200 close to the display panel 100.
In an exemplary implementation, the substantially symmetrical structure B and structure C along the centerline L of the display apparatus means that the distance between structure B and the centerline L and the distance between structure C and the centerline L may be the same or may be different. When the distance between structure B and the centerline L is different from the distance between structure C and the centerline L, the difference between the distance between structure B and the centerline L and the distance between structure C and the centerline L is less than a threshold difference value, wherein the threshold difference value is determined according to the size and the structure of the display apparatus.
In an exemplary implementation, as shown in
In an exemplary implementation, for at least one printed circuit board, the first circuit connector PCN1 is located on a side of the second circuit connector PCN2 away from a centerline L of the display apparatus, and the first circuit connector PCN1 and the second circuit connector PCN2 are located on a side of the printed circuit board close to the timing controller 200.
In an exemplary implementation, as shown in
In an exemplary implementation, as shown in
In an exemplary implementation, as shown in
In an exemplary implementation, as shown in
In an exemplary implementation, the timing controller in the display apparatus shown in
In an exemplary implementation, as shown in
In an exemplary implementation, as shown in
In an exemplary implementation, as shown in
In an exemplary implementation, as shown in
In one exemplary implementation, the quantity of printed circuit boards is four, and the four printed circuit boards are respectively a first printed circuit board 500A, a second printed circuit board 500B, a third printed circuit board 500C, and a fourth printed circuit board 500D.
In an exemplary implementation, as shown in
In an exemplary implementation, as shown in
In an exemplary implementation, as shown in
In an exemplary implementation, as shown in
In an exemplary implementation, the second printed circuit board 500B and the third printed circuit board 500C further include a fourth circuit connector PCN4 and a fifth circuit connector PCN5; the fourth circuit connector PCN4 is located on a side of the fifth circuit connector PCN5 away from the centerline L of the display apparatus.
In an exemplary implementation, for the second printed circuit board 500B and the third printed circuit board 500C, the fourth circuit connector PCN4 transmits the same signal as the third circuit connector PCN3, and the fifth circuit connector PCN5 transmits the same signal as the first circuit connector PCN1.
In an exemplary implementation, as shown in
In an exemplary implementation, as shown in
In an exemplary implementation, as shown in
In an exemplary implementation, a first circuit connector PCN1 of the first printed circuit board 500A is connected to a fifth circuit connector PCN5 of the second printed circuit board 500B, a second circuit connector PCN2 of the first printed circuit board 500A is connected to a fourth circuit connector PCN4 of the second printed circuit board 500B, a first circuit connector PCN1 of the fourth printed circuit board 500D is connected to a fifth circuit connector PCN5 of the third printed circuit board 500B, and a second circuit connector PCN2 of the fourth printed circuit board 500D is connected to a fourth circuit connector PCN4 of the third printed circuit board 500C, In this way, the quantity of connectors of the timing controller and the cost of the display apparatus can be reduced.
In an exemplary implementation, the first timing connector TCN1 is further configured to transmit a fourth signal and a sixth signal S6, wherein the sixth signal S6 includes a third power supply signal.
In an exemplary implementation, the timing controller in the display apparatus shown in
In an exemplary implementation, as shown in
In an exemplary implementation, as shown in
In an exemplary implementation, as shown in
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In an exemplary implementation, the third circuit connector PCN3 of the first printed circuit board 500A is connected to the third circuit connector PCN3 of the second printed circuit board 500B, and the third circuit connector PCN3 of the third printed circuit board 500C is connected to the third circuit connector PCN3 of the fourth printed circuit board 500D. In this way, the quantity of connectors of the timing controller and the cost of the display apparatus can be reduced.
In an exemplary implementation, as shown in
In an exemplary implementation, as shown in
In an exemplary implementation, the timing controller in the display apparatus shown in
The accompanying drawings of the present disclosure only involve the structures involved in the implementations of the present disclosure, and other structures may refer to usual designs.
For the sake of clarity, in the accompanying drawings used for describing the implementations of the present disclosure, a thickness and dimension of a layer or a micro structure is enlarged. It may be understood that when an element such as a layer, a film, a region, or a substrate is described as being “on” or “under” another element, the element may be “directly” located “on” or “under” the other element, or there may be an intermediate element.
Although the implementations disclosed in the present disclosure are as above, the described contents are only implementations used for convenience of understanding the present disclosure and are not intended to limit the present disclosure. Any person skilled in the art to which the present disclosure pertains may make any modification and variation in implementation forms and details without departing from the spirit and scope disclosed in the present disclosure. However, the scope of patent protection of the present disclosure is still subject to the scope defined by the appended claims.
The present application is a U.S. National Phase Entry of International PCT Application No. PCT/CN2021/134130, having an international filing date of Nov. 29, 2021, the entire content of which is hereby incorporated by reference.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2021/134130 | 11/29/2021 | WO |
