Patent Grant
9378686
This disclosure relates to the field of imaging displays, and in particular to pixel circuits for display elements.
Electromechanical systems (EMS) include devices having electrical and mechanical elements, actuators, transducers, sensors, optical components such as mirrors and optical films, and electronics. EMS devices or elements can be manufactured at a variety of scales including, but not limited to, microscales and nanoscales. For example, microelectromechanical systems (MEMS) devices can include structures having sizes ranging from about a micron to hundreds of microns or more. Nanoelectromechanical systems (NEMS) devices can include structures having sizes smaller than a micron including, for example, sizes smaller than several hundred nanometers. Electromechanical elements may be created using deposition, etching, lithography, and/or other micromachining processes that etch away parts of substrates and/or deposited material layers, or that add layers to form electrical and electromechanical devices.
In some implementations, display devices can include electromechanical elements for displaying images. For example, some display devices can include an array of electromechanical (MEMS or NEMS) light modulators for manipulating light emitted by a backlight before the light reaches a viewer. In some implementations, the array of light modulators can selectively manipulate the light by blocking, allowing, or partially allowing the light from reaching the viewer. The operation of the light modulators can be controlled using pixel circuitry coupled to the array of light modulators. The pixel circuitry can control the array of light modulators based on image frame data.
The systems, methods and devices of the disclosure each have several innovative aspects, no single one of which is solely responsible for the desirable attributes disclosed herein.
One innovative aspect of the subject matter described in this disclosure can be implemented in an apparatus including a data loading circuit capable of accepting a data voltage, a light modulator capable of selectively allowing passage of light, an actuation circuit having an input node and an output node, the input node coupled to the data loading circuit and the output node coupled to the light modulator, capable of providing an actuation voltage to the light modulator based on the data voltage, and a positive feedback circuit capable of providing a positive feedback voltage from the output node to the input node.
In some implementations, the positive feedback circuit includes a data storing capacitor coupled between the input node and the output node, where the data storing capacitor is capable of storing the data voltage. In some implementations, the data storing capacitor is a floating capacitor. In some implementations, the feedback circuit includes a switch capable of providing an actuation voltage to the input node in response to the output node being charged to the actuation voltage via the actuation circuit.
In some implementations, the light modulator includes a shutter terminal, a first actuator terminal and a second actuator terminal, where the output node is coupled to one of the first actuator terminal and the second actuator terminal. In some implementations, a voltage at the shutter terminal is toggled such that a previous state of the light modulator is preserved when the output node is discharged by the actuation circuit. In some implementations, the light modulator includes a shutter terminal, a first actuator terminal and a second actuator terminal, where the output node is coupled to the shutter terminal.
In some implementations, the voltages at the first actuator terminal and the second actuator terminal are switched from being complementary to being non-complementary such that a previous state of the light modulator is preserved when the output node is discharged by the actuation circuit. In some implementations, a period of a state of the light modulator is a function of the magnitude of the data voltage. In some implementations, the display device uses analog grayscale technique for displaying an image.
In some implementations, the apparatus includes a display including an array of the display elements, and a corresponding array of the circuits, a processor that is capable of communicating with the display, the processor being capable of processing image data and a memory device that is capable of communicating with the processor.
In some implementations, the display further includes a driver circuit capable of sending at least one signal to the display and a controller capable of sending at least a portion of the image data to the driver circuit. In some implementations, the apparatus further includes an image source module capable of sending the image data to the processor, where the image source module includes at least one of a receiver, transceiver, and transmitter. In some implementations, the apparatus further includes an input device capable of receiving input data and to communicate the input data to the processor.
Another innovative aspect of the subject matter described in this disclosure can be implemented in a method including accepting a data voltage from a data interconnect, discharging an output node of an actuation circuit, where the output node is coupled to a light modulator capable of switching between two discrete states, charging the output node to an actuation voltage via the actuation circuit based on the data voltage, and providing a positive feedback voltage from the output node to an input node of the actuation circuit.
In some implementations, accepting the data voltage from a data interconnect includes storing the data voltage into a data storing capacitor. In some implementations, accepting the data voltage from the data interconnect includes accepting the data voltage from the data interconnect concurrently with discharging the output node of the actuation circuit. In some implementations, providing the positive feedback voltage from the output node to the input node of the actuation circuit includes charging the input node in response to a charging of the output node via the actuation circuit.
In some implementations, charging the input node in response to a charging of the output node via the actuation circuit includes charging the input node via a switch. In some implementations, charging the input node in response to a charging of the output node via the actuation circuit includes charging the input node via the data storing capacitor to a voltage that is greater than the voltage at the output node by the magnitude of the data voltage.
In some implementations, the method further includes providing a voltage at the output node to one of at least two actuators of the light modulator. In some such implementations, the method further includes toggling a voltage at the shutter terminal during discharging the output node of the actuation circuit such that a previous state of the light modulator is preserved.
In some implementations, the method further includes providing a voltage at the output node to a shutter terminal of the light modulator. In some such implementations, the method includes switching the voltages at the first actuator terminal and the second actuator terminal from being complementary to being non-complementary during discharging the output node.
In some implementations, charging the output node to an actuation voltage via the actuation circuit based on the data voltage includes charging the output node at a rate that is a function of the magnitude of the data voltage. In some such implementations, the method includes displaying an image using analog grayscale technique.
Another innovative aspect of the subject matter described in this disclosure can be implemented in an apparatus including a circuit for controlling a display element, including data acquiring means for accepting a data voltage from a data interconnect, discharging means for discharging an output node of an actuation circuit, the output node coupled to a light modulator, charging means for charging the output node to an actuation voltage via the actuation circuit based on the data voltage and feedback means providing a positive feedback voltage from the output node to an input node of the actuation circuit.
In some implementations, the data acquiring means are capable of storing the data voltage on a data storing capacitor. In some implementations, the feedback means are capable of charging the input node in response to a charging of the output node via the charging means. In some implementations, the feedback means includes a floating data storing capacitor coupled between the input node and the output node, the floating data storing capacitor capable of storing the data voltage.
Details of one or more implementations of the subject matter described in this disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages will become apparent from the description, the drawings and the claims. Note that the relative dimensions of the following figures may not be drawn to scale.
Like reference numbers and designations in the various drawings indicate like elements.
The following description is directed to certain implementations for the purposes of describing the innovative aspects of this disclosure. However, a person having ordinary skill in the art will readily recognize that the teachings herein can be applied in a multitude of different ways. The described implementations may be implemented in any device, apparatus, or system that is capable of displaying an image, whether in motion (such as video) or stationary (such as still images), and whether textual, graphical or pictorial. The concepts and examples provided in this disclosure may be applicable to a variety of displays, such as liquid crystal displays (LCDs), organic light-emitting diode (OLED) displays, field emission displays, and electromechanical systems (EMS) and microelectromechanical (MEMS)-based displays, in addition to displays incorporating features from one or more display technologies.
The described implementations may be included in or associated with a variety of electronic devices such as, but not limited to: mobile telephones, multimedia Internet enabled cellular telephones, mobile television receivers, wireless devices, smartphones, Bluetooth® devices, personal data assistants (PDAs), wireless electronic mail receivers, hand-held or portable computers, netbooks, notebooks, smartbooks, tablets, printers, copiers, scanners, facsimile devices, global positioning system (GPS) receivers/navigators, cameras, digital media players (such as MP3 players), camcorders, game consoles, wrist watches, wearable devices, clocks, calculators, television monitors, flat panel displays, electronic reading devices (such as e-readers), computer monitors, auto displays (such as odometer and speedometer displays), cockpit controls and/or displays, camera view displays (such as the display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, microwaves, refrigerators, stereo systems, cassette recorders or players, DVD players, CD players, VCRs, radios, portable memory chips, washers, dryers, washer/dryers, parking meters, packaging (such as in electromechanical systems (EMS) applications including microelectromechanical systems (MEMS) applications, in addition to non-EMS applications), aesthetic structures (such as display of images on a piece of jewelry or clothing) and a variety of EMS devices.
The teachings herein also can be used in non-display applications such as, but not limited to, electronic switching devices, radio frequency filters, sensors, accelerometers, gyroscopes, motion-sensing devices, magnetometers, inertial components for consumer electronics, parts of consumer electronics products, varactors, liquid crystal devices, electrophoretic devices, drive schemes, manufacturing processes and electronic test equipment. Thus, the teachings are not intended to be limited to the implementations depicted solely in the Figures, but instead have wide applicability as will be readily apparent to one having ordinary skill in the art.
A display apparatus includes pixel circuits for controlling the state of operation of shutter based light modulators. The state of operation of the light modulator is controlled by the pixel circuit based on a data voltage stored in a data storage element of the pixel circuit. The pixel circuit includes an actuation circuit for providing an actuation voltage to the light modulator and a feedback circuit for providing a positive feedback voltage from an output node of the actuation circuit to an input node of the actuation circuit. In some implementations, the feedback circuit includes the data storage element connected between the input node and the output node.
In some implementations, the output node is connected to one of two actuators of the light modulator. In some such implementations, the voltage on a shutter of the light modulator is toggled during a data loading period of the pixel circuit such that a previous state of the light modulator is preserved during the data loading period. In some implementations, the output node is connected to the shutter of the light modulator. In some implementations, the pixel circuit can operate in an analog mode, in which the period for which the light modulator is maintained in a particular state is based on the magnitude of the data voltage.
Particular implementations of the subject matter described in this disclosure can be implemented to realize one or more of the following potential advantages. By using a positive voltage feedback circuit in conjunction with an actuation circuit, the output voltage at an output of the actuation circuit can be boosted to an actuation voltage without the need for separate pre-charge circuitry. Furthermore, only a relatively low data voltage is needed to boost the output voltage to the actuation voltage. When the actuation circuit is utilized to drive one of the actuators of a light modulator, manipulating the voltage at the shutter of the light modulator allows preserving a previous state of the light modulator while new data is being loaded. This, in turn, allows an increase in an on-time of a light-source used for illuminating the display. A similar increase in the on-time of the light-source can be achieved by manipulating the voltages at the two actuators of the light modulator when the actuation circuit is used to drive the shutter. Additionally, analog mode operation of the pixel circuit allows the use of analog grayscale techniques for displaying images, which can reduce image artifacts.
In some implementations, each light modulator 102 corresponds to a pixel 106 in the image 104. In some other implementations, the display apparatus 100 may utilize a plurality of light modulators to form a pixel 106 in the image 104. For example, the display apparatus 100 may include three color-specific light modulators 102. By selectively opening one or more of the color-specific light modulators 102 corresponding to a particular pixel 106, the display apparatus 100 can generate a color pixel 106 in the image 104. In another example, the display apparatus 100 includes two or more light modulators 102 per pixel 106 to provide a luminance level in an image 104. With respect to an image, a pixel corresponds to the smallest picture element defined by the resolution of image. With respect to structural components of the display apparatus 100, the term pixel refers to the combined mechanical and electrical components utilized to modulate the light that forms a single pixel of the image.
The display apparatus 100 is a direct-view display in that it may not include imaging optics typically found in projection applications. In a projection display, the image formed on the surface of the display apparatus is projected onto a screen or onto a wall. The display apparatus is substantially smaller than the projected image. In a direct view display, the image can be seen by looking directly at the display apparatus, which contains the light modulators and optionally a backlight or front light for enhancing brightness and/or contrast seen on the display.
Direct-view displays may operate in either a transmissive or reflective mode. In a transmissive display, the light modulators filter or selectively block light which originates from a lamp or lamps positioned behind the display. The light from the lamps is optionally injected into a lightguide or backlight so that each pixel can be uniformly illuminated. Transmissive direct-view displays are often built onto transparent substrates to facilitate a sandwich assembly arrangement where one substrate, containing the light modulators, is positioned over the backlight. In some implementations, the transparent substrate can be a glass substrate (sometimes referred to as a glass plate or panel), or a plastic substrate. The glass substrate may be or include, for example, a borosilicate glass, wine glass, fused silica, a soda lime glass, quartz, artificial quartz, Pyrex, or other suitable glass material.
Each light modulator 102 can include a shutter 108 and an aperture 109. To illuminate a pixel 106 in the image 104, the shutter 108 is positioned such that it allows light to pass through the aperture 109. To keep a pixel 106 unlit, the shutter 108 is positioned such that it obstructs the passage of light through the aperture 109. The aperture 109 is defined by an opening patterned through a reflective or light-absorbing material in each light modulator 102.
The display apparatus also includes a control matrix coupled to the substrate and to the light modulators for controlling the movement of the shutters. The control matrix includes a series of electrical interconnects (such as interconnects 110, 112 and 114), including at least one write-enable interconnect 110 (also referred to as a scan line interconnect) per row of pixels, one data interconnect 112 for each column of pixels, and one common interconnect 114 providing a common voltage to all pixels, or at least to pixels from both multiple columns and multiples rows in the display apparatus 100. In response to the application of an appropriate voltage (the write-enabling voltage, VWE), the write-enable interconnect 110 for a given row of pixels prepares the pixels in the row to accept new shutter movement instructions. The data interconnects 112 communicate the new movement instructions in the form of data voltage pulses. The data voltage pulses applied to the data interconnects 112, in some implementations, directly contribute to an electrostatic movement of the shutters. In some other implementations, the data voltage pulses control switches, such as transistors or other non-linear circuit elements that control the application of separate drive voltages, which are typically higher in magnitude than the data voltages, to the light modulators 102. The application of these drive voltages results in the electrostatic driven movement of the shutters 108.
The control matrix also may include, without limitation, circuitry, such as a transistor and a capacitor associated with each shutter assembly. In some implementations, the gate of each transistor can be electrically connected to a scan line interconnect. In some implementations, the source of each transistor can be electrically connected to a corresponding data interconnect. In some implementations, the drain of each transistor may be electrically connected in parallel to an electrode of a corresponding capacitor and to an electrode of a corresponding actuator. In some implementations, the other electrode of the capacitor and the actuator associated with each shutter assembly may be connected to a common or ground potential. In some other implementations, the transistor can be replaced with a semiconducting diode, or a metal-insulator-metal switching element.
The display apparatus 128 includes a plurality of scan drivers 130 (also referred to as write enabling voltage sources), a plurality of data drivers 132 (also referred to as data voltage sources), a controller 134, common drivers 138, lamps 140-146, lamp drivers 148 and an array of display elements 150, such as the light modulators 102 shown in
In some implementations of the display apparatus, the data drivers 132 are capable of providing analog data voltages to the array of display elements 150, especially where the luminance level of the image is to be derived in analog fashion. In analog operation, the display elements are designed such that when a range of intermediate voltages is applied through the data interconnects 133, there results a range of intermediate illumination states or luminance levels in the resulting image. In some other implementations, the data drivers 132 are capable of applying only a reduced set, such as 2, 3 or 4, of digital voltage levels to the data interconnects 133. In implementations in which the display elements are shutter-based light modulators, such as the light modulators 102 shown in
The scan drivers 130 and the data drivers 132 are connected to a digital controller circuit 134 (also referred to as the controller 134). The controller 134 sends data to the data drivers 132 in a mostly serial fashion, organized in sequences, which in some implementations may be predetermined, grouped by rows and by image frames. The data drivers 132 can include series-to-parallel data converters, level-shifting, and for some applications digital-to-analog voltage converters.
The display apparatus optionally includes a set of common drivers 138, also referred to as common voltage sources. In some implementations, the common drivers 138 provide a DC common potential to all display elements within the array 150 of display elements, for instance by supplying voltage to a series of common interconnects 139. In some other implementations, the common drivers 138, following commands from the controller 134, issue voltage pulses or signals to the array of display elements 150, for instance global actuation pulses which are capable of driving and/or initiating simultaneous actuation of all display elements in multiple rows and columns of the array.
Each of the drivers (such as scan drivers 130, data drivers 132 and common drivers 138) for different display functions can be time-synchronized by the controller 134. Timing commands from the controller 134 coordinate the illumination of red, green, blue and white lamps (140, 142, 144 and 146 respectively) via lamp drivers 148, the write-enabling and sequencing of specific rows within the array of display elements 150, the output of voltages from the data drivers 132, and the output of voltages that provide for display element actuation. In some implementations, the lamps are light emitting diodes (LEDs).
The controller 134 determines the sequencing or addressing scheme by which each of the display elements can be re-set to the illumination levels appropriate to a new image 104. New images 104 can be set at periodic intervals. For instance, for video displays, color images or frames of video are refreshed at frequencies ranging from 10 to 300 Hertz (Hz). In some implementations, the setting of an image frame to the array of display elements 150 is synchronized with the illumination of the lamps 140, 142, 144 and 146 such that alternate image frames are illuminated with an alternating series of colors, such as red, green, blue and white. The image frames for each respective color are referred to as color subframes. In this method, referred to as the field sequential color method, if the color subframes are alternated at frequencies in excess of 20 Hz, the human visual system (HVS) will average the alternating frame images into the perception of an image having a broad and continuous range of colors. In some other implementations, the lamps can employ primary colors other than red, green, blue and white. In some implementations, fewer than four, or more than four lamps with primary colors can be employed in the display apparatus 128.
In some implementations, where the display apparatus 128 is designed for the digital switching of shutters, such as the shutters 108 shown in
In some implementations, the data for an image state is loaded by the controller 134 to the array of display elements 150 by a sequential addressing of individual rows, also referred to as scan lines. For each row or scan line in the sequence, the scan driver 130 applies a write-enable voltage to the write enable interconnect 131 for that row of the array of display elements 150, and subsequently the data driver 132 supplies data voltages, corresponding to desired shutter states, for each column in the selected row of the array. This addressing process can repeat until data has been loaded for all rows in the array of display elements 150. In some implementations, the sequence of selected rows for data loading is linear, proceeding from top to bottom in the array of display elements 150. In some other implementations, the sequence of selected rows is pseudo-randomized, in order to mitigate potential visual artifacts. And in some other implementations, the sequencing is organized by blocks, where, for a block, the data for only a certain fraction of the image is loaded to the array of display elements 150. For example, the sequence can be implemented to address only every fifth row of the array of the display elements 150 in sequence.
In some implementations, the addressing process for loading image data to the array of display elements 150 is separated in time from the process of actuating the display elements. In such an implementation, the array of display elements 150 may include data memory elements for each display element, and the control matrix may include a global actuation interconnect for carrying trigger signals, from the common driver 138, to initiate simultaneous actuation of the display elements according to data stored in the memory elements.
In some implementations, the array of display elements 150 and the control matrix that controls the display elements may be arranged in configurations other than rectangular rows and columns. For example, the display elements can be arranged in hexagonal arrays or curvilinear rows and columns.
The host processor 122 generally controls the operations of the host device 120. For example, the host processor 122 may be a general or special purpose processor for controlling a portable electronic device. With respect to the display apparatus 128, included within the host device 120, the host processor 122 outputs image data as well as additional data about the host device 120. Such information may include data from environmental sensors 124, such as ambient light or temperature; information about the host device 120, including, for example, an operating mode of the host or the amount of power remaining in the host device's power source; information about the content of the image data; information about the type of image data; and/or instructions for the display apparatus 128 for use in selecting an imaging mode.
In some implementations, the user input module 126 enables the conveyance of personal preferences of a user to the controller 134, either directly, or via the host processor 122. In some implementations, the user input module 126 is controlled by software in which a user inputs personal preferences, for example, color, contrast, power, brightness, content, and other display settings and parameters preferences. In some other implementations, the user input module 126 is controlled by hardware in which a user inputs personal preferences. In some implementations, the user may input these preferences via voice commands, one or more buttons, switches or dials, or with touch-capability. The plurality of data inputs to the controller 134 direct the controller to provide data to the various drivers 130, 132, 138 and 148 which correspond to optimal imaging characteristics.
The environmental sensor module 124 also can be included as part of the host device 120. The environmental sensor module 124 can be capable of receiving data about the ambient environment, such as temperature and or ambient lighting conditions. The sensor module 124 can be programmed, for example, to distinguish whether the device is operating in an indoor or office environment versus an outdoor environment in bright daylight versus an outdoor environment at nighttime. The sensor module 124 communicates this information to the display controller 134, so that the controller 134 can optimize the viewing conditions in response to the ambient environment.
In the depicted implementation, the shutter 206 includes two shutter apertures 212 through which light can pass. The aperture layer 207 includes a set of three apertures 209. In
Each aperture has at least one edge around its periphery. For example, the rectangular apertures 209 have four edges. In some implementations, in which circular, elliptical, oval, or other curved apertures are formed in the aperture layer 207, each aperture may have only a single edge. In some other implementations, the apertures need not be separated or disjointed in the mathematical sense, but instead can be connected. That is to say, while portions or shaped sections of the aperture may maintain a correspondence to each shutter, several of these sections may be connected such that a single continuous perimeter of the aperture is shared by multiple shutters.
In order to allow light with a variety of exit angles to pass through the apertures 212 and 209 in the open state, the width or size of the shutter apertures 212 can be designed to be larger than a corresponding width or size of apertures 209 in the aperture layer 207. In order to effectively block light from escaping in the closed state, the light blocking portions of the shutter 206 can be designed to overlap the edges of the apertures 209.
The electrostatic actuators 202 and 204 are designed so that their voltage-displacement behavior provides a bi-stable characteristic to the shutter assembly 200. For each of the shutter-open and shutter-close actuators, there exists a range of voltages below the actuation voltage, which if applied while that actuator is in the closed state (with the shutter being either open or closed), will hold the actuator closed and the shutter in position, even after a drive voltage is applied to the opposing actuator. The minimum voltage needed to maintain a shutter's position against such an opposing force is referred to as a maintenance voltage Vm.
Electrical bi-stability in electrostatic actuators, such as actuators 202 and 204, can arise from the fact that the electrostatic force across an actuator is a function of position as well as voltage. The beams of the actuators in the shutter assembly 200 can be implemented to act as capacitor plates. The force between capacitor plates is proportional to 1/d2 where d is the local separation distance between capacitor plates. When the actuator is in a closed state, the local separation between the actuator beams is very small. Thus, the application of a small voltage can result in a relatively strong force between the actuator beams of the actuator in the closed state. As a result, a relatively small voltage, such as Vm, can keep the actuator in the closed state, even if other elements exert an opposing force on the actuator.
In dual-actuator light modulators, the equilibrium position of the light modulator can be determined by the combined effect of the voltage differences across each of the actuators. In other words, the electrical potentials of the three terminals, namely, the shutter open drive beam, the shutter close drive beam, and the load beams, as well as modulator position, can be considered to determine the equilibrium forces on the modulator.
For an electrically bi-stable system, a set of logic rules can describe the stable states and can be used to develop reliable addressing or digital control schemes for a given light modulator. Referring to the shutter assembly 200 as an example, these logic rules are as follows:
Let Vs be the electrical potential on the shutter or load beam. Let Vo be the electrical potential on the shutter-open drive beam. Let Vc be the electrical potential on the shutter-close drive beam. Let the expression |Vo−Vs| refer to the absolute value of the voltage difference between the shutter and the shutter-open drive beam. Let Vm be the maintenance voltage. Let Vat be the actuation threshold voltage, i.e., the voltage to actuate an actuator absent the application of Vm to an opposing drive beam. Let Vmax be the maximum allowable potential for Vo and Vc. Let Vm<Vat<Vmax. Then, assuming Vo and Vc remain below Vmax:
If |Vo−Vs|<Vm and |Vc−Vs|<Vm (rule 1)
Then the shutter will relax to the equilibrium position of its mechanical spring.
If |Vo−Vs|>Vm and |Vc−Vs|>Vm (rule 2)
Then the shutter will not move, i.e., it will hold in either the open or the closed state, whichever position was established by the last actuation event.
If |Vo−Vs|>Vat and |Vc−Vs|<Vm (rule 3)
Then the shutter will move into the open position.
If |Vo−Vs|<Vm and |Vc−Vs|>Vat (rule 4)
Then the shutter will move into the closed position.
Following rule 1, with voltage differences on each actuator near zero, the shutter will relax. In many shutter assemblies, the mechanically relaxed position is only partially open or closed, and so this voltage condition is usually avoided in an addressing scheme.
The condition of rule 2 makes it possible to include a global actuation function into an addressing scheme. By maintaining a shutter voltage which provides beam voltage differences that are at least the maintenance voltage, Vm, the absolute values of the shutter open and shutter closed potentials can be altered or switched in the midst of an addressing sequence over wide voltage ranges (even where voltage differences exceed Vat) with no danger of unintentional shutter motion.
The conditions of rules 3 and 4 are those that are generally targeted during the addressing sequence to ensure the bi-stable actuation of the shutter.
The maintenance voltage difference, Vm, can be designed or expressed as a certain fraction of the actuation threshold voltage, Vat. For systems designed for a useful degree of bi-stability, the maintenance voltage can exist in a range between about 20% and about 80% of Vat. This helps ensure that charge leakage or parasitic voltage fluctuations in the system do not result in a deviation of a set holding voltage out of its maintenance range—a deviation which could result in the unintentional actuation of a shutter. In some systems, an exceptional degree of bi-stability or hysteresis can be provided, with Vm existing over a range of about 2% and about 98% of Vat. In these systems, however, care must be taken to ensure that an electrode voltage condition of |Vc−Vs| or |Vo−Vs| being less than Vm can be reliably obtained within the addressing and actuation time available.
In some implementations, the first and second actuators of each light modulator are coupled to a latch or a drive circuit to ensure that the first and second states of the light modulator are the only two stable states that the light modulator can assume.
The pixel circuit 300 includes a data loading circuit 304, an actuation circuit 306, and a voltage feedback circuit 308. The data loading circuit 304 is configured to load a data voltage from the data interconnect 310. The actuation circuit 306 is configured to provide an actuation voltage to the light modulator 302 based on the data voltage. The voltage feedback circuit 308 is configured to provide a positive feedback voltage from the output of the actuation circuit 306 to an input of the actuation circuit 306.
The pixel circuit 300 receives voltage signals from various interconnects. For example, as mentioned above, the data interconnect 310 provides a data voltage that is to be stored at the pixel circuit 300. The data interconnect 310 can be common to all pixel circuits associated with pixels in the same column of a pixel array. The pixel circuit 300 can receive a write enable voltage from a write enable interconnect 312, also referred to as scan line. The write enable interconnect 312 can be common to all pixel circuits associated with pixels in the same row of the pixel array. The pixel circuit 300 is also coupled to an actuation voltage interconnect 314, which provides the pixel circuit 300 with an actuation voltage. In addition, a common interconnect 316 provides a common or ground terminal to the pixel circuit 300.
The data loading circuit 304 includes a data loading transistor 318 and a data storage capacitor 320. The drain/source terminal of the data loading transistor 318 is coupled to the data interconnect 310, while the source/drain terminal of the data loading transistor 318 is coupled to the data storage capacitor 320. The gate terminal of the data loading transistor 318 is coupled to the write enable interconnect 312. The data loading transistor 318 can operate as a switch and can be selectively switched ON or OFF by the write enable voltage on the write enable interconnect 312. For example, the write enable voltage on the write enable interconnect 312 can be appropriately selected to switch ON the data loading transistor 318, causing the data voltage appearing on the data interconnect 310 to be stored in the data storing capacitor 320.
The actuation circuit 306 includes an actuation transistor 322 and a discharge transistor 324. The actuation transistor 322 can operate as a switch and can provide a charge path from the actuation voltage interconnect 314 to a first output node 326 of the pixel circuit 300. The discharge transistor 324 also can operate as a switch and can provide a discharge path between the first output node 326 and the common interconnect 316. The gate terminal of the actuation transistor 322 is coupled to an input node 328, which is also coupled to the source/drain terminal of the data loading transistor 318 and to the data storage capacitor 320. The actuation transistor 322 can switch ON or OFF based on the data voltage loaded by the data loading circuit 304 and stored in the data storage capacitor 320. If the data voltage is sufficient to switch the actuation transistor ON, then the first output node 326 is charged to a voltage that is substantially equal to the actuation voltage on the actuation voltage interconnect 314. The gate terminal of the discharge transistor 324 is coupled to the write enable interconnect 312 (which is also coupled to the gate terminal of the data loading transistor 318). If the voltage on the write enable interconnect 312 is sufficient to switch ON the discharge transistor 324, then the first output node 326 is discharged to a ground or common voltage.
The voltage feedback circuit 308 includes a feedback transistor 329 and the data storage capacitor 320 (which is also included in the data loading circuit 304, as discussed above). The voltage feedback circuit 308 provides a positive voltage feedback from the first output node 326 to the input node 328 of the actuation circuit 306. The drain terminal and the source terminal of the feedback transistor 329 are coupled to the actuation voltage interconnect 314 and the input node 328, respectively. The gate terminal of the feedback transistor is coupled to the first output node 326. The data storage capacitor 320 is coupled between the input node 328 and the first output node 326.
The voltage feedback circuit 308 provides a positive voltage feedback from the first output node 326 to the input node 328. Specifically, the voltage feedback circuit 308 provides a positive voltage feedback from the source terminal of the actuation transistor 322 to the gate terminal of the actuation transistor 322. For example, when the actuation voltage on the actuation interconnect 314 is increased and the data voltage stored on the data storage capacitor 320 is greater than the threshold voltage of the actuation transistor 322, the actuation transistor 322 switches ON. This causes the voltage at the first output node 326 to increase. As the gate terminal of the feedback transistor 329 is coupled to the first output node 326, the feedback transistor 329 also switches ON. This results in the input node 328, i.e., the gate terminal of the actuation transistor 322, being pulled toward the actuation voltage. This increases the voltage at the gate terminal of the actuation transistor 322, which, in turn, causes the actuation transistor 322 to further pull the first output node 326 towards the actuation voltage.
Furthermore, the data storage capacitor 320, which is coupled between the source terminal and the gate terminal of the actuation transistor 322, is a floating capacitor. Thus, as the voltage at one terminal of the data storage capacitor 320, coupled to the first output node 326, increases by a certain magnitude, the voltage at the other terminal of the data storage capacitor 320, coupled to the input terminal 328, also increases by about the same magnitude.
In this manner, the voltage feedback circuit 308 allows the first output node 326 to be charged to a voltage that is substantially greater than the data voltage stored in the data storage capacitor 320, and that is substantially equal to the actuation voltage. Thus, the first output node 326 can be charged to the actuation voltage without the need for a separate pre-charge circuit. In some implementations, even a small data voltage stored in the data storage capacitor 320 can be sufficient to charge the first output node 326 to the actuation voltage. For example, a data voltage equal to or greater than the threshold voltage of the first actuation transistor 322 can be sufficient to switch ON the actuation transistor. Switching ON the actuation transistor 322 can cause the feedback transistor 329 to switch ON and to provide a positive voltage feedback from the source terminal to the gate terminal of the actuation transistor 322, resulting in the first output node 326 to charge to the actuation voltage.
This means that the data interconnect 310 need to only be charged to a voltage that can cause the data storage capacitor 320 to be charged to a voltage that is at or slightly greater than the threshold voltage of the actuation transistor 322. By reducing the magnitude of the voltage needed at the data interconnect 310 to actuate the light modulator 302, power consumption can be reduced.
As mentioned above, the first output node 326 is coupled to the light modulator 302. Specifically, the first output node 326 is coupled to a first actuator 330. The light modulator 302 also includes a second actuator 332 and a shutter terminal 334. The second actuator 332 can be coupled to a global interconnect 336 via a second output node 338. The global interconnect 336, in some implementations, is coupled to the second actuators of all light modulators. In some implementations, the shutter terminal 334 is coupled to a shutter interconnect 340, which is used to supply a shutter voltage to the shutter terminal 334. A shutter voltage, similar to the shutter voltage Vs discussed above in relation to the shutter assembly 200 shown in
The magnitudes of voltages shown in
The first frame period F1 begins with a data loading period. The actuation voltage VACT 402, the data voltage VDATA 404, and the write enable voltage VWE 406 are maintained at a low voltage that is, for example, substantially equal to 0 V or the ground voltage. This results in the input node voltage VIN 408 and the output voltage VOUT1 410 being pulled to a voltage that is substantially equal to the ground voltage. At time t0, the data voltage can be loaded onto the data interconnect 310. This causes the data voltage VDATA 404 to increase to about 5 V. Thus, the voltage at one of the source/drain terminals of the data loading transistor 318 is raised to 5 V. The gate terminal of the data loading transistor 318 is maintained at ground voltage. Therefore, the data loading transistor 318 is in an OFF state, and the input node 328 is isolated from the data interconnect 310.
At time t1, the write enable voltage VWE 406 on the write enable interconnect 312 is raised such that both the data loading transistor 318 and the discharge transistor 324 switch ON. For example, as shown in
It should be noted that even though the voltage difference between the gate and source terminals of the actuation transistor 322 is about 5 V (which can be assumed to be greater than the threshold voltage of the actuation transistor 322), the actuation transistor 322 does not conduct any current. This is because the actuation voltage VACT 402, which is applied to the drain terminal of the actuation transistor 322, is at about 0 V; and the first output node voltage VOUT1 410, which is applied to the source terminal of the actuation transistor 322 is also at about 0V. This means that the voltage difference between the drain and source terminals of the actuation transistor 322 is about 0 V, resulting in the actuation transistor 322 not conducting any current.
At time t2, the write enable voltage VWE 406 is reduced such that both the data load transistor 318 and the discharge transistor 324 are switched OFF. For example, as shown in
While not shown in
The actuation period begins at time t3. At this time, the actuation voltage VACT 402 on the actuation voltage interconnect 314 is increased to about 25 V. Thus, the drain terminal of the actuation transistor 322, which is coupled to the actuation voltage interconnect 314, is at 25 V. This causes the actuation transistor 322 to conduct current and charge the first output node 326. As discussed above, the increase in the voltage at the first output node 326 causes the feedback transistor 329 to switch ON. The switching ON of the feedback transistor 329, in turn, causes the voltage at the input node 328, i.e., the gate terminal of the actuation transistor 322 to increase. In addition, the data storage capacitor 320, which is coupled between the gate and source terminals of the actuation transistor 322, is a floating capacitor. Therefore, any increase in voltage at the source terminal (i.e., the first output node 326) causes a substantially similar increase in the voltage at the gate terminal (i.e., the input node 328).
The combination of the actuation transistor 322 switching ON and the positive voltage feedback provided by the feedback circuit 308 causes the first output node 326 to be charged to a voltage that is substantially equal to the actuation voltage VACT 402. The input node 328, which is coupled to one terminal of the floating data storage capacitor 320 (the second terminal of which is coupled to the first output node 326), is pulled to a voltage that is about VDATA volts greater than the actuation voltage VACT 402.
As shown in
The actuation period ends at time t4. At this time, the actuation voltage VACT 402 is brought low to about 0 V. This causes both the input node voltage VIN 408 and the first output node voltage VOUT1 410 to be pulled to about 0 V. As a result, a low voltage of about 0 V is provided to the first actuator 330.
The image frame period F2 begins at time t5 with a data loading period. In contrast with the image frame period F1, during which a high data voltage appears on the data interconnect 310, in image frame period F2 a low data voltage appears on the data interconnect 310. At time t6, the write enable voltage VWE 406 is pulled high to about 5 V. This causes both the data loading transistor 318 and the discharge transistor 324 to switch ON. As the data voltage VDATA 404 at the data interconnect 310 is about 0 V, the data storage capacitor 320 is discharged such that the input node voltage VIN 408 at the input node 328 is substantially equal to 0V. Furthermore, the switching ON of the discharge transistor causes the first output node voltage VOUT1 410 to be pulled to about 0 V.
As both the input node 328 and the first output node 326 are at about 0 V, the data storage capacitor 320 is in a discharged state with the voltage across its terminals being maintained at about 0 V.
The data loading period ends and the actuation period begins at time t7. At this time, the actuation voltage VACT 402 is raised to about 25 V. This means that the drain terminal of the actuation transistor 322 is also raised to about 25 V. The gate and source terminals of the actuation transistor 322 are coupled to the input node 328 and the first output node 326, respectively. As mentioned above, both the input node 328 and the first output node 326 are at about 0 V. Thus, the voltage difference between the gate and source terminals of the actuation transistor 322 is below its threshold voltage. As a result, the actuation transistor 322 remains in the OFF state. Thus, the first output node voltage VOUT1 410 is also maintained at 0 V. This means that 0 V is provided to the first actuator 330 of the light modulator 302. Based on the voltages applied to the shutter 334 and the second output node 338, the light modulator 302 may switch to an OPEN or a CLOSED state.
In some implementations, the voltage Vs at the shutter 334 can be operated in at least two ways. For example, in some implementations, the voltage Vs at the shutter 334 can be maintained at constant voltage (such as 0 V) while the voltages VOUT1 and VOUT2 can be appropriately varied to attain the desired state of the light modulator 302. Such an operation of the pixel circuit 300 and the light modulator 302 is discussed below in relation to
As discussed above in relation to
The light modulator (LM) can switch between an OPEN, a CLOSED and an intermediate (INT) state. The light modulator 302 state can be based on the voltage states of the first output node 326, the second output node 338, and the state of the shutter 334. In the example shown in
In the timing diagram 500 shown in
The light source state 508 shows that the light source can switch between an ON and an OFF state. In the ON state the light source emits light, while in the OFF state the light source does not emit light. While the color of the light source is not specified in
The timing diagram 500 includes three image frame periods F3, F4, and F5. In some implementations, the image frame periods F3, F4, and F5 can represent subframe periods of an image frame. The image frame periods F3, F4, and F5 can be similar to the image frame periods F1 and F2 shown in
The actuation period within each image frame period F3, F4, and F5 also can include times tout2 and tlight-source each occurring after tACT. The time tout2 indicates the time at which the voltage state of the second output node 338 can be switched from ‘0’ to ‘1’ as discussed further below. A time delay is inserted between tACT and tout2 to allow the shutter 344 sufficient time to move towards the first actuator 330 if the first output node 326 is in voltage state ‘1’. The time tlight-source indicates the time when the state of the light-source can be switched from the OFF state to the ON state. A time delay is inserted between the tout2 and tlight-source to allow the shutter 334 sufficient time to move towards the second actuator 332 if the second output node 338 were in voltage state ‘1’.
Referring to
At time tACT-F3, the data loading period ends and the actuation period begins. It is assumed that during image frame period F3, a data voltage of about 0 V is loaded into the pixel circuit 300. As a result, the voltage state 502 of the first output node 326 would be ‘0’. As the voltage states of both the first output node 330 and the second output node 332 are unchanged, the shutter 334 remains in the intermediate state, as shown in
At time tout2-F3, the voltage state 504 of the second output node 338 is switched to voltage state ‘1’. This causes the shutter 334 to be pulled towards the second actuator 332. The transitioning of the shutter 334 into the CLOSED position is indicated in
Referring to
At time tACT-F4, the voltage state 502 of the first output node 326 changes to voltage state ‘1’. The change of voltage state of the first output node 326 at time tACT-F4 can be similar to the increase in the voltage at the first output node 326 from about 0 V to about 25 V, as shown in
At time tout2-F4, the voltage state of the second output node 338 switches from voltage state ‘0’ to voltage state ‘1’, by which time the light modulator 302 has completed its transition to the OPEN position, as shown in
At the beginning of the image frame period F5, the voltage states of the first output node 326 and the second output node 338 are switched from voltage state ‘1’ to voltage state ‘0’ at time tdata-load-F5. Thus, as shown in
At time tout2-F5, the voltage state 504 of the second output node 338 is also switched from voltage state ‘0’ to voltage state ‘1’ (as shown in
In some implementations, the duration of time for which the state of the light-source is maintained in the ON state during an image frame period can be increased. For example, referring to
As indicated above,
As mentioned above,
Referring to
At time tACT-F5, when the data loading period ends and the actuation period begins, the voltage state 710 of the shutter 334 is switched back to voltage state ‘0’. The state 708 of the light-source is also switched from the ON state to the OFF state. At time tACT-F5, each light modulator in the display array can assume a state based on the data voltage loaded during the data loading period for image frame period F5. That is, the light modulators 302 may transition from one state to another. Thus, the state 708 of the light-source can be switched OFF to allow the light modulators 302 to successfully transition to their next state. The state 706 of the light modulator 302 shown in
The switching of the voltage state 710 of the shutter 334 as described above between image frame periods F4 and F5 can be similarly carried out during the transitions between any two image frame periods. For example, in transitioning from the image frame period F3 to image frame period F4, the voltage state 710 of the shutter 334 is switched form voltage state ‘0’ to voltage state ‘1’ at the beginning of the data loading period of the image frame period F4 (as shown in
Similarly, when transitioning to the image frame period F3 from the image frame previous to the image frame period F3, the voltage state 710 of the shutter 334 is switched from the voltage state ‘0’ to the voltage state ‘1’ at the beginning (time tdata-load-F3) of the data loading period of the image frame period F3 (as shown in
The state of the light modulator 302 shown in
In some implementations, the increase in the period for which the state 708 of the light-source can be maintained in an ON state allows the display device to display the image with greater pixel intensity. In some other implementations, with the increased illumination time, the illumination intensity of the light-source, and therefore the power consumption of the display, can be reduced.
As discussed above in relation to
As mentioned above,
The second example pixel circuit 900 is similar to the first example pixel circuit 300 shown in
The light modulator (LM) can switch between OPEN and CLOSED states. While not shown in
The light modulator 302 state 1004 can be based on the voltage states of the first shutter 334, the first actuator 330 and the second actuator 332. For
The light-source state 1006 shows that the light-source can switch between an ON and an OFF state. In the ON state the light-source emits light, while in the OFF state the light-source does not emit light.
The timing diagram 1000 includes image frame periods F6 and F7. In some implementations, the image frame periods F6 and F7 can represent subframe periods of an image frame. The image frame periods F6 and F7 can be similar to the image frame periods F1 and F2 shown in
The actuation period within each image frame period F6 and F7 also includes times tlight-source-F6 and tlight-source-F7, respectively. The times tlight-source-F6 and tlight-source-F7 indicate the times when the state of the light-source can be switched from the OFF state to the ON state in the image frame periods F6 and F7, respectively. A time delay is inserted between tACT-F6/tACT-F7 and tlight-source-F6/tlight-source-F7 to allow the light modulator 302 sufficient time to settle into a state.
Referring to
At time tACT-F6, the data loading period ends and the actuation period begins. It is assumed that during image frame period F6, a data voltage of about 5 V is loaded into the pixel circuit 900. As a result, the voltage state 502 of the first output node 326 would be ‘1’. Thus, the shutter 334 would be pulled towards the second actuator 332, which is maintained at voltage state ‘0’, as shown in
A time delay is inserted between tACT-F6 and tlight-source-F6 to allow the light modulator 302 of all the pixels in the pixel array to settle into their respective intended states. By time tlight-source-F6, the shutter 334 moves to the OPEN position near the second actuator 332 (as shown in
The next image frame period F7 begins with the data loading period at time tdata-load-F7. At this time the first output node 326 is discharged. As the previous voltage state 1002 of the first output node 326 was voltage state ‘1’, the discharging of the first output node 326 causes the voltage state of the shutter 334 to change from voltage state ‘1’ to voltage state ‘0’. While in the previous voltage state ‘1’, the shutter 334 is pulled by the second actuator 332, which is at voltage state ‘0’, when the voltage state of the shutter 334 is changed to voltage state ‘0’, the shutter 334 is pulled towards the first actuator 330, which is maintained at voltage state ‘1’ (as shown in
The actuation period begins at time tACT-F7. As the data voltage loaded into the pixel circuit 900 is about 5 V, the output voltage at the first output node 326 increases to the actuation voltage. Thus, the voltage state 1002 of the first output node 326 changes from voltage state ‘0’ to voltage state ‘1’. As the voltage state 1002 of the first output node 326 switches to voltage state ‘1’, the voltage state of the shutter 334 also switches to voltage state ‘1’. As the second actuator 332 is maintained at the voltage state ‘0’, the shutter 334 would be pulled towards the second actuator 332 and into an OPEN position (as shown in
At time tlight-source-F7, the state 1006 of the light-source is switched form the OFF state to the ON state. At this time, the light modulators 302 of all the pixels in the pixel array would have settled into their respective states. Thus, when the light-source is illuminated in the ON state, an image can be displayed by the display device.
As mentioned above, in some implementations, the duration of time for which the state of the light-source is maintained in the ON state during an image frame period can be increased. For example, referring to
In some implementations, an increase in the duration for which the light-source state can be maintained in the ON state can be accomplished by manipulating the voltage states of the first actuator interconnect 904 and the second actuator interconnect 906. Specifically, the voltage state of, for example, the second actuator interconnect 906 can be switched at the beginning of the data loading period such that the state of the light modulator 302 is maintained in its previous state. As the state of the light modulator 302 does not switch during the data loading period, the state of the light-source can be maintained in the ON state.
As mentioned above,
Referring to
As shown in
At time tACT-F7, when the actuation period begins, the voltage state 1208 of the second actuator interconnect 906 is reverted back to the voltage state ‘0’, which is complementary to the voltage state ‘1’ of the first actuator interconnect 904 (as shown in
The state 1206 of the light-source is switched to the OFF state for some duration of time at the beginning of the actuation period to allow for light modulators in other pixels to settle into their respective states.
In comparison with the timing diagram 1000 shown in
The states of the light modulator 302 shown in
As discussed above, in some implementations, the increase in the duration of time for which the state 1206 of the light-source can be maintained in an ON state allows the display device to display the image with greater pixel intensity. In some other implementations, for a given pixel intensity, the illumination intensity of the light-source, and therefore the power consumption, can be reduced.
While not shown in
In some implementations, the pixel circuit 300 shown in
The first image frame period F1 begins with a data loading period. The actuation voltage VACT 1402, the data voltage VDATA 1404, and the write enable voltage VWE 1406 are maintained at a low voltage that is, for example, substantially equal to 0 V or the ground voltage. Thus, the voltage VOUT1 1410 at the first output node 326 is pulled low. This means that the shutter 334 is maintained at a low voltage of about 0 V. Assuming that the first actuator interconnect 904 and the second actuator interconnect 906 are maintained at about 25 V and 0 V, respectively, the shutter 334 would be pulled towards the first actuator 330. It is assumed that when the shutter 334 is pulled to the first actuator 330, the light modulator 302 is in a CLOSED state, while when the shutter 334 is pulled to the second actuator 332, the light modulator is in an OPEN state. Thus, as shown in
Also during the data loading period, at time t0, the data interconnect 310 is loaded with the data voltage VDATA1. Subsequently, at time t1, the write enabling voltage VWE 1406 is increased to a high voltage such that both the data loading transistor 318 and the discharge transistor 324 are switched ON. As a result, the data voltage VDATA1 is loaded onto the data storing capacitor 320. After the data voltage has been loaded onto the data storing capacitor 320, the write enable voltage VWE 1406 is brought low such that both the data loading transistor 318 and the discharge transistor 324 are switched OFF.
At time t3, the data loading period ends and the actuation period begins. At this time, the actuation voltage VACT 1402 on the actuation voltage interconnect 314 is increased to about 25 V. As discussed above in relation to
As shown in
The light modulator 302 remains in the OPEN state for the remaining actuation period until time t4. Specifically, the light modulator 302 remains in the OPEN state for period tOPEN-1. After this period, the voltage VOUT1 1410 at the first output node 326 is pulled to about 0 V. This can cause the state 1410 of the light modulator 302 to switch back to the CLOSED state.
During the data loading period of the image frame period F2 starting at time t5, a data voltage VDATA2 is loaded into the data storing capacitor 320 at time t6. The data voltage VDATA2 is less than the data voltage VDATA1 loaded during the image frame period F1. For example, VDATA2 may be equal to about 1.5 V.
At time t7, the actuation period of the image frame period F2 begins. As discussed above, at the beginning of the actuation period the actuation voltage VACT 1402 increases to about 25 V. As the voltage across the actuation transistor 322 is greater than the threshold voltage of the actuation transistor 322, the actuation transistor 322 switches ON. This causes the voltage VOUT1 at the first output node 326 to increase.
As discussed above, the rate at which the voltage VOUT1 increases is a function of the data voltage stored in the data storing capacitor 320. The data voltage VDATA2 stored in the data storage capacitor 320 during image frame period F2 is less than the data voltage VDATA1 stored during the first image frame period F1. Therefore, the rate of increase of the voltage VOUT1 1410 corresponding to the data voltage VDATA2 would be less than its rate of increase corresponding to the data voltage VDATA1. As a result, in image frame period F2, it takes relatively longer for the voltage VOUT1 1410 to reach the actuation threshold voltage VTH-ACT. For example, as shown in
The relatively slower rate of increase of the voltage at the shutter 334 results in a relatively shorter period for which the light modulator 302 can remain in the OPEN state. For example, for the image frame period F2, the light modulator 302 remains in the OPEN state for period tOPEN-2, which is relatively shorter than the period tOPEN-1 corresponding to image frame period F1. Assuming that the light-source is switched ON during the entire actuation period, the total intensity of light transmitted during an image frame period depends upon the time for which the light modulator 302 can remain in the OPEN state during the actuation period. As the time for which the light modulator 302 remains in the OPEN state can be controlled by selecting the appropriate data voltage VDATA 1404, the total intensity of light transmitted by a pixel during an image frame period can be controlled by storing the appropriate value of the data voltage VDATA into the data storage capacitor.
In some implementations, the analog operation of the pixel circuit 900 can be utilized to implement analog gray scale techniques in displaying images on a display. Using analog gray scale techniques can mitigate image artifacts such as flicker, dynamic false contouring (DFC), and color break-up (CBU) that can adversely affect the use of digital gray scale techniques in displaying images.
The process 1500 includes accepting a data voltage from a data interconnect (stage 1502). One example of this process stage has been discussed above in relation to
The process 1500 also includes discharging an output node of an actuation circuit, where the output node is coupled to a light modulator (stage 1504). One example of this process stage has been discussed above in relation to
The process 1500 also includes charging t/he output node to an actuation voltage via the actuation circuit based on the data voltage (stage 1506). One example of this process stage has been discussed above in relation to
The process 1500 also includes providing a positive feedback voltage from the output node to the input node of the actuation circuit (stage 1508). One example of this process stage has been discussed above in relation to
The display device 40 includes a housing 41, a display 30, an antenna 43, a speaker 45, an input device 48 and a microphone 46. The housing 41 can be formed from any of a variety of manufacturing processes, including injection molding, and vacuum forming. In addition, the housing 41 may be made from any of a variety of materials, including, but not limited to: plastic, metal, glass, rubber and ceramic, or a combination thereof. The housing 41 can include removable portions (not shown) that may be interchanged with other removable portions of different color, or containing different logos, pictures, or symbols.
The display 30 may be any of a variety of displays, including a bi-stable or analog display, as described herein. The display 30 also can be capable of including a flat-panel display, such as plasma, electroluminescent (EL) displays, OLED, super twisted nematic (STN) display, LCD, or thin-film transistor (TFT) LCD, or a non-flat-panel display, such as a cathode ray tube (CRT) or other tube device. In addition, the display 30 can include a mechanical light modulator-based display, as described herein.
The components of the display device 40 are schematically illustrated in
The network interface 27 includes the antenna 43 and the transceiver 47 so that the display device 40 can communicate with one or more devices over a network. The network interface 27 also may have some processing capabilities to relieve, for example, data processing requirements of the processor 21. The antenna 43 can transmit and receive signals. In some implementations, the antenna 43 transmits and receives RF signals according to any of the IEEE 16.11 standards, or any of the IEEE 802.11 standards. In some other implementations, the antenna 43 transmits and receives RF signals according to the Bluetooth® standard. In the case of a cellular telephone, the antenna 43 can be designed to receive code division multiple access (CDMA), frequency division multiple access (FDMA), time division multiple access (TDMA), Global System for Mobile communications (GSM), GSM/General Packet Radio Service (GPRS), Enhanced Data GSM Environment (EDGE), Terrestrial Trunked Radio (TETRA), Wideband-CDMA (W-CDMA), Evolution Data Optimized (EV-DO), 1×EV-DO, EV-DO Rev A, EV-DO Rev B, High Speed Packet Access (HSPA), High Speed Downlink Packet Access (HSDPA), High Speed Uplink Packet Access (HSUPA), Evolved High Speed Packet Access (HSPA+), Long Term Evolution (LTE), AMPS, or other known signals that are used to communicate within a wireless network, such as a system utilizing 3G, 4G or 5G, or further implementations thereof, technology. The transceiver 47 can pre-process the signals received from the antenna 43 so that they may be received by and further manipulated by the processor 21. The transceiver 47 also can process signals received from the processor 21 so that they may be transmitted from the display device 40 via the antenna 43.
In some implementations, the transceiver 47 can be replaced by a receiver. In addition, in some implementations, the network interface 27 can be replaced by an image source, which can store or generate image data to be sent to the processor 21. The processor 21 can control the overall operation of the display device 40. The processor 21 receives data, such as compressed image data from the network interface 27 or an image source, and processes the data into raw image data or into a format that can be readily processed into raw image data. The processor 21 can send the processed data to the driver controller 29 or to the frame buffer 28 for storage. Raw data typically refers to the information that identifies the image characteristics at each location within an image. For example, such image characteristics can include color, saturation and gray-scale level.
The processor 21 can include a microcontroller, CPU, or logic unit to control operation of the display device 40. The conditioning hardware 52 may include amplifiers and filters for transmitting signals to the speaker 45, and for receiving signals from the microphone 46. The conditioning hardware 52 may be discrete components within the display device 40, or may be incorporated within the processor 21 or other components.
The driver controller 29 can take the raw image data generated by the processor 21 either directly from the processor 21 or from the frame buffer 28 and can re-format the raw image data appropriately for high speed transmission to the array driver 22. In some implementations, the driver controller 29 can re-format the raw image data into a data flow having a raster-like format, such that it has a time order suitable for scanning across the display array 30. Then the driver controller 29 sends the formatted information to the array driver 22. Although a driver controller 29 is often associated with the system processor 21 as a stand-alone Integrated Circuit (IC), such controllers may be implemented in many ways. For example, controllers may be embedded in the processor 21 as hardware, embedded in the processor 21 as software, or fully integrated in hardware with the array driver 22.
The array driver 22 can receive the formatted information from the driver controller 29 and can re-format the video data into a parallel set of waveforms that are applied many times per second to the hundreds, and sometimes thousands (or more), of leads coming from the display's x-y matrix of display elements. In some implementations, the array driver 22 and the display array 30 are a part of a display module. In some implementations, the driver controller 29, the array driver 22, and the display array 30 are a part of the display module.
In some implementations, the driver controller 29, the array driver 22, and the display array 30 are appropriate for any of the types of displays described herein. For example, the driver controller 29 can be a conventional display controller or a bi-stable display controller (such as a mechanical light modulator display element controller). Additionally, the array driver 22 can be a conventional driver or a bi-stable display driver (such as a mechanical light modulator display element controller). Moreover, the display array 30 can be a conventional display array or a bi-stable display array (such as a display including an array of mechanical light modulator display elements). In some implementations, the driver controller 29 can be integrated with the array driver 22. Such an implementation can be useful in highly integrated systems, for example, mobile phones, portable-electronic devices, watches or small-area displays.
In some implementations, the input device 48 can be configured to allow, for example, a user to control the operation of the display device 40. The input device 48 can include a keypad, such as a QWERTY keyboard or a telephone keypad, a button, a switch, a rocker, a touch-sensitive screen, a touch-sensitive screen integrated with the display array 30, or a pressure- or heat-sensitive membrane. The microphone 46 can be configured as an input device for the display device 40. In some implementations, voice commands through the microphone 46 can be used for controlling operations of the display device 40. Additionally, in some implementations, voice commands can be used for controlling display parameters and settings.
The power supply 50 can include a variety of energy storage devices. For example, the power supply 50 can be a rechargeable battery, such as a nickel-cadmium battery or a lithium-ion battery. In implementations using a rechargeable battery, the rechargeable battery may be chargeable using power coming from, for example, a wall socket or a photovoltaic device or array. Alternatively, the rechargeable battery can be wirelessly chargeable. The power supply 50 also can be a renewable energy source, a capacitor, or a solar cell, including a plastic solar cell or solar-cell paint. The power supply 50 also can be configured to receive power from a wall outlet.
In some implementations, control programmability resides in the driver controller 29 which can be located in several places in the electronic display system. In some other implementations, control programmability resides in the array driver 22. The above-described optimization may be implemented in any number of hardware and/or software components and in various configurations.
As used herein, a phrase referring to “at least one of” a list of items refers to any combination of those items, including single members. As an example, “at least one of: a, b, or c” is intended to cover: a, b, c, a-b, a-c, b-c, and a-b-c.
The various illustrative logics, logical blocks, modules, circuits and algorithm processes described in connection with the implementations disclosed herein may be implemented as electronic hardware, computer software, or combinations of both. The interchangeability of hardware and software has been described generally, in terms of functionality, and illustrated in the various illustrative components, blocks, modules, circuits and processes described above. Whether such functionality is implemented in hardware or software depends upon the particular application and design constraints imposed on the overall system.
The hardware and data processing apparatus used to implement the various illustrative logics, logical blocks, modules and circuits described in connection with the aspects disclosed herein may be implemented or performed with a general purpose single- or multi-chip processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general purpose processor may be a microprocessor, or, any conventional processor, controller, microcontroller, or state machine. A processor also may be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. In some implementations, particular processes and methods may be performed by circuitry that is specific to a given function.
In one or more aspects, the functions described may be implemented in hardware, digital electronic circuitry, computer software, firmware, including the structures disclosed in this specification and their structural equivalents thereof, or in any combination thereof. Implementations of the subject matter described in this specification also can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions, encoded on a computer storage media for execution by, or to control the operation of, data processing apparatus.
Various modifications to the implementations described in this disclosure may be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other implementations without departing from the spirit or scope of this disclosure. Thus, the claims are not intended to be limited to the implementations shown herein, but are to be accorded the widest scope consistent with this disclosure, the principles and the novel features disclosed herein.
Additionally, a person having ordinary skill in the art will readily appreciate, the terms “upper” and “lower” are sometimes used for ease of describing the figures, and indicate relative positions corresponding to the orientation of the figure on a properly oriented page, and may not reflect the proper orientation of any device as implemented.
Certain features that are described in this specification in the context of separate implementations also can be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation also can be implemented in multiple implementations separately or in any suitable subcombination. Moreover, although features may be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.
Similarly, while operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Further, the drawings may schematically depict one more example processes in the form of a flow diagram. However, other operations that are not depicted can be incorporated in the example processes that are schematically illustrated. For example, one or more additional operations can be performed before, after, simultaneously, or between any of the illustrated operations. In certain circumstances, multitasking and parallel processing may be advantageous. Moreover, the separation of various system components in the implementations described above should not be understood as requiring such separation in all implementations, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products. Additionally, other implementations are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results.
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