This disclosure relates generally to display circuits.
Thin film transistors (TFTs) are a type of field effect transistor that can be made by depositing thin films over a supporting but non-conducting substrate. TFTs can be used in display panels (and/or display backplanes), in which a common substrate is glass. Displays have been transitioning from liquid crystal displays (LCDs) to organic light emitting diode (OLED) displays. A major driving force for this change has been use of oxide semiconductor materials as the active channel layer in thin film transistors (TFTs) of the display.
The following detailed description may be better understood by referencing the accompanying drawings, which contain specific examples of numerous features of the disclosed subject matter.
In some cases, the same numbers are used throughout the disclosure and the figures to reference like components and features. In some cases, numbers in the 100 series refer to features originally found in
Some embodiments relate to display circuits. Some embodiments relate to a display including a display timing controller (TCON) embedded driver circuit combined with a de-multiplexer (DEMUX) circuit.
It is desirable for a bezel of a display to be as thin as possible, and it is undesirable for a bezel of a display to be wide. Industry trend has been to minimize a width of display bezels as much as possible. For example, manufacturers of mobile devices have been working to make devices as small as possible, while maximizing display screen size and minimizing display bezel width within those small device size constraints. However, in some displays bezel width has necessarily increased due to, for example, a number of required traces (or paths).
In some embodiments such as, for example, those illustrated in
In some embodiments, a timing controller embedded driver integrated circuit (TED IC) can be implemented by combining two discrete functional components. In some embodiments, a timing controller and a driver circuit can be combined in a display such as a display with a thin film transistor (TFT) backplane, a TFT liquid crystal display (LCD) or an organic light emitting diode (OLED) display. A combined timing controller and driver circuit can result in a reduction of bill of material (BOM) cost (for example, due to IC integration), lower logic power, and/or slimmer (and/or smaller) printed circuit boards. Sometimes, however, a size and/or width of the display panel bezel (also sometimes referred to as “black matrix”) can increase due to the integration of the timing controller and driver functionalities due to a need to operate a wider active area with one driver IC.
In some embodiments, a display such as, for example, a full high definition (FHD) display panel (for example, 1920 by 1080 by 3 colors such as red, green and blue subpixels) and/or a thin film transistor (TFT) display (and/or a display with a TFT backplane) is used. In some embodiments, the display has a display panel bezel width that is impacted as illustrated in
A first (bottom) row of red (R), green (G), and blue (B) transistors 732R, 732G, and 732B are coupled to the bottom line from gate scan driver 722. A first (bottom) row of red (R), green (G), and blue (B) light emitting diodes (LEDs) 734R, 734G, and 734B are coupled to transistors 732R, 732G, and 732B, respectively. A second (middle) row of red (R), green (G), and blue (B) transistors 742R, 742G, and 742B are coupled to the middle line from gate scan driver 722. A second (middle) row of red (R), green (G), and blue (B) light emitting diodes (LEDs) 744R, 744G, and 744B are coupled to transistors 742R, 742G, and 742B, respectively. A third (top) row of red (R), green (G), and blue (B) transistors 752R, 752G, and 752B are coupled to the top line from gate scan driver 722. A third (top) row of red (R), green (G), and blue (B) light emitting diodes (LEDs) 754R, 754G, and 754B are coupled to transistors 752R, 752G, and 752B, respectively.
Display circuit 700 also includes a DEMUX circuit including transistors 762R, 762G and 762B each coupled to data driver 724. The DEMUX circuit in display circuit 700 can be referred to as a single transistor DEMUX circuit with a single transistor for each subpixel data line. Transistor 762R is coupled to data driver 724, a first subpixel line (R subpixel data line), and to transistors 732R, 742R, and 752R. Transistor 762G is coupled to data driver 724, a second subpixel line (G subpixel data line), and to transistors 732G, 742G, and 752G. Transistor 762B is coupled to data driver 724, a third subpixel line (B subpixel data line), and to transistors 732B, 742B, and 752B.
A first (bottom) row of red (R), green (G), and blue (B) transistors 1032R, 1032G, and 1032B are coupled to the bottom line from gate scan driver 1022. A first (bottom) row of red (R), green (G), and blue (B) light emitting diodes (LEDs) 1034R, 1034G, and 1034B are coupled to transistors 1032R, 1032G, and 1032B, respectively. A second (middle) row of red (R), green (G), and blue (B) transistors 1042R, 1042G, and 1042B are coupled to the middle line from gate scan driver 1022. A second (middle) row of red (R), green (G), and blue (B) light emitting diodes (LEDs) 1044R, 1044G, and 1044B are coupled to transistors 1042R, 1042G, and 1042B, respectively. A third (top) row of red (R), green (G), and blue (B) transistors 1052R, 1052G, and 1052B are coupled to the top line from gate scan driver 1022. A third (top) row of red (R), green (G), and blue (B) light emitting diodes (LEDs) 1054R, 1054G, and 1054B are coupled to transistors 1052R, 1052G, and 1052B, respectively.
Display circuit 1000 also includes a DEMUX circuit including transistors 1062R, 1064R, 1062G, 1064G, 1062B, and 1064B each coupled to data driver 1024. The DEMUX circuit in display circuit 1000 can be referred to as a dual transistor DEMUX circuit with two transistors for each subpixel data line. Transistors 1062R and 1064R are coupled to each other and also are coupled to data driver 1024, a first subpixel line (R subpixel data line), and to transistors 1032R, 1042R, and 1052R. Transistor 1062G and 1064G are coupled to each other and are also coupled to data driver 1024, a second subpixel line (G subpixel data line), and to transistors 1032G, 1042G, and 1052G. Transistors 1062B and 1064B are coupled to each other, and are also coupled to data driver 1024, a third subpixel line (B subpixel data line), and to transistors 1032B, 1042B, and 1052B.
In some embodiments such as, for example, those illustrated in
In some embodiments, a timing controller embedded driver integrated circuit (TED IC) can be implemented by combining two discrete functional components. In some embodiments, a timing controller and a driver circuit can be combined in a display with a thin film transistor (TFT) backplane, a TFT liquid crystal display (LCD) or an organic light emitting diode (OLED) display. A combined timing controller and driver circuit can result in a reduction of bill of material (BOM) cost (for example, due to IC integration), lower logic power, and/or slimmer (and/or smaller) printed circuit boards. Sometimes, however, a size and/or width of the display panel bezel (also sometimes referred to as “black matrix”) can increase due to the integration of the timing controller and driver functionalities due to a need to operate a wider active area with one driver IC.
In some embodiments, a display such as, for example, a full high definition (FHD) display panel (for example, 1920 by 1080 by 3 colors such as red, green and blue subpixels) and/or a thin film transistor (TFT) display (or display with a TFT backplane) is used. In some embodiments, the display has a display panel bezel width that is impacted as illustrated in
In some embodiments, such as, for example, illustrated in some embodiments of
In some embodiments, implementation of a combined timing controller and driver circuit on an oxide thin film transistor (TFT) backplane display can improve costs and power savings, but may require an unattractive wider bezel for signal routing (for example, in some embodiments, as illustrated in
In some embodiments, considering a low mobility of oxide (for example, 10 cm2/vsec) and typical LTPS mobility of 100 cm2/vsec, a single oxide DEMUX transistor design might need to be increased by ten times (that is, 1,200 μm /3 μm) for transistor width to length ratio (W/L), resulting in a 1.2 mm panel bezel (an 1,080 μm increment). On the other hand, with dual oxide DEMUX TFTs, the DEMUX circuit can have the same transistor output with only a 600 μm/3 μm width to length (W/L), or a 0.6 mm panel bezel (480 μm increment).
In some embodiments, an integrated timing controller (TCON) plus driver integrated circuit (TCON+driver IC or TED IC) can be used to reduce platform cost and/or to reduce logic IC power. In some embodiments, this approach can be implemented using TFTs such as LTPS transistors, oxide transistors, or amorphous silicon transistors. It can be used for small size displays and high resolution displays, for example. LTPS TFT display backplanes are known to have high mobility (for example, 100 cm2/vsec) as compared with oxide TFT display backplanes (for example, 10 to 30 cm2/vsec) and amorphous silicon (a-Si) TFT display backplanes (for example 0.3 cm2/vsec). High mobility can enable implementation of de-multiplexing (DEMUX) circuitry within the display panel. However, in some embodiments, LTPS TFT backplane technology can be limited to smaller sizes due to industry capacity and high manufacturing costs. In some embodiments, integrated timing controller plus driver integrated circuit (TED IC) technology can be extended to larger size displays. In some embodiments, this extension to larger size displays can be made through use of oxide TFT display backplanes.
In some embodiments, DEMUX circuits such as, for example, DEMUX circuits illustrated in
In some embodiments, such as, for example, DEMUX circuits illustrated in
In some embodiments, a single DEMUX TFT implementation can be used in high mobility and/or high pixel per inch (PPI) displays. For example, in some embodiments, a single DEMUX TFT implementation can be used in LTPS TFT LCD or OLED implementations. This can be implemented in a single DEMUX TFT implementation that only has one transistor output (for example, one drain output) per sub-pixel, where DEMUX TFT pitch is small (for example, five times the channel length or 5L).
In some embodiments, dual DEMUX TFT implementations can be more efficient than single DEMUX TFT implementations such as those having two output (drain) nodes with only one input (source) node per sub-pixel. Use of dual TFT DEMUX implementations can reduce transistor channel width (and/or can reduce transistor width to length ratio, and/or can reduce transistor size) by 50% relative to a single TFT DEMUX implementation. This can result in a panel bezel width reduction, for example. With a same layout design rule, dual DEMUX TFT pitch can be bigger than a single type (8L vs. 5L, for example). In some embodiments, dual DEMUX TFT can be particularly beneficial for oxide TFT DEMUX and low pixel per inch (for example, lower than 300 PPI).
In some embodiments, a fixed low frame rate (FLFR) can be used. Use of a fixed low frame rate (for example, in some embodiments, below 60 Hz) can increase viability of timing controller embedded data driver IC combined with DEMUX approaches. This can allow a further extension of cost and power consumption benefits to higher pixel per inch (PPI) implementations. In some embodiments, driving at a low frequency can allow for lower power consumption when combined with logic power savings of timing controller embedded data driver IC (TED IC) implementations. In some embodiments, combining DEMUX circuit implementation with fixed low frame rate (FLFR) can help in providing a slim design with cost efficient and lower power displays. This can be implemented, for example, in mobile devices such as a 2in1 mobile computing device, for example.
In some embodiments, an ultra-high-definition (UHD) implementation can be implemented. For example, a 13.3 inch UHD display may have a 25.5 μm subpixel pitch as 332 PPI. One UHD gate scan time can be around 7.73 μsec at 60 Hz (without considering balnking time and others, for example). In implementations using RGB DEMUX, this time can be 2.53 μsec, for example. In a 30 Hz implementation, one gate scan time can be around 15.43 μsec. In a 1 to 3 RGB DEMUX implementation, the time can become around 5.143 μsec, and in a 1 to 2 DEMUX it can be around 7.715 μsec. In a 40 Hz implementation, one gate scan time can be around 11.57 μsec, and 1 to 3 RGB DEMUX can bring the time down to 3.86 μsec, and 1 to 2 DEMUX can bring the time down to around 5.785 μsec, for example.
The processor 1202 may also be linked through a system interconnect 1206 (e.g., PCI®, PCI-Express®, NuBus, etc.) to a display interface 1208 adapted to connect the computing device 1200 to a display device 1210. In some embodiments, display device 1210 can include one or more displays, display circuits, DEMUX, and/or any other circuits or functionality as described and/or illustrated herein. The display device 1210 may include a display screen that is a built-in component of the computing device 1200. The display device 810 may include a display panel, a display backlight, display circuits, DEMUX, and/or display drivers, for example.
In some embodiments, the display interface 1208 can include any suitable graphics processing unit, transmitter, port, physical interconnect, and the like. In some examples, the display interface 1208 can implement any suitable protocol for transmitting data to the display device 1210. For example, the display interface 1208 can transmit data using a high-definition multimedia interface (HDMI) protocol, a DisplayPort protocol, or some other protocol or communication link, and the like
In some embodiments, display device 1210 includes a display controller. In some embodiments, a display controller can provide control signals within and/or to the display device. In some embodiments, a display controller can be included in the display interface 1208 (and/or instead of the display interface 1208). In some embodiments, a display controller can be coupled between the display interface 1208 and the display device 1210. In some embodiments, the display controller can be coupled between the display interface 1208 and the interconnect 1206. In some embodiments, the display controller can be included in the processor 1202. In some embodiments, the display controller can implement functionality according to any of the examples illustrated in any of the drawings and/or as described anywhere herein.
In some embodiments, any of the techniques described in this specification can be implemented entirely or partially within the display device 1210. In some embodiments, any of the techniques described in this specification can be implemented entirely or partially within a display controller. In some embodiments, any of the techniques described in this specification can be implemented entirely or partially within the processor 1202.
In addition, a network interface controller (also referred to herein as a NIC) 1212 may be adapted to connect the computing device 1200 through the system interconnect 1206 to a network (not depicted). The network (not depicted) may be a wireless network, a wired network, cellular network, a radio network, a wide area network (WAN), a local area network (LAN), a global position satellite (GPS) network, and/or the Internet, among others.
The processor 1202 may be connected through system interconnect 1206 to an I/O interface 1214. I/O interface 1214 can be used to couple interconnect 1206 with one or more I/O devices 1216. One or more input/output (I/O) device interfaces 1214 may be adapted to connect the computing host device 1200 to one or more I/O devices 1216. The I/O devices 1216 may include, for example, a keyboard and/or a pointing device, where the pointing device may include a touchpad or a touchscreen, among others. The I/O devices 1216 may be built-in components of the computing device 1200, or may be devices that are externally connected to the computing device 1200.
In some embodiments, the processor 1202 may also be linked through the system interconnect 1206 to a storage device 1218 that can include a hard drive, a solid state drive (SSD), a magnetic drive, an optical drive, a portable drive, a flash drive, a Universal Serial Bus (USB) flash drive, an array of drives, and/or any other type of storage, including combinations thereof. In some embodiments, the storage device 1218 can include any suitable applications.
It is to be understood that the block diagram of
Reference in the specification to “one embodiment” or “an embodiment” or “some embodiments” of the disclosed subject matter means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosed subject matter. Thus, the phrase “in one embodiment” or “in some embodiments” may appear in various places throughout the specification, but the phrase may not necessarily refer to the same embodiment or embodiments.
Example 1 includes a display. The display includes a plurality of display pixels, an integrated timing controller and driver circuit to drive the display pixels, and a de-multiplexer circuit. The de-multiplexer circuit can include one or more transistors coupled to the integrated timing controller and driver circuit and coupled to one or more of the plurality of display pixels.
Example 2 includes the display of example 1, including or excluding optional features. In this example, the plurality of display pixels include one or more sub-pixels (for example, the display pixels can include red, green, and blue sub-pixels).
Example 3 includes the display of any of examples 1 or 2, including or excluding optional features. In this example, the display is a thin film transistor display (or a display with a thin film transistor backplane).
Example 4 includes the display of example 3, including or excluding optional features. In this example, the thin film transistor display is at least one of a low temperature polycrystalline silicon (LTPS) display (or a display with an LTPS backplane), an oxide display (or a display with an oxide backplane), and an amorphous silicon display (or a display with an amorphous silicon backplane).
Example 5 includes the display of any of examples 1-4, including or excluding optional features. In this example, the de-multiplexer circuit includes a single de-multiplexer transistor circuit.
Example 6 includes the display of any of examples 1-5, including or excluding optional features. In this example, the de-multiplexer circuit includes a dual de-multiplexer transistor circuit.
Example 7 includes the display of any of examples 1-6, including or excluding optional features. In this example, the de-multiplexer circuit includes an oxide de-multiplexer transistor circuit.
Example 8 includes the display of any of examples 1-7, including or excluding optional features. In this example, the integrated timing controller and driver circuit is to drive the display pixels at a fixed low frame rate.
Example 9 includes the display of example 8, including or excluding optional features. In this example, the fixed low frame rate is below 60 Hertz.
Example 10 includes the display of any of examples 1-9, including or excluding optional features. In this example, the de-multiplexer circuit includes one or more transistors that split sub-pixel data into separate data lines during one gate scan time.
Example 11 includes the display of any of examples 1-10, including or excluding optional features. In this example, the de-multiplexer circuit includes one or more transistors with two drain output nodes and one input source.
Example 12 is a computing device. The computing device includes a processor and a display. The display includes a plurality of display pixels, an integrated timing controller and driver circuit to drive the display pixels, and a de-multiplexer circuit including one or more transistors coupled to the integrated timing controller and driver circuit and coupled to one or more of the plurality of display pixels.
Example 13 includes the computing device of example 12, including or excluding optional features. In this example, the plurality of display pixels include one or more sub-pixels.
Example 14 includes the computing device of any of examples 12 or 13, including or excluding optional features. In this example, the display is a thin film transistor display (or a display with a thin film transistor backplane).
Example 15 includes the computing device of example 14, including or excluding optional features. In this example, the thin film transistor display is at least one of a low temperature polycrystalline silicon (LTPS) display (or a display with an LTPS backplane), an oxide display (or a display with an oxide backplane), and an amorphous silicon display (or a display with an amorphous silicon backplane).
Example 16 includes the computing device of any of examples 12-15, including or excluding optional features. In this example, the de-multiplexer circuit includes a single de-multiplexer transistor circuit.
Example 17 includes the computing device of any of examples 12-16, including or excluding optional features. In this example, the de-multiplexer circuit includes a dual de-multiplexer transistor circuit.
Example 18 includes the computing device of any of examples 12-17, including or excluding optional features. In this example, the de-multiplexer circuit includes an oxide de-multiplexer transistor circuit.
Example 19 includes the computing device of any of examples 12-18, including or excluding optional features. In this example, the integrated timing controller and driver circuit is to drive the display pixels at a fixed low frame rate.
Example 20 includes the computing device of example 19, including or excluding optional features. In this example, the fixed low frame rate is below 60 Hertz.
Example 21 includes the computing device of any of examples 12-20, including or excluding optional features. In this example, the de-multiplexer circuit includes one or more transistors that split sub-pixel data into separate data lines during one gate scan time.
Example 22 includes the computing device of any of examples 12-21, including or excluding optional features. In this example, the de-multiplexer circuit includes one or more transistors with two drain output nodes and one input source.
Example 23 is a display. The display includes a plurality of display pixels, an integrated timing controller and driver means to drive the display pixels, and means for de-multiplexing coupled to the integrated timing controller and driver means and coupled to one or more of the plurality of display pixels.
Example 24 includes the display of example 23, including or excluding optional features. In this example, the means for de-multiplexing includes one or more transistors coupled to the integrated timing controller and driver means and coupled to one or more of the plurality of display pixels.
Example 25 includes the display of any of examples 23 or 24, including or excluding optional features. In this example, the plurality of display pixels includes one or more sub-pixels.
Example 26 includes the display of any of examples 23-25, including or excluding optional features. In this example, the display is a thin film transistor display (or a display with a thin film transistor backplane).
Example 27 includes the display of example 26, including or excluding optional features. In this example, the thin film transistor display is at least one of a low temperature polycrystalline silicon (LTPS) display (or a display with an LTPS backplane), an oxide display (or a display with an oxide backplane), and an amorphous silicon display (or a display with an amorphous silicon backplane).
Example 28 includes the display of any of examples 23-27, including or excluding optional features. In this example, the means for de-multiplexing includes a single de-multiplexer transistor circuit.
Example 29 includes the display of any of examples 23-28, including or excluding optional features. In this example, the means for de-multiplexing includes a dual de-multiplexer transistor circuit.
Example 30 includes the display of any of examples 23-29, including or excluding optional features. In this example, the means for de-multiplexing includes an oxide de-multiplexer transistor circuit.
Example 31 includes the display of any of examples 23-30, including or excluding optional features. In this example, the integrated timing controller and driver means is to drive the display pixels at a fixed low frame rate.
Example 32 includes the display of example 31, including or excluding optional features. In this example, the fixed low frame rate is below 60 Hertz.
Example 33 includes the display of any of examples 23-32, including or excluding optional features. In this example, the means for de-multiplexing includes one or more transistors that split sub-pixel data into separate data lines during one gate scan time.
Example 34 includes the display of any of examples 23-33, including or excluding optional features. In this example, the means for de-multiplexing includes one or more transistors with two drain output nodes and one input source.
Example 35 is a computing device. A computing device includes processing means and display means. The display means includes a plurality of display pixels, an integrated timing controller and driver means for driving the display pixels, and means for de-multiplexing coupled to the integrated timing controller and driver means and coupled to one or more of the plurality of display pixels.
Example 36 includes the computing device of example 35, including or excluding optional features. In this example, the means for de-multiplexing includes one or more transistors coupled to the integrated timing controller and driver means and coupled to one or more of the plurality of display pixels.
Example 37 includes the computing device of any of examples 35 or 36, including or excluding optional features. In this example, the plurality of display pixels include one or more sub-pixels.
Example 38 includes the computing device of any of examples 35-37, including or excluding optional features. In this example, the display means is a thin film transistor display means.
Example 39 includes the computing device of example 38, including or excluding optional features. In this example, the thin film transistor display means is at least one of a low temperature polycrystalline silicon display means, an oxide display means, and an amorphous silicon display means.
Example 40 includes the computing device of any of examples 35-39, including or excluding optional features. In this example, the means for de-multiplexing includes a single de-multiplexer transistor circuit.
Example 41 includes the computing device of any of examples 35-40, including or excluding optional features. In this example, the means for de-multiplexing includes a dual de-multiplexer transistor circuit.
Example 42 includes the computing device of any of examples 35-41, including or excluding optional features. In this example, the means for de-multiplexing includes an oxide de-multiplexer transistor circuit.
Example 43 includes the computing device of any of examples 35-42, including or excluding optional features. In this example, the integrated timing controller and driver means is to drive the display pixels at a fixed low frame rate.
Example 44 includes the computing device of example 43, including or excluding optional features. In this example, the fixed low frame rate is below 60 Hertz.
Example 45 includes the computing device of any of examples 35-44, including or excluding optional features. In this example, the means for de-multiplexing includes one or more transistors that split sub-pixel data into separate data lines during one gate scan time.
Example 46 includes the computing device of any of examples 35-45, including or excluding optional features. In this example, the means for de-multiplexing includes one or more transistors with two drain output nodes and one input source.
Although example embodiments of the disclosed subject matter are described with reference to circuit diagrams, flow diagrams, block diagrams etc. in the drawings, persons of ordinary skill in the art will readily appreciate that many other ways of implementing the disclosed subject matter may alternatively be used. For example, the arrangements of the elements in the diagrams, and/or the order of execution of the blocks in the diagrams may be changed, and/or some of the circuit elements in circuit diagrams, and blocks in block/flow diagrams described may be changed, eliminated, or combined. Any elements as illustrated and/or described may be changed, eliminated, or combined.
In the preceding description, various aspects of the disclosed subject matter have been described. For purposes of explanation, specific numbers, systems and configurations were set forth in order to provide a thorough understanding of the subject matter. However, it is apparent to one skilled in the art having the benefit of this disclosure that the subject matter may be practiced without the specific details. In other instances, well-known features, components, or modules were omitted, simplified, combined, or split in order not to obscure the disclosed subject matter.
Various embodiments of the disclosed subject matter may be implemented in hardware, firmware, software, or combination thereof, and may be described by reference to or in conjunction with program code, such as instructions, functions, procedures, data structures, logic, application programs, design representations or formats for simulation, emulation, and fabrication of a design, which when accessed by a machine results in the machine performing tasks, defining abstract data types or low-level hardware contexts, or producing a result.
Program code may represent hardware using a hardware description language or another functional description language which essentially provides a model of how designed hardware is expected to perform. Program code may be assembly or machine language or hardware-definition languages, or data that may be compiled and/or interpreted. Furthermore, it is common in the art to speak of software, in one form or another as taking an action or causing a result. Such expressions are merely a shorthand way of stating execution of program code by a processing system which causes a processor to perform an action or produce a result.
Program code may be stored in, for example, one or more volatile and/or non-volatile memory devices, such as storage devices and/or an associated machine readable or machine accessible medium including solid-state memory, hard-drives, floppy-disks, optical storage, tapes, flash memory, memory sticks, digital video disks, digital versatile discs (DVDs), etc., as well as more exotic mediums such as machine-accessible biological state preserving storage. A machine-readable medium may include any tangible mechanism for storing, transmitting, or receiving information in a form readable by a machine, such as antennas, optical fibers, communication interfaces, etc. Program code may be transmitted in the form of packets, serial data, parallel data, etc., and may be used in a compressed or encrypted format.
Program code may be implemented in programs executing on programmable machines such as mobile or stationary computers, personal digital assistants, set top boxes, cellular telephones and pagers, and other electronic devices, each including a processor, volatile and/or non-volatile memory readable by the processor, at least one input device and/or one or more output devices. Program code may be applied to the data entered using the input device to perform the described embodiments and to generate output information. The output information may be applied to one or more output devices. One of ordinary skill in the art may appreciate that embodiments of the disclosed subject matter can be practiced with various computer system configurations, including multiprocessor or multiple-core processor systems, minicomputers, mainframe computers, as well as pervasive or miniature computers or processors that may be embedded into virtually any device. Embodiments of the disclosed subject matter can also be practiced in distributed computing environments where tasks may be performed by remote processing devices that are linked through a communications network.
Although operations may be described as a sequential process, some of the operations may in fact be performed in parallel, concurrently, and/or in a distributed environment, and with program code stored locally and/or remotely for access by single or multi-processor machines. In addition, in some embodiments the order of operations may be rearranged without departing from the spirit of the disclosed subject matter. Program code may be used by or in conjunction with embedded controllers.
While the disclosed subject matter has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the subject matter, which are apparent to persons skilled in the art to which the disclosed subject matter pertains are deemed to lie within the scope of the disclosed subject matter. For example, in each illustrated embodiment and each described embodiment, it is to be understood that the diagrams of the figures and the description herein is not intended to indicate that the illustrated or described devices include all of the components shown in a particular figure or described in reference to a particular figure. In addition, each element may be implemented with logic, wherein the logic, as referred to herein, can include any suitable hardware (e.g., a processor, among others), software (e.g., an application, among others), firmware, or any suitable combination of hardware, software, and firmware, for example.
Filing Document | Filing Date | Country | Kind |
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PCT/CN2017/105242 | 10/3/2017 | WO | 00 |