Patent Grant
10217400
This invention relates to a display control apparatus and a method of dynamically configuring a bandwidth for image data flow over an interface component from a memory element, within which image data is stored, to a display controller.
In many embedded applications, power consumption and heat generation are critical design considerations. In applications such as automotive applications, embedded devices include, for example, display controllers for infotainment and instrument cluster displays. It is known for such embedded display controllers to read (fetch) image data to be displayed on-the-fly from external memory elements. For example, the display controller periodically reads image data from a memory element, potentially performs operations like blending, format conversions in a streaming processing mode, etc. and transmits the data to be displayed to the display. In this manner, the display controllers do not require internal memory within which to store image data to be displayed, thereby enabling a significant size and cost reduction of the display controllers. In order to avoid under-run of image data from the external memory elements to the display controllers, it is necessary to ensure sufficient bandwidth is provided between the external memory elements and the display controllers. However, the higher the bandwidth of the interface between the external memory element and the embedded display controller, the higher the power consumption and heat generation associated with such an interface. Accordingly, there is a trade-off between achieving low power consumption and heat generation whilst ensuring sufficient bandwidth between the external memory element and the embedded display controller.
The present invention provides a display control apparatus, an interface bandwidth control component and a method of dynamically configuring a bandwidth for image data flow over at least one interface component as described in the accompanying claims.
Specific embodiments of the invention are set forth in the dependent claims.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.
Further details, aspects and embodiments of the invention will be described, by way of example only, with reference to the drawings. In the drawings, like reference numbers are used to identify like or functionally similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
In accordance with examples of the present invention, an interface bandwidth for image data flow from a memory element to a display controller is configured based on a measured image data flow. Advantageously, by configuring the interface bandwidth based on measured image data flow, a sufficient bandwidth for avoiding under-run of image data from the memory element to the display controller is dynamically configured. This avoids the use of a fixed, conservatively large bandwidth that would result in excessive and unnecessary power consumption and heat generation within the interface component.
Referring now to
The instantaneous display data 125 output by the display controller 120 typically includes pixel data 115 for one pixel, for example a 32-bit value made up of four 8-bit bytes defining the red, green, blue and alpha components of the pixel respectively. The display data 125 further includes a clock (Clk) signal delineating when pixel data 115 for consecutive pixels to be displayed is being output by the display controller 120. Thus, for each clock cycle of the display data 125, the display controller 120 outputs the pixel data 115 for one pixel to the display 130, e.g. 32-bits of pixel data 115. The display data 125 further includes a vertical synchronisation (V-Sync) signal indicating when the pixel data 115 being output by the display controller 120 corresponds to a first pixel of a new frame to be displayed, and a horizontal synchronisation (H-Sync) signal indicating when the current pixel data 115 being output by the display controller 120 corresponds to a first pixel of the next line in the frame to be displayed.
The display control apparatus 100 further includes at least one interface component, indicated generally at 140 in
In the illustrated example, the interface component 140 consists of a serial peripheral interface (SPI). As is well known in the art, an SPI is a synchronous serial communication interface typically used for short distance communication within embedded systems. For example, an SPI controller 142 within (or coupled to) the memory element 110 serially (i.e. one bit at a time) transmits image (e.g. pixel) data 115 over an SPI bus 145 to an SPI controller 144 within (or coupled to) the display controller 120. In some examples, the interface component 140 may consist of a quad SPI (QSPI) interface that transmits data four bits at a time.
In order to avoid under-run of pixel data 115 from the memory element 110 to the display controller 120, it is necessary to ensure sufficient bandwidth is provided across the interface component 140. Conventionally, in order to avoid under-run of pixel data 115 from the memory element 110 to the display controller 120, the interface component 140 would be configured to have a fixed bandwidth (data rate) sufficient for an anticipated maximum data flow across the interface component 140 from the memory element 110 to the display controller 120.
In the example illustrated in
For the illustrated example in which the interface component 140 consists of an SPI bus 145, the memory element 110 acts as a slave device, and as such includes an SPI bus slave module 142. In the example illustrated in
In some examples, the data flow measurement component 152 is arranged to measure image data flow across the interface component 140 over a period of time, and to output an indication 155 of a peak flow of image data 115 measured across the interface component 140 during that period of time. For example, the data flow measurement component 152 may be arranged to repeatedly measure the number of bytes transmitted across the interface component 140 during intervals of a defined duration. The data flow measurement component 152 may then output an indication 155 of the maximum number of measured bytes transmitted during a single interval of the defined duration. Such an indication 155 of the peak flow may simply be a single bit value indicating whether, for example, the maximum number of measured bytes transmitted across the interface component 140 during a single interval of the defined duration exceeded a threshold value. Conversely, such an indication 155 of the peak flow may be a multi-bit value providing a finer granularity indication of the peak flow to be output by the data flow measurement component 152.
In the example illustrated in
In some examples, the data flow measurement component 152 may be arranged to continuously measure image data flow across the interface component 140, and output an indication 155 of the peak measured data flow for each consecutive period of time (e.g. for consecutive start of frame time periods in the illustrated example). Alternatively, and as illustrated in
It is contemplated that the indication 155 of the measured data flow is not limited to providing an indication of a peak flow of image data 115 measured across the interface component 140 during a period of time. For example, the indication 155 of the measured data flow may alternatively provide an indication of, for example, total data flow during a period of time, an average data flow during a defined of time, etc.
The interface bandwidth control component 150 illustrated in
The bandwidth configuration component 154 may configure the bandwidth for image data flow over the interface component 140 from the memory element 110 to the display controller 120 in any suitable manner. For example, the bandwidth configuration component 154 may be arranged to output a bandwidth configuration signal 157 indicating a desired bandwidth for image data flow over the interface component 140. As illustrated in
Furthermore, it is contemplated that the bandwidth configuration component 154 is not limited to configuring the bandwidth for image data flow over the interface component 140 solely through configuring a data rate (i.e. clock signal) with which image data 115 is transmitted over the interface component 140. For example, the interface component 140 may consist of multiple SPI buses 145, and the bandwidth configuration component 154 may additionally/alternatively be arranged to configure the number of SPI buses used to transmit image data 115 from the memory element 110 to the display controller 120. For example, when a high bandwidth is required for transmitting image data 115 from the memory element 110 to the display controller 120, the bandwidth configuration component 154 may be arranged to enable one or more ‘auxiliary’ SPI bus(es) 145 to provide additional bandwidth. Conversely, when a low bandwidth is required for transmitting image data 115 from the memory element 110 to the display controller 120, the bandwidth configuration component 154 may be arranged to disable the auxiliary SPI bus(es) 145 to reduce power consumption and heat generation.
Additionally, it is contemplated that for examples where the interface component 140 consists of a bus/interface consisting of multiple data lines for transmitting multiple bits of data at a time, such as a quad SPI (QSPI) interface that transmits data four bits at a time, the bandwidth configuration component 154 may additionally/alternatively be arranged to configure the number of data lines used by such a bus/interface to transmit image data 115 from the memory element 110 to the display controller 120.
In some examples, and as illustrated in
Advantageously, by configuring the bandwidth for data flow over the interface component 140 based on measured image data flow, a sufficient bandwidth for avoiding under-run of image data 115 from the memory element 110 to the display controller 120 may be dynamically configured, whilst reducing the power consumption and heat generation resulting from the transmission of image data 115 from the memory element 110 to the display controller 120. In particular, as the data rate for image data being displayed changes, for example due to changes in the layers to be combined to generate the image to be displayed, the bandwidth of the interface component 140 can be dynamically adapted accordingly.
In the example illustrated in
In the example illustrated in
It will be appreciated that further alternative implementations other than those illustrated in the accompanying drawings are contemplated. For example, the data flow measurement component 152 or the bandwidth configuration component 154 may be integrated within the memory element 110. Furthermore, although the data flow measurement component 152 and the bandwidth configuration component 154 have been illustrated and hereinbefore described as separate functional components, it is contemplated that the respective functionality may be implemented within a single hardware component.
Referring now to
At least some parts the invention may be implemented in a computer program for running on a computer system, at least including code portions for performing steps of a method according to the invention when run on a programmable apparatus, such as a computer system or enabling a programmable apparatus to perform functions of a device or system according to the invention.
A computer program is a list of instructions such as a particular application program and/or an operating system. The computer program may for instance include one or more of: a subroutine, a function, a procedure, an object method, an object implementation, an executable application, an applet, a servlet, a source code, an object code, a shared library/dynamic load library and/or other sequence of instructions designed for execution on a computer system.
The computer program may be stored internally on a tangible and non-transitory computer readable storage medium or transmitted to the computer system via a computer readable transmission medium. All or some of the computer program may be provided on computer readable media permanently, removably or remotely coupled to an information processing system. The tangible and non-transitory computer readable media may include, for example and without limitation, any number of the following: magnetic storage media including disk and tape storage media; optical storage media such as compact disk media (e.g., CD-ROM, CD-R, etc.) and digital video disk storage media; non-volatile memory storage media including semiconductor-based memory units such as FLASH memory, EEPROM, EPROM, ROM; ferromagnetic digital memories; MRAM; volatile storage media including registers, buffers or caches, main memory, RAM, etc.
A computer process typically includes an executing (running) program or portion of a program, current program values and state information, and the resources used by the operating system to manage the execution of the process. An operating system (OS) is the software that manages the sharing of the resources of a computer and provides programmers with an interface used to access those resources. An operating system processes system data and user input, and responds by allocating and managing tasks and internal system resources as a service to users and programs of the system.
The computer system may for instance include at least one processing unit, associated memory and a number of input/output (I/O) devices. When executing the computer program, the computer system processes information according to the computer program and produces resultant output information via I/O devices.
In the foregoing specification, the invention has been described with reference to specific examples of embodiments of the invention. Because the illustrated embodiments of the present invention may for the most part, be implemented using electronic components and circuits known to those skilled in the art, details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention.
It will, however, be evident that various modifications and changes may be made therein without departing from the scope of the invention as set forth in the appended claims and that the claims are not limited to the specific examples described above.
The connections as discussed herein may be any type of connection suitable to transfer signals from or to the respective nodes, units or devices, for example via intermediate devices. Accordingly, unless implied or stated otherwise, the connections may for example be direct connections or indirect connections. The connections may be illustrated or described in reference to being a single connection, a plurality of connections, unidirectional connections, or bidirectional connections. However, different embodiments may vary the implementation of the connections. For example, separate unidirectional connections may be used rather than bidirectional connections and vice versa. Also, plurality of connections may be replaced with a single connection that transfers multiple signals serially or in a time multiplexed manner. Likewise, single connections carrying multiple signals may be separated out into various different connections carrying subsets of these signals. Therefore, many options exist for transferring signals.
Each signal described herein may be designed as positive or negative logic. In the case of a negative logic signal, the signal is active low where the logically true state corresponds to a logic level zero. In the case of a positive logic signal, the signal is active high where the logically true state corresponds to a logic level one. Note that any of the signals described herein can be designed as either negative or positive logic signals. Therefore, in alternate embodiments, those signals described as positive logic signals may be implemented as negative logic signals, and those signals described as negative logic signals may be implemented as positive logic signals.
Furthermore, the terms ‘assert’ or ‘set’ and ‘negate’ (or ‘de-assert’ or ‘clear’) are used herein when referring to the rendering of a signal, status bit, or similar apparatus into its logically true or logically false state, respectively. If the logically true state is a logic level one, the logically false state is a logic level zero. And if the logically true state is a logic level zero, the logically false state is a logic level one.
Those skilled in the art will recognize that the boundaries between logic blocks are merely illustrative and that alternative embodiments may merge logic blocks or circuit elements or impose an alternate decomposition of functionality upon various logic blocks or circuit elements. Thus, it is to be understood that the architectures depicted herein are merely exemplary, and that in fact many other architectures can be implemented which achieve the same functionality. For example and as previously mentioned, although the data flow measurement component 152 and the bandwidth configuration component 154 have been illustrated and hereinbefore described as separate functional components, it is contemplated that the respective functionality may be implemented within a single hardware component.
Any arrangement of components to achieve the same functionality is effectively ‘associated’ such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as ‘associated with’ each other such that the desired functionality is achieved, irrespective of architectures or intermediary components. Likewise, any two components so associated can also be viewed as being ‘operably connected,’ or ‘operably coupled,’ to each other to achieve the desired functionality.
Furthermore, those skilled in the art will recognize that boundaries between the above described operations merely illustrative. The multiple operations may be combined into a single operation, a single operation may be distributed in additional operations and operations may be executed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.
Also for example, in one embodiment, the illustrated examples may be implemented as circuitry located on a single integrated circuit or within a same device. For example, the data flow measurement component 152 and the bandwidth configuration component 154 may be implemented as circuitry located on a single integrated circuit or within a same device. Alternatively, the examples may be implemented as any number of separate integrated circuits or separate devices interconnected with each other in a suitable manner. For example, the data flow measurement component 152 and the bandwidth configuration component 154 may be implemented as any number of separate integrated circuits or separate devices interconnected with each other in a suitable manner.
Also for example, the examples, or portions thereof, may implemented as soft or code representations of physical circuitry or of logical representations convertible into physical circuitry, such as in a hardware description language of any appropriate type.
Also, the invention is not limited to physical devices or units implemented in non-programmable hardware but can also be applied in programmable devices or units able to perform the desired device functions by operating in accordance with suitable program code, such as mainframes, minicomputers, servers, workstations, personal computers, notepads, personal digital assistants, electronic games, automotive and other embedded systems, cell phones and various other wireless devices, commonly denoted in this application as ‘computer systems’.
However, other modifications, variations and alternatives are also possible. The specifications and drawings are, accordingly, to be regarded in an illustrative rather than in a restrictive sense.
In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word ‘comprising’ does not exclude the presence of other elements or steps then those listed in a claim. Furthermore, the terms ‘a’ or ‘an,’ as used herein, are defined as one or more than one. Also, the use of introductory phrases such as ‘at least one’ and ‘one or more’ in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles ‘a’ or ‘an’ limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases ‘one or more’ or ‘at least one’ and indefinite articles such as ‘a’ or ‘an.’ The same holds true for the use of definite articles. Unless stated otherwise, terms such as ‘first’ and ‘second’ are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. The mere fact that certain measures are recited in mutually different claims does not indicate that a combination of these measures cannot be used to advantage.
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| PCT/IB2015/001566 | Aug 2015 | WO | international |
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| 20170039932 A1 | Feb 2017 | US |
