Display control semiconductor integrated circuit

Abstract

The present invention provides a display control semiconductor integrated circuit having therein a RAM, capable of repairing a defective bit included in the RAM and improving the yield without significantly increasing the occupation area. A liquid crystal controller/driver in which a RAM for storing display data is provided in a chip and the storage capacity of the built-in RAM is determined according to the size of a display screen of a liquid crystal panel to be driven, includes a fuse circuit for setting a defect address, and a comparing circuit for comparing the defect address set in the fuse circuit with an input address. The liquid crystal controller/driver also has a redundant circuit, when the addresses match each other, for replacing the input address with an address that instructs the spare memory area and supplying the address to an address decoder.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing an embodiment of a liquid crystal controller/driver having therein a RAM and a repairing circuit.

FIG. 2 is a diagram showing the relation between a storage area and an address space in a display memory in the liquid crystal controller/driver of the embodiment.

FIG. 3 is a diagram showing the relation between a display screen and a window area in the case of performing window display and a window area.

FIG. 4 is a diagram showing the relation between a word select address and repair information in a memory in which a data storage area is set in a whole data storage area and there is no unused address space like a general RAM.

FIG. 5 is a diagram showing the relation between a word select address and repair information in a display memory in the liquid crystal controller/driver of the embodiment.

FIG. 6 is a block diagram showing a configuration example of a repair circuit in the liquid crystal controller/driver of the embodiment.

FIG. 7 is a time chart showing operation timings in the repair circuit of the liquid crystal controller driver of the embodiment.

FIG. 8 is a block diagram showing a configuration example of a replacing circuit in the repair circuit of the embodiment.

FIG. 9 is a block diagram showing another configuration example of the replacing circuit in the embodiment.

FIG. 10 is a block diagram showing the configuration of a redundancy circuit employed in a general RAM.

Claims

1. A display control semiconductor integrated circuit comprising: a readable/writable display memory having a storage area smaller than an address space of the n-th power of 2, which can be expressed by an address made by a binary code of n bits (where n is an integer), and storing display data in the storage area, wherein the display memory has a spare storage area in addition to a normal storage area for storing display data; anda repair circuit for performing defect repair by replacing an area including a defect in the display memory with the spare storage area is provided,wherein an address of the spare storage area is set in the address space and on the outside of a range of addresses of the normal storage area.

2. The display control semiconductor integrated circuit according to claim 1, further comprising: an address setting register for setting an area for displaying a window in a display screen, wherein the address of the spare storage area is set on the outside of an address range in which an address can be set by the register.

3. The display control semiconductor integrated circuit according to claim 1, further comprising: repair information setting means for setting address information of an area including a defect in the display memory,wherein when address information of the area including a defect in the display memory is not set, the repair information setting means indicates an address out of the address range of the normal storage area and the spare storage area in the address space.

4. The display control semiconductor integrated circuit according to claim 3, wherein the repair information setting means does not have means for setting information indicating whether an area including a defect in the display memory is replaced with the spare memory area or not.

5. The display control semiconductor integrated circuit according to claim 1, further comprising: an address comparing circuit for comparing an address set in the repair information setting means with an input address supplied to the display memory; andan address replacing circuit, when the address comparing circuit detects a match of the addresses, for replacing the input address supplied to the display memory with an address designating the spare storage area.

6. The display control semiconductor integrated circuit according to claim 5, wherein the display memory has an address decoder, and the address decoder selects the normal storage area and the spare storage area on the basis of a common input address.

7. The display control semiconductor integrated circuit according to claim 5, wherein the address replacing circuit is constructed by a combinational logic circuit made by a plurality of logic gate circuits, receiving an address input to the address comparing circuit and an output of the address comparing circuit, and capable of outputting an address that designates the spare storage area by a logic operation.

8. The display control semiconductor integrated circuit according to claim 1, wherein replacement of an area including a defect in the display memory with the spare storage area by the repairing circuit is performed in the unit of a word as the storage area in the display memory corresponding to one display line in a display device.

9. The display control, semiconductor integrated circuit according to claim 6, further comprising: a first address counter for generating an address for writing data to the display memory;a second address counter for generating an address for reading data from the display memory;a first address comparing circuit for comparing an address generated by the first address counter with an address set in the repair information setting means; anda second address comparing circuit for comparing an address generated by the second address counter with the address set in the repair information setting means,wherein the address replacing circuit replaces an address when a match of addresses is detected by the first or second address comparing circuit.

10. The display control semiconductor integrated circuit according to claim 9, further comprising: a write inhibit control circuit including a third address comparing circuit for detecting whether an address generated by the first address counter lies in an address range of the normal storage area or not and, when the third address comparing circuit determines that an address generated by the first address counter does not lie in the address range of the normal storage area, generating and outputting a signal inhibiting writing of data to the display memory.