Claims
- 1. A display controller having a timing signal generating circuit for generating various timing signals utilized in the display controller, a display address generating circuit for sequentially outputting a display address, a display memory which stores pixel display data and read out the pixel display data in response to a display address provided by the display address generating circuit, a data width converting circuit which converts the pixel display data read out of said display memory into an input format of a parallel lookup table, a parallel look up table which converts said pixel display data reads out of said data width converting circuit into data indicating color corresponding to each pixel delivered to a display device, a display interface circuit for outputting image data composed of a plurality of pixels read out of said parallel lookup table in synchronous with an input timing of said display device, and a flat panel display for displaying said image data composed of said plurality of pixels read out of said display interface circuit, wherein said parallel lookup table includes memory means of n in number (where n is an integer greater than one) for storing information indicating a color of said pixel; and selection means of m number (where m is an integer greater than one) for independently receiving n pieces of information indicating color of the pixels stored in said n memory means and delivering information indicating color of pixel m in number simultaneously by each selecting one from said n pieces of information indicating color of pixel, a selecting means for inputting n pieces of information indicating color of pixel stored in said n memory means and selectively outputting information indicating color of pixel stored in said memory means in response to read access from a predetermined processor for carrying out system control or said display control system; and writing means, responsive to a write access from said processor, for writing information indicating color of pixel reads out of said processor into said memory means.
- 2. A display controller according to claims 1, wherein said parallel lookup table is formed by a single chip.
- 3. A display controller according to claims 2, wherein an output data width of image data read out of said single chip is equal to an input data width of said flat panel display.
- 4. A display controller according to claim 1, wherein said data width converting circuit, said parallel lookup table, and said display interface circuit are integrated into a single chip.
- 5. A display controller according to claim 4, wherein an output data width of image data read out of said single chip is equal to an input data width of said flat panel display.
- 6. A display controller according to claim 1, wherein said timing signal generating circuit, said display address generating circuit, said data width converting circuit, said parallel lookup table, and said display interface circuit are integrated into a single chip.
- 7. A display controller according to claim 6, wherein an output data width of image data read out of said single chip is equal to an input data width of said flat panel display.
- 8. A display controller according to claim 1, wherein said timing signal generating circuit, said display address generating circuit, said display memory, said data width converting circuit, said parallel lookup table and said display interface circuit are integrated into a single chip.
- 9. A display controller according to claim 8, wherein an output data width of image data read out of said single chip is equal to an input data width of said flat panel display.
Priority Claims (1)
Number |
Date |
Country |
Kind |
2-328891 |
Nov 1990 |
JPX |
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Parent Case Info
This is a divisional of application Ser. No. 08/224,177 filed Apr. 7, 1994 which is a divisional of application Ser. No. 07/796,678 filed Nov. 25, 1991 now U.S. Pat. No. 5,329,292.
US Referenced Citations (7)
Divisions (2)
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Number |
Date |
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Parent |
224177 |
Apr 1994 |
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Parent |
796678 |
Nov 1991 |
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