1. Field of the Invention
The present invention relates to a display controlling system and a method thereof, and particularly relates to a display controlling system that can adjust displaying frame rate without a frame rate converter and a method thereof.
2. Description of the Prior Art
However, the pixels shown in
One objective of the present invention is providing a display controlling system that can control displaying frame rate without a frame rate converter, and a related method.
One embodiment of the present invention discloses a display controlling system, which includes: a memory module, for buffering a pixel data; a comparator, for comparing the pixel data and a counter signal to generate a comparing result signal; and a pixel, for refreshing according to the comparing result signal.
Another embodiment of the present invention discloses a display controlling method, which includes: buffering a pixel data; comparing the pixel data and a counter signal to generate a comparing result signal; and refreshing a pixel according to the comparing result signal.
Another embodiment of the present invention discloses a display controlling system, which includes: a plurality of memory modules, for buffering different types of pixel data; a selector, for selecting one of memory modules as a target memory module; and a comparator, for comparing pixel data from the target memory module and a counter signal to generate a comparing result signal; a pixel, for refreshing according to the comparing result signal.
Still another embodiment of the present invention discloses a display controlling method, which includes: buffering different types of pixel data in a plurality of memory modules; selecting one of memory modules as a target memory module; comparing pixel data from the target memory module and a counter signal to generate a comparing result signal; and refreshing a pixel according to the comparing result signal.
According to above mentioned description, the displaying frame rate can be controlled without utilizing a frame rate converter, thus the cost and circuit region can be reduced.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
In this embodiment, the pixel 307 is a 3-bit pixel, and the memory module 301 includes 3 latches 313, 315 and 317 to latch the pixel data D0[0], D0[1] and D0[2] (i.e., the grey level), which are [1, 0, 0] in this case. Please note that the pixel applied to the embodiments of the present application is not limited to 3 bit. For example, the pixel can be a N-bit pixel, and N is a positive integer. Accordingly, if the counter signal CV reaches the value [1, 0, 0], the comparator 303 will generate a comparing result signal CR with a high voltage level. The meaning of the counter signal CV will be described as below. The level shifter 305 shifts a voltage level of the comparing result signal CR to generate a control signal CS to control the pixel 307 to refresh or not. For example, the voltage level of the comparing result signal CR, which is 1.8V in this embodiment, is shifted to the voltage level of the control signal CS, which is 6V in this embodiment. The control signal CS is utilized to turn on or turn off the switch 309 in the pixel 307, and the capacitor 311 is charged by the ramp voltage Vramp when the control signal CS turns on the switch 309. That is, when the control signal CS turns on the switch 309, the ramp voltage Vramp is transmitted to the pixel 307 such that the pixel 307 refreshes. The transmitted ramp voltage Vramp corresponds to the latched pixel data (i.e., the grey level) of the pixel 307. Specifically, the ramp voltage Vramp indicates grey level voltages. The counter value CV indicates the grey level and the ramp voltage Vramp varies following the counting of the counter.
The displaying frame rate can be controlled via utilizing the ramp voltage Vramp to refresh the pixel 307 or not, therefore the frame rate converter described in
Similar with the display controlling system 300 shown in
It should be noted that the above-mentioned description are only for example and do not mean to limit the scope of the present invention. For example, the pixel is not limited to a 3-bit pixel and the number of latches shown in
According to above mentioned description, the displaying frame rate can be controlled without utilizing a frame rate converter, thus the cost and circuit region can be reduced.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.