The present invention relates to a display device such as a liquid crystal display device and to an active matrix substrate to be used for the display device.
In this active matrix substrate 700, the TFT 712 turns on (the source electrode 719 and the drain electrode 708 are in a conducting state) in response to a scan signal (gate ON voltage) supplied to the scan signal line 716. In this state, a data signal (signal voltage) supplied to the data signal line 715 is written into the pixel electrode 717, through the source electrode 719, the drain electrode 708, and the drain lead-out electrode 707. Note that a retentive capacity (Cs) wiring 718 has, for example, a function of preventing self-discharge of a liquid crystal layer during a turn off period of the TFT 712.
Note that, in the active matrix substrate 700, a pixel electrode 717 in each pixel has a uniform electric potential. Namely, when an active matrix substrate 700 is used in a liquid crystal display device, a display is carried out by pixels each of which has a substantially uniform luminance over its entire surface.
Note that patent document 1 discloses a structure in which each pixel is divided into two sub-pixels, i.e. an upper sub-pixel and a lower sub-pixel, one of them is intended to be a bright pixel having high luminance and the other is intended to be a dark pixel having low luminance. This intends to suppress viewing angle dependency of γ characteristic.
[Patent Document 1] Japanese Unexamined Patent Publication, Tokukai, No. 2004-62146 (date of publication: Feb. 26, 2004)
[Patent Document 2] Japanese Unexamined Patent Publication, Tokukai, No. 2004-78157 (date of publication: Mar. 11, 2004)
However, when a display is carried out while maintaining a uniform luminance in each pixel, a problem arises that an image having a high spatial frequency blurs as illustrated in
The present invention is made in view of the foregoing problem. The objective of the present invention is to provide a display device which can clearly display an image having a high spatial frequency and an active matrix substrate to be used for the display device.
A display device of the present invention includes a plurality of pixels. Each of the pixels includes a first luminance area (high luminance area) and a second luminance area (low luminance area) which surrounds the first luminance area and has a luminance lower than that of the first luminance area. Namely, in this display device, each of the pixels includes (i) a first luminance area whose luminance can be controlled higher than that of the surrounding area, and (ii) a second luminance area, surrounding the first luminance area, whose luminance can be controlled lower than that of the first luminance area.
For example, in a display device expressed by the three primary colors (R, G, and B) of a simultaneous additive color mixture, each of the pixels is provided for each primary color. In this case, three pixels corresponding to the three primary colors are arranged in such as stripe, mosaic, or delta formation.
Thus, the display device of the present invention has pixels each of which has a pixel arrangement so that a low luminance area and a high luminance area surrounded by the low luminance area can be provided. This causes the high luminance area to deal with the total luminance or substantially the total luminance of an entire pixel (the light irradiation is carried out from the center part of a pixel) so that most of gradation displays are carried out. This allows an image having a high spatial frequency to be clearly displayed because of a great improvement in transfer characteristic in a high spatial frequency area.
In the display device of the present invention, each of the pixels may include a first switching element, a second switching element, a first sub-pixel electrode connected to the first switching element, and a second sub-pixel electrode which surrounds the first sub-pixel electrode and is connected to the second switching electrode.
The display device of the present invention is preferably arranged such that the first and the second luminance areas have the same gravity center. This structure can recreate the position information corresponding to the image signal correctly and realize smooth graphic display without jaggy edges.
The display device of the present invention is preferably arranged such that a lowest luminance area is provided between the first luminance area (high luminance area) and the second luminance area (low luminance area). The lowest luminance area (for example, formed by shielding light in periphery of the high luminance area) enables to prevent a decline in contrast due to leakage of light. Unlike the above arrangement, it is also possible to arrange the first luminance area (high luminance area) and the second luminance area (low luminance area) adjacent to each other without having the lowest luminance area therebetween.
In the display device of the present invention including an active matrix substrate and a color filter substrate, the lowest luminance area may be formed at least one of a black matrix in the color filter substrate, and a light-shielding body in the active matrix substrate. This allows a reduction in manufacturing processes and manufacturing cost because it is not necessary to form an additional light-shielding body (for preventing light leakage from the periphery of the high luminance area).
In the display device of the present invention, the first switching element and the second switching element may be connected to the same data signal line. Alternatively, the first switching element and the second switching element may be connected to the same scan signal line. In this case, for example, a first retentive capacity wiring, the first sub-pixel electrode and the first retentive capacity wiring defining capacitance, and a second retentive capacity wiring, the second sub-pixel electrode and the second retentive capacity wiring defining capacitance, are provided. Further, electric potentials of the first retentive capacity wiring and the second retentive capacity wiring are set to be controlled independently. Specifically, the first retentive capacity wiring and the second retentive capacity wiring are applied an opposite-phase signal voltage with each other. This makes easier to control an effective voltage of each first and second sub-pixel electrode and to form the high luminance area and the low luminance area. With this structure, the first retentive capacity wiring and the second retentive capacity wirings may be controlled to have waveforms whose phase shift is 180°. Also, the first and the second retentive capacity wiring may be controlled to have an electric potential which increases or decreases after each of the first and the second switching elements turns off and is then maintained until each of the first and the second switching elements turns off in the following frame.
Namely, the first retentive capacity wiring is controlled to have an electric potential which increases after each of the switching elements turns off and is then maintained until each of the switching elements turns off in the following frame. At the same time, the second retentive capacity wiring is controlled to have an electric potential which decreases after each of the switching elements turns off and is then maintained until each of the switching elements turns off in the following frame. Alternatively, the first retentive capacity wiring is controlled to have an electric potential which decreases after each of the switching elements turns off and is then maintained until each of the switching elements turns off in the following frame. At the same time, the second retentive capacity wiring is controlled to have an electric potential which increases after each of the switching elements turns off and is then maintained until each of the switching elements turns off in the following frame. In this case, increasing of the electric potential of the first retentive capacity wiring is in sync with decreasing of the electric potential of the second retentive capacity wiring, or decreasing of the electric potential of the first retentive capacity wiring is in sync with increasing of the electric potential of the second retentive capacity wiring. Alternatively, increasing of the electric potential of the first retentive capacity wiring and decreasing of the electric potential of the second retentive capacity wiring are shifted by one horizontal period, or decreasing of the electric potential of the first retentive capacity wiring and increasing of the electric potential of the second retentive capacity wiring are shifted by one horizontal period.
The display device of the present invention may be arranged such that the first switching element and the second switching element are connected to the first and the second scan signal lines, respectively. In this case, an on-pulse signal applied to the first scan signal line and an on-pulse signal applied to the second scan signal line may not temporally overlap, or may overlap for a certain period of time but become in their off-states at different timing, respectively.
For example, the on-pulse signal applied to the first scan signal line and the on-pulse signal applied to the second scan signal line simultaneously become in their on-states but the on-pulse signal applied to the first scan signal line becomes in its off-state earlier than the on-pulse signal applied to the second scan signal line. Also, an electric potential applied to the data signal line changes in sync with timing at which one of the on-pulse signals becomes in its off-state earlier than the other or after the timing. As a result, the second sub-pixel electrode, which is connected to the second switching element controlled by the second scan signal line, is charged in a good condition because after an electric potential is once applied to the second sub-pixel electrode, an electric potential to be written is applied to the second sub-pixel electrode. This is especially effective (i) in cases where the polarity of the signal potential applied to the data signal line is inverted for every horizontal period (namely, in cases where a distortion of the signal potential is large), such as the dot inversion driving and the H line inversion driving or (ii) in cases where the second sub-pixel electrode has a large area (namely, in cases where it takes long for charging to be carried out). Further, it is possible to suppress a driving frequency of the scan signal because the on-pulse signal has a longer cycle.
Note that the polarity of the same data signal line is inverted for every horizontal period.
In the display device of the present invention, the first switching element and the second switching element may be connected to independent first and second data signal lines, respectively. In this case, the first luminance area and the second luminance area are formed by applying different signal electric potentials to the first and the second data signal lines, respectively.
The active matrix substrate of the present invention includes a plurality of pixel regions. Each of the pixel regions includes a first switching element, a second switching element, a first sub-pixel electrode connected to the first switching element, a second sub-pixel electrode which surrounds the first sub-pixel electrode and is connected to the second switching element.
When the active matrix substrate of the present invention is used for a display device, it is possible to form a high luminance area and a low luminance area which surrounds the low luminance area in each pixel corresponding to each pixel region. Namely, this causes the high luminance area to deal with the total luminance or substantially the total luminance of an entire pixel (the light irradiation is carried out from the center part of a pixel) so that most of gradation displays are carried out. Thus, the display device including this active matrix substrate can clearly display an image having a high spatial frequency because of a great improvement in transfer characteristic in a high spatial frequency area.
The active matrix substrate of the present invention may be arranged such that the first switching element and the second switching element are connected to the same scan signal line. Alternatively, the first switching element and the second switching element may be connected to independent first and second data signal lines, respectively.
The active matrix substrate of the present invention may include a data signal line provided to each of the pixel regions, the first and second switching elements being connected to the single data signal line, a first retentive capacity wiring, the first sub-pixel electrode and the first retentive capacity wiring defining capacitance, a second retentive capacity wiring, the second sub-pixel electrode and a second retentive capacity wiring defining capacitance.
The active matrix of the present invention substrate may include a data signal line provided to each of the pixel regions, the first and second switching elements being connected to the single data signal line, a first retentive capacity wiring, the first sub-pixel electrode and the first retentive capacity wiring defining capacitance, a second retentive capacity wiring, the second sub-pixel electrode and a second retentive capacity wiring defining capacitance.
The active matrix substrate of the present invention may include independent first and second data signal lines provided to the pixel regions respectively, the first data signal line connected to the first switching element, and the second signal line connected to the second switching element.
In the active matrix substrate of the present invention, a light-shielding body may be provided so that the light-shielding body, a boundary area between the first sub-pixel electrode and the second sub-pixel electrode overlap each other. Thus, it is possible to avoid a decline in contrast due to leakage of light from (gap area) in the vicinity of the boundary area between the first and second pixel electrodes. Further, in an active matrix substrate including a light shielding body, no decline occurs in light-shielding effect due to the misalignment in combining of a color filter substrate like in cases where a light-shielding body is provided on a color filter substrate. Note that a part of the wiring from the first switching element or the second switching element and a boundary area between the first sub-pixel electrode and the second sub-pixel electrode may overlap each other. Also, a part of the scan signal line and a boundary area between the first sub-pixel electrode and the second sub-pixel electrode may overlap each other. In this case, the scan signal line may be wired in a middle part of a pixel in a frame shape so that the scan signal line and the boundary area overlap each other. Note that a part of the first retentive capacity wiring and a boundary area between the first sub-pixel electrode and the second sub-pixel electrode may overlap each other. In this case, the first retentive capacity wiring may be wired in a middle part of a pixel in a frame shape so that the first retentive capacity wiring and the boundary area overlap each other.
Also, a display device of the present invention is characterized by including the active matrix substrate.
Also, a liquid crystal display device of the present invention including the active matrix substrate, a back light radiating a plurality of colors in a time division, and this liquid crystal display device is characterized by performing a field sequential display. With this structure, for example, three primary colors (R, G, and B) are displayed in one pixel consecutively (two or more colors will never be displayed at a time). This structure allows the display quality to be improved because there is no dislocation of the color information. Further, this allows the cost reduction because no color filter is required.
A television receiver of the present invention is characterized by including the display device, and a tuner member for receiving the television broadcasting.
As explained above, the display device of the present invention can clearly display an image having a high spatial frequency. Also, when this active matrix substrate is used for a display device, it is possible to form a high luminance area and a low luminance area which surrounds the high luminance area in each pixel corresponding to each pixel region so that an image having a high spatial frequency can be displayed clearly.
The following description deals with an embodiment of the present invention with reference to the
Each of the pixel regions 5 includes a first TFT (Thin Film Transistor) 12a, a second TFT 12b, a first sub-pixel electrode 17a, and a second sub-pixel electrode 17b.
The second sub-pixel electrode 17b has a rectangular shape which is hollowed out to have a hollow part. The second sub-pixel electrode 17b has (i) an outer rim 17x which has a big rectangular shape and (ii) an inner rim (outer rim of the hollow part) 17y which has a small rectangular shape. Inside the inner rim 17y, there is provided the first sub-pixel electrode 17a having a rectangular shape. Namely, an active matrix substrate of the present embodiment has a structure in which the first sub-pixel electrode 17a is surrounded by the second sub-pixel electrode 17b.
There is provided a gap area 26 between an outer rim 17z of the first sub-pixel electrode 17a and the inner rim 17y of the second sub-pixel electrode 17b. The first retentive capacity wiring 20 is wired in a frame shape so that the first retentive capacity wiring 20, the gap area 26, an adjacent area of the outer rim of the first sub-pixel electrode 17a, and an adjacent area of the inner rim of the second sub-pixel electrode 17b overlap each other. Also, an upper electrode 30a for forming a retentive capacity is provided so that the upper electrode 30a, the first retentive capacity wiring 20 and the first sub-pixel electrode 17a overlap each other. The upper electrode 30a and the first sub-pixel electrode 17a are connected via a contact hole 11a. Also, (i) a lower end part of the second sub-pixel electrode 17b (one end part in the column direction) and (ii) a scan signal line 16 which is provided to extend in a row direction (in a transverse direction in the figure) overlap each other. With the arrangement, the first retentive capacity wiring 20 allows a black display area (lowest luminance area) to be formed in a flame shape between the high luminance area 47a (first luminance area) and the low luminance area 47b (second luminance area).
A first TFT 12a and a second TFT 12b are provided in the vicinity of each intersection of a data signal line 15 and a scan signal line 16. A source electrode 9a of the first TFT 12a and a source electrode 9b of the second TFT 12b are connected to a data signal line 15. A drain electrode 8a of the first TFT 12a is connected to the upper electrode 30a via a drain lead-out wiring 7a, and a drain electrode 8b of the second TFT 12b is connected to the second sub-pixel electrode 17b via a drain lead-out wiring 7b and a contact hole 11b.
Further, the second retentive capacity wiring 21 is provided so as to get across a part of an upper part of the second sub-pixel electrode 17b (provided on an opposite side where the TFT 12a and TFT 12b are provided, with respect to the first pixel electrode 17a) in a row direction (in a transverse direction in the figure). An upper electrode 30b for forming a retentive capacity is provided so that the upper electrode 30b, the second retentive capacity wiring 21 and the second sub-pixel electrode 17b overlap each other. The upper electrode 30b is connected to the second sub-pixel electrode 17b via a contact hole 11c.
A circuit illustrated in
As described later, Cs signals (auxiliary capacitance counter voltage) having different phases are applied to the first retentive capacity wiring 20 and the second retentive capacity wiring 21 in
The following description deals with a driving method of a liquid crystal display device in accordance with an embodiment of the present invention.
In an embodiment of the present invention, a display signal voltage is applied, via a single data signal line, to the first sub-pixel electrode and the second sub-pixel electrode, which surrounds the first sub-pixel electrode. Thereafter, while turning off the each TFT, the voltages of the first and second retentive capacity wiring are changed so as to be different from each other. As a result, each pixel includes a high luminance area caused by a first sub-pixel capacitance Csp1 and a low luminance area caused by a second sub-pixel capacitance Csp2. The high luminance area is surrounded by the low luminance area. With this arrangement, a single data signal line supplies a display signal voltage to two sub-pixel electrodes. This gives rise to the following advantage. Namely, it is not necessary to increase the number of data signal lines and the number of source drivers for driving the data signal lines.
The following description deals with how each voltage waveform in the n-th frame in
Firstly, it is assumed that, at time T0, Vcs1=(Vcom−Vad) and Vcs2=(Vcom+Vad) are satisfied. Note that Vcom is a voltage of a counter electrode.
At time T1, Vg is changed from VgL to VgH and each TFT turns on. As a result, Vlc1 and Vlc2 increase to Vsp. Retentive capacitances Cs1, Cs2 and sub-pixel capacitances Csp 1, Csp 2 are charged, respectively.
At time T2, Vg is changed from VgH to VgL, and each TFT turns off. The retentive capacitances Cs1, Cs2 and sub-pixel capacitances Csp1, Csp2 are electrically insulated from a data signal line. Right after this, pull-in effect is caused by the influence of a parasitic capacity or other influence. As a result, the following equations are satisfied: Vlc1=(Vsp−Vd1), and Vlc2=(Vsp−Vd2).
At time T3, Vcs1 is changed from (Vcom−Vad) to (Vcom+Vad), and Vcs2 is changed from (Vcom+Vad) to (Vcom−Vad). As a result, the following equations are satisfied: Vlc1=(Vsp−Vd1+2×K×Vad), and Vlc2=(Vsp−Vd2−2×K×Vad). Note that K=Ccs/(Clc+Ccs) is satisfied, where Ccs is a capacity value of each retentive capacitance (Cs1 and Cs2), and Clc is a capacity value of each sub-pixel capacitance (Csp1 and Csp2).
At time T4, Vsc1 is changed from (Vcom+Vad) to (Vcom−Vad), and Vcs2 is changed from (Vcom−Vad) to (Vcom+Vad). As a result, the following equations are satisfied: Vlc1=(Vsp−Vd1), and Vlc2=(Vsp−Vd2).
At time T5, Vsc1 is changed from (Vcom−Vad) to (Vcom+Vad), and Vsc2 is changed from (Vcom+Vad) to (Vcom−Vad). As a result, the following equations are satisfied: Vlc1=(Vsp−Vd1+2×K×Vad), and Vlc2=(Vsp−Vd2−2×K×Vad).
After that, the processes made during time T4 and time T5 are repeated for every integral multiple of a horizontal scan period 1H until the next satisfying of Vg=Vgh causes the writing to be carried out. Therefore, Vlc1 has an effective value of (Vsp−Vd1+K×Vad) and Vlc2 has an effective value of (Vsp−Vd2−K×Vad).
According to this, effective voltages (V1 and V2) applied, during the n-th frame, to the respective sub-pixel capacitance (first sub-pixel capacitance Csp1 and second sub-pixel capacitance Csp2) become V1=(Vsp−Vd1+K×Vad−Vcom) and V2=(Vsp−Vd2−K×Vad−Vcom), respectively. This causes formation of (i) a high luminance area caused by the first sub-pixel capacitance Csp1 and (ii) a low luminance area caused by the second sub-pixel capacitance Csp2, which low luminance area surrounds the high luminance area.
The following description deals with how each voltage waveform in the (n+1)-th frame changes over time.
Firstly, it is assumed that, at time T0, Vcs1=(Vcom+Vad) and Vcs2=(Vcom−Vad) are satisfied. Note that Vcom is a voltage of a counter electrode.
At time T1, Vg is changed from VgL to VgH, and each TFT turns on. As a result, Vlc1 and Vlc2 fall to Vsn. Retentive capacitances Cs1, Cs2 and sub-pixel capacitances Csp1, Csp2 are changed, respectively.
At time T2, Vg is changed from VgH to VgL and each TFT turns off. The retentive capacitances Cs1, Cs2 and the sub-pixel capacitances Csp1, Csp2 are electrically insulated from a data signal line. Right after this, pull-in effect caused by the influence of a parasitic capacity or other influence. As a result, the following equations are satisfied: Vlc1=(Vsn−Vd1), and Vlc2=(Vsn−Vd2).
At time T3, Vcs1 is changed from (Vcom+Vad) to (Vcom−Vad), and Vcs2 is changed from (Vcom−Vad) to (Vcom+Vad). As a result, the following equations are satisfied: Vlc1=(Vsn−Vd1+2×K×Vad), and Vlc2=(Vsn−Vd2−2×K×Vad). Note that K=Ccs/(Clc+Ccs) is satisfied, where Ccs is a capacity value of each retentive capacitance (Cs1 and Cs2), and Clc is a capacity value of each sub-pixel capacitance (Csp1 and Csp2).
At time T4, Vcs1 is changed from (Vcom−Vad) to (Vcom+Vad) and Vcs2 is changed from (Vcom+Vad) to (Vcom−Vad). As a result, the following equations are satisfied: Vlc1=(Vsn−Vd1), and Vlc2=(Vsn+Vd2).
At time T5, Vcs1 is charged from (Vcom+Vad) to (Vcom−Vad) and Vcs 2 is charged from (Vcom−Vad) to (Vcom+Vad). As a result, the following equations are satisfied: Vlc1=(Vsn−Vd1−2×K×Vad), and Vlc2=(Vsn−Vd2+2×K×Vad).
After that, the process made during time T4 and time T5 are repeated for every integral multiple of a horizontal scan period 1H until the next satisfying of Vg=Vgh causes the writing to be carried out. Therefore, Vlc1 has an effective value of (Vsn−Vd1−K×Vad) and Vlc2 has an effective value of (Vsn−Vd2+K×Vad).
According to this, effective voltages (V1 and V2) applied, during (n+1)-th frame, to the respective sub-pixel capacitance (Csp1 and Csp2) become V1=(Vsn−Vd1−K×Vad−Vcom) and V2=(Vsn−Vd2+K×Vad−Vcom), respectively. This causes formation of (i) a high luminance area caused by the first sub-pixel capacitance Csp1 and (ii) a low luminance area caused by the second sub-pixel capacitance Csp2, which low luminance area surrounds the high luminance area.
As illustrated in
Further, as illustrated in
The following description deals with how each voltage waveform changes over time in the n-th frame in
It is assumed that at time T0, Vcs1=(Vcom−Vad) and Vcs2=(Vcom+Vad) are satisfied. Note that Vcom is a voltage of the counter electrode.
At time T1, Vg is changed from VgL to VgH, and each TFT turns on. As a result, Vlc1 and Vlc2 rise to Vsp. Retentive capacitances Cs1, Cs2 and sub-pixel capacitances Csp1, Csp2 are charged, respectively.
At time T2, Vg is changed from VgH to VgL, and each TFT turns off. The retentive capacitances Cs1, Cs2 and the sub-pixel capacitances Csp1, Csp2 are electrically insulated from a data signal line, respectively. Right after this, a pull-in effect is caused by the influence of a parasitic capacity or other influence. As a result, the following equations are satisfied: Vlc1=(Vsp−Vd1), and Vlc2=(Vsp−Vd2).
At time T3, Vcs1 is changed from (Vcom−Vad) to (Vcom+Vad). At time T4 (one horizontal period later from T3), Vcs2 is changed from (Vcom+Vad) to (Vcom−Vad). As a result, the following equations are satisfied: Vlc1=(Vsp−Vd1+2×K×Vad), and Vlc2=(Vsp−Vd2−2×K×Vad). Note that K=Ccs/(Clc+Ccs) is satisfied, where Ccs is a capacitance value of each retentive capacitance (Cs1 and Cs2), and Clc is a capacitance value of each sub-pixel capacitance (Csp1 and Csp2).
According to this, effective voltages (V1 and V2) to be applied during the n-th frame to respective sub-pixel capacitance (first sub-pixel capacitance Csp1 and second sub-pixel capacitance Csp2) satisfy V1=(Vsp−Vd1+2×K×Vad−Vcom), and V2=(Vsp−Vd2−2×K×Vad−Vcom). This causes a high luminance area caused by the first sub-pixel capacitance Csp1 and a low luminance area caused by the second sub-pixel capacitance Csp2 to be formed within a single pixel.
With the arrangement, the round waveforms of Vcs1 and Vcs2 less affect the drain effective electric potential, thereby having a beneficial effect on a reduction in luminance unevenness.
One example of the luminance distribution between the high luminance area and the low luminance area in the structure of the present embodiment is illustrated in
Thus, according to a liquid crystal display device of the present embodiment, it is possible to provide in each pixel a low luminance area and a high luminance area surrounded by the low luminance area. The following description deals with how an image having a high spatial frequency can be clearly displayed by the structure in which each pixel has a high luminance area and a low luminance area surrounding the high luminance area.
As is clear from
As illustrated in
In the active matrix substrate illustrated in
Also, in the present embodiment, an active matrix substrate includes a light-shielding body (a first retentive capacity wiring 20). As such, no decline occurs in light-shielding effect due to the misalignment in combining of substrates like in cases where a light-shielding body is provided on a color filter substrate.
Further, according to the structure in
An active matrix substrate may have a structure illustrated in
The second sub-pixel electrode 117b has a rectangular shape which is hollowed out to have a hollow part. The second sub-pixel electrode 117b has (i) an outer rim 117x which has big rectangular shape and (ii) an inner rim (outer rim of the hollowed out) 117y which has a small rectangular shape. Inside the inner rim 117y, there is provided the first sub-pixel electrode 117a having a rectangular shape. Namely, an active matrix substrate of the present embodiment has a structure in which the first sub-pixel electrode 117a is surrounded by the second sub-pixel electrode 117b.
Between an outer rim 117z of the first sub-pixel electrode 117a and the inner rim 117y of the second sub-pixel electrode 117b, there is provided a gap area (126a through 126d). The gap area 126 has a frame shape including (i) the areas 126a and 126b, which are provided to extend in a row direction (in a transverse direction in
The first TFT 112a and the second TFT 112b are provided in the vicinity of each intersection of a data signal line 15 and a scan signal line 16. A source electrode 109a of the first TFT 112a and a source electrode 109b of the second TFT 112b are connected to the data signal line 15. A drain electrode 108a of the first TFT 112a is connected to the upper electrode 130a via a drain lead-out wiring 107a. The drain lead-out wring 107a is wired so that the drain lead-out wring 107a, the area 126c extending in a column direction (in an up-and-down direction in
As illustrated in
A circuit illustrated in
It is possible to arrange an active matrix substrate of the present embodiment as illustrated in
The second sub-pixel electrode 217b has a rectangular shape which is hollowing out to have a hollow part. The second sub-pixel electrode 217b has (i) an outer rim 217x which has a big rectangular shape and (ii) an inner rim (outer rim of the hollow part) 217y has a small rectangular shape. Inside the inner rim 217y, there is provided the first sub-pixel electrode 217a. Namely, an active matrix substrate of the present embodiment has a structure in which the first sub-pixel electrode 217a is surrounded by the second sub-pixel electrode 217b.
In the arrangement, there is provided a scan signal line 216 in the center part of the pixel area 205. The scan signal line 216 in the pixel area 205 includes three sections, i.e., a left side section 216a as a gate electrode of the first TFT 212a and the second TFT 212b, a frame section 216b, and a right side section 216c. The first and second TFT 212a and 212b are provided in the vicinity of an intersection of a data signal line 15 and a scan signal line 216. A source electrode 209a of the first TFT 212a and a source electrode 209b of the second TFT 212b are connected to the data signal line 15.
There is provided a gap area 226 between an outer rim 217z of the first sub-pixel electrode 217a and the inner rim 217y of the second sub-pixel electrode 217b. A scan signal line 216 is wired so that the gap area 226, an adjacent area of the outer rim of the first sub-pixel electrode 217a, and an adjacent area of the inner rim of the second sub-pixel electrode 217b overlap each other. This allows the frame section 216b to be formed. A drain electrode 208a of the first TFT 212a is connected to the first sub-pixel electrode 217a via a drain lead-out wiring and a contact hole 211a.
Also, edges of the pixel area 205 (both edges in a column direction), first and second retentive capacity wiring 220 and 221 are provided in a row direction (in a transverse direction in
According to the structure in
A circuit illustrated in
It is possible to arrange an active matrix substrate of the present embodiment as illustrated in
In the arrangement, two data signal lines 315a and 315b are provided for a single pixel area 305. The data signal lines 315a and 315b are provided in the vicinity of end parts on both sides of the pixel area 305 in a column direction (in an up-and-down direction in
The second sub-pixel electrode 317b has a shape which is defined by hollowing out a rectangle part from the pixel region 305. The second sub-pixel electrode 317b has (i) an outer rim 317x which has a big rectangular shape and (ii) an inner rim (the rectangle part thus hollowed out) 317y which has a small rectangular shape. Inside the inner rim 317y, there is provided the first sub-pixel electrode 317a having a rectangular shape. Namely, an active matrix substrate of the present embodiment has a structure in which the first sub-pixel electrode 317a is surrounded by the second sub-pixel electrode 317b.
There is provided a gap area 326 between an outer rim 317z of the first sub-pixel electrode 317a and an inner rim 317y (the rectangle part thus hollowed out) of the second sub-pixel electrode 317b. A retentive capacity wiring 320 is wired in a frame shape so that the gap area 326, an adjacent area of the outer rim of the first sub-pixel electrode 317a, and an adjacent area of the inner rim of the second sub-pixel electrode 317b overlap each other. Further, an upper electrode 330a is provided so that the retentive capacity wiring 320 and the first sub-pixel electrode 317a overlap each other. This upper electrode 330a is connected to the first sub-pixel electrode 317a via a contact hole 311a. Also, an upper electrode 330b is provided so that the retentive capacity wiring 320 and the second sub-pixel electrode 317b overlap each other. The upper electrode 330b is connected to the second sub-pixel electrode 317b via a contact hole 311b.
The first TFT 312a is provided in the vicinity of an intersection of a scan signal line and the data signal line 315a. A source electrode 309a of the first TFT 312a is connected to the data signal line 315a, and a drain electrode 308a of the first TFT 312a is connected to the upper electrode 330a, via a drain lead-out wiring. Also, the second TFT 312b is provided in the vicinity of an intersection of a scan signal line and the data signal line 315b. A source electrode 309b of the second TFT 312b is connected to the data signal line 315b, and a drain electrode 308b of the second TFT 312b is connected to the upper electrode 330b, via a drain lead-out wiring.
A circuit illustrated in
It is also possible, as illustrated in
It is possible to arrange an active matrix substrate of the present embodiment as illustrated in
The pixel region 405 includes a first TFT 412a, a second TFT 412b, a first sub-pixel electrode 417a, and a second sub-pixel electrode 417b. The second sub-pixel electrode 417b has a shape which is defined by hollowing out a rectangle part from the pixel region 405. The second sub-pixel electrode 417b has (i) an outer rim 417x which has a big rectangular shape and (ii) an inner rim (the rectangle part thus hollowed out) 417y which has a small rectangular shape. Inside the inner rim 417y, there is provided the first sub-pixel electrode 417a having a rectangular shape. Namely, an active matrix substrate of the present embodiment has a structure in which the first sub-pixel electrode 417a is surrounded by the second sub-pixel electrode 417b.
The retentive capacity wiring 420 is wired across a center part of a pixel region. An upper electrode 430b is provided so that the upper electrode 430b, the retentive capacity wiring 420 and the second sub-pixel electrode 417b overlap each other. An upper electrode 430a is provided so that the upper electrode 430a, the retentive capacity wiring 420 and the first sub-pixel electrode 417a overlap each other.
The first TFT 412a is provided in the vicinity of an intersection of a data signal line 15 and a first scan signal line 16a, and the first scan signal line 16a serves as a gate electrode of the first TFT 412a. The second TFT 412b is provided in the vicinity of an intersection of a data signal line 15 and a second scan signal line 16b, and the second scan signal line 16b serves as a gate electrode of the second TFT 412b. A source electrode of the first TFT 412a and a source electrode of the second TFT 412b are connected to the data signal line 415.
Further, a drain electrode of the first TFT 412a is connected to the upper electrode 430a, via a drain lead-out wiring 407a. The upper electrode 430a is connected to the first sub-pixel electrode 417a, via a contact hole 411a. Also, a drain electrode of the second TFT 412b is connected to the upper electrode 430b via a drain lead-out wiring 407b, and the upper electrode 430b is connected to the second sub-pixel electrode 417b, via a contact hole 411b.
A circuit illustrated in
As shown in
Alternatively, in cases where the circuit in
Namely, during a horizontal period, on-pulse signals (scan signals) are applied to the first scan signal line 416a and the second scan signal line 416b, respectively. In response to the on-pulse signals, signal electric potentials v1 and v2 (each having a negative polarity) are applied to the data signal line 415. At this time, the on-pulse signals applied to the first and second scan signal lines, respectively, are set so that (i) they partially overlap each other for a certain period of time and (ii) become in their off-states at different timing, respectively. For example, these two on-pulse signals are set so that (i) they simultaneously become in their on-states and (ii) the on-pulse signal applied to the first scan signal line 416a becomes in its off-state earlier than that applied to the second scan signal line 416b. For example, these two on-pulse signals become in their off-states so as to differ in phase by ½H (a half of one horizontal period). Further, an electric potential applied to the data signal line 415 is set so that (1) it is changed into v1 either (i) in sync with the timing at which the two on-pulse signals become in their on-states or (ii) before the timing and then (2) the v1 is changed into v2 either (a) in sync with the timing at which one of the two on-pulse signals (the on-pulse applied to the first scan signal line 416a) becomes in its off-state earlier than the other or (b) after the timing. This causes (i) v1 to be written in the first sub-pixel electrode 417a and (ii) v2 to be rewritten in the second sub-pixel electrode 417b after v1 is written in the second sub-pixel electrode 417b. Further, in the following horizontal period, the on-pulse signals are applied to the first and second scan signal lines 416c and 416d of the next stage at the above timing. In response to the respective on-pulse signals, signal electric potentials V1 and V2 (each having a positive polarity) are applied to the data signal line 415. Namely, V1 is changed into V2 either (a) in sync with the timing at which the on-pulse signal applied to the first scan signal line 416a becomes in its off-state earlier than the other or (b) after the timing. This causes (i) V1 to be written in the first sub-pixel electrode 417c of the next stage and (ii) V2 to be rewritten in the second sub-pixel electrode 417d of the next stage after the V1 is written in the second sub-pixel electrode 417d.
This allows the second sub-pixel electrode 417b, which is connected to the second TFT 412b controlled by the second scan signal line 416b, to be charged in a good condition because, after the electric potential v1 (having a same polarity as a potential to be written) is once applied to the second sub-pixel electrode 417b, the electric potential v2 (an electric potential to be rewritten) is applied to the second sub-pixel electrode 417b. This is especially effective (i) in cases where the polarity of the signal potential applied to the data signal line 415 is inverted for every horizontal period (namely, in cases where a distortion of the signal potential is large), such as the dot inversion driving and the H line inversion driving or (ii) in cases where the second sub-pixel electrode 417b has a large area (namely, in cases where it takes long for charging to be carried out). A driving method shown in FIG. 33 can further achieve an effect that suppresses a driving frequency of the scan signal because the on-pulse signal has a longer cycle in the method of
A liquid crystal display panel is prepared by (1) combining an active matrix substrate obtained by the present embodiment and a color filter substrate including (i) a plurality of colored layers for Red, Green, and Blue colors which are provided in matrix so as to correspond to a respective one of pixels of the active matrix substrate and (ii) a black matrix for light-shielding which is provided so as to be alternately provided in the colored layers, and (2) injecting and sealing a liquid crystal.
A liquid crystal display panel thus prepared is illustrated in
The following description deals with a television receiver to which a liquid crystal display device of the present embodiment is applied.
Note that an active matrix substrate is applicable to a liquid crystal display device in which a field sequential method is adopted. One pixel in the filed sequential method illustrated in
The filed sequential method has an advantage that positions of color information for respective colors are identical to each other (respective colors are displayed in the middle portion of a pixel as illustrated in
As illustrated in
The television receiver 602 in which the liquid crystal display device 601 is used is realized by, for example the following arrangement. Specifically, as illustrated in
Note that the present invention is not limited to a liquid crystal display device. For example, it is possible to realize an organic EL display device by the following arrangement. Specifically, an organic EL panel is prepared by providing an organic EL layer between a color filter substrate and an active matrix substrate of the present invention which is provided so as to face the color filter substrate. Thereafter, a driver and the like are connected to an external lead-out terminal of the organic EL panel, thereby preparing. The present invention is not limited to a liquid crystal display device and an organic EL display device, provided that a display device is constituted by an active matrix substrate.
An active matrix substrate of the present invention is suitable for a device such as a liquid crystal television.
Number | Date | Country | Kind |
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2006-029043 | Feb 2006 | JP | national |
2006-248558 | Sep 2006 | JP | national |
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/JP2006/323966 | 11/30/2006 | WO | 00 | 7/16/2008 |