The present application claims priority over Japanese Application JP2008-312348 filed on Dec. 8, 2008, the contents of which are hereby incorporated into this application by reference.
(1) Field of the Invention
The present invention relates to a display device and an aging method, and in particular, to an aging method for an active matrix type display device using organic electroluminescent elements as light emitting elements.
(2) Description of the Related Art
Organic EL display devices with an active matrix using organic electroluminescent elements (hereinafter referred to as organic EL elements) as light emitting elements are expected to become next-generation flat panel displays.
In such active matrix type organic EL display devices, wires for transmitting a video voltage and current are wired in a matrix and a pixel circuit formed of a thin film transistor (hereinafter referred to as TFT), which is an active element, is built-in in each pixel, in addition to an organic EL element. The brightness of light emitted by the organic EL elements is adjusted by controlling the current supplied to the organic EL elements by the pixel circuits.
As for the pixel circuits for organic EL display devices, capacitor direct connection type pixels circuits where capacitor elements for holding a video voltage are connected to signal wires (JP2003-122301A) and capacitor separation type pixel circuits where capacitor elements are separated from signal wires by switching transistors (JP2008-40326A) are known.
Capacitor direct connection type pixel circuits do not require a switch element between signal wires and capacitor elements, and therefore, the number of TFT's is generally small, and thus, there is an advantage, such that the pixel circuits can be made compact. However, as shown in
Meanwhile, organic EL display devices require aging.
In organic EL display devices having a capacitor direct connection type pixel circuit, no write-in period (T-DW) is required, because no image is displayed during aging, and thus, as shown in
In conventional organic EL display devices having a capacitor direct connection type pixel circuit, however, an image voltage of the maximum level is written into one display line unit during the write-in period (T-DW), as shown in
The present invention is provided in order to solve the above described problems with the prior art, and an object of the present invention is to provide a technology that makes it possible to shorten the aging period in display devices and aging methods.
The above described and other objects, as well as novel features, of the present invention will become clearer from the description in the present specification and the accompanying drawings.
One typical invention from among the inventions described in the present application is briefly described below.
In order to achieve the above described object, the present invention is characterized in that a thin film transistor (first transistor) for aging which directly connects an organic EL element to a power supply line, and furthermore, an aging control line and a thin film transistor (second transistor) for switching aging control signals (second transistor) is provided for controlling the thin film transistor for aging.
During aging, the thin film transistor for switching aging control signals (second transistor) is turned on, so that a drive voltage for turning on the thin film transistor for aging is supplied to an aging control line, and the thin film transistor for aging is also turned on, and thus, the power supply line and the organic EL element are directly connected, and a current is supplied from the power supply line to an organic EL element for aging.
In addition, the thin film transistor (second transistor) for switching aging control signals is turned off and the thin film transistor for aging also turned off during normal operation, so that the organic EL element is detached from the power supply line and power is supplied to the organic EL element via the thin film transistor for driving the pixel, and thus, an image is displayed.
The effects of the typical invention from among the inventions disclosed in the present specification are briefly described below.
The display device and aging method according to the present invention make it possible to shorten the aging period.
In the following, the embodiments of the present invention are described in detail in reference to the drawings.
Here, the same symbols are used for components having the same function in all of the drawings for illustrating the embodiments, and the descriptions thereof are not repeated.
A number of pixels (PIX) are provided in a matrix within the display region on the organic EL display panel of the organic EL display device according to the present embodiment. A signal line 11, a reset line 12, a turn on switch line 13, a power supply line 14 and an aging control line 20 are connected to each pixel (PIX). The signal line 11, the reset line 12 and the turn on switch line 13 are connected to the below described drive circuit (DRV).
The drive circuit (DRV) supplies a drive voltage to the reset line 12 and the turn on switch line 13 and selects a display line. In addition, the drive circuit DRV converts digital video data supplied from outside the organic EL display panel to an analog video voltage in series, which is then supplied to the signal line 11.
All of the circuits; that is, all of the pixels and all of the drive circuits, are formed on a glass substrate (GLAS) using a low temperature polycrystal silicon thin film that is generally well-known. In addition, though a great number of pixels (PIX) are actually aligned within the display region on the organic EL display panel,
In addition, the pixels (PIX) are wired with a common ground line, not shown in the drawings.
Each pixel (PIX) has an organic electroluminescent element (hereinafter referred to as organic EL element) 1 as a light emitting element, and the cathode electrode of the organic EL element 1 is connected to a common electrode. In addition, the anode electrode is connected to a power supply line 14 via an n type thin film transistor for turning on (hereinafter referred to as turning on TFT) (Q3) and a p type thin film transistor (hereinafter referred to as drive TFT) (Q1).
The source electrode of the drive TFT (Q1) is connected to a power supply line 14, which is shared by all of the pixels (PIX). In addition, the gate electrode of the drive TFT (Q1) is connected to one of the signal lines 11 via a capacitor element (holding capacitor) (CS), and an n type thin film transistor for resetting (hereinafter referred to as reset switch) (Q2) is provided between the drain electrode and the gate electrode of the drive TFT (Q1). Here, the gate electrode of the reset switch (Q2) is connected to one of the reset lines 12. In addition, the gate electrode of the turning on TFT (Q3) is connected to one of the turning on switch lines 13.
Here, the drive TFT (Q1), the reset switch (Q2) and the turning on TFT (Q3) are all formed on a glass substrate using polycrystal silicon thin film transistors, where polysilicon is used for the semiconductor layers. Here, the method for manufacturing the polycrystal silicon thin film transistors and the organic EL element 1 is not greatly different from those generally known, and therefore, the descriptions thereof are omitted.
In the present embodiment also, one frame period that is set 1/60 seconds in advance is divided in two: a “write-in period” and a “light emitting period.”
In the following, write-in of a video voltage in each pixel (PIX) and the light emitting operation of the present embodiment are described in reference to the above
In
[Write-in Period]
At the time of write-in, an analog video voltage (Vdata) is supplied from the drive circuit DRV to the signal line 11 as a video voltage (VD).
Next, when the drive voltage (GW) and the drive voltage (GL) become of a high level (hereinafter referred to as H level) at time T0, the reset switch (Q2) and the turning on TFT (Q3) are turned on. As a result, the drive TFT (Q1) provides a diode connection through which the gate electrode and the drain electrode are connected, and the voltage of the gate electrode of the drive TFT (Q1) stored in the capacitor element (CS) in the previous frame is cleared.
Next, when the drive voltage (GL) becomes of a low level (hereinafter referred to as L level) at time T1, the turning on TFT (Q3) is turned off. As a result, the drive TFT (Q1) and the organic EL element 1 are forcibly made of such a state that the current is cut off, and at this time, the gate electrode and the drain electrode of the drive TFT (Q1) are connected through the reset switch (Q2), and therefore, the voltage of the gate electrode of the rive TFT (Q1), which is also one end of the capacitor element (CS) is automatically reset to a voltage that is lower than the voltage of the power supply line 14 by the threshold voltage (Vth).
Next, when the drive voltage (GW) becomes of the L level at time T2, the reset switch (Q2) is turned off, and the difference in potential between the two ends of the capacitor element (CS) is stored in the capacitor element (CS) as it is.
At this time, when the voltage value inputted in the capacitor element (CS) on the signal line side is higher than the analog video voltage Vdata, the drive TFT (Q1) is in an off state, while when the voltage value inputted in the capacitor element (CS) on the signal line 11 side is lower than the analog video voltage Vdata, the drive TFT (Q1) becomes of an on state.
Here, the turning on TFT (Q3) of the pixel (PIX) is always in an off state during the period when a pixel (PIX) on the display line in another row is being scanned, and therefore, the organic EL element 1 is not turned on, whether the analog video voltage of the signal line 11 is high or low.
Here, write-in of an analog video voltage for pixels is carried out one row at a time in sequence, as described above, and at the point in time when write-in is completed for all of the pixels, the “write-in” in one frame is completed.
[Light Emitting Period]
During the “light emitting period” in one frame, the drive voltage (GW) is at the L level and the drive voltage (GL) is at the H level, and therefore, the turning on TFT's (Q3) of all of the elements become of an on state at the same time. At this time, a triangular wave voltage is inputted into the signal line 11.
Here, the turning on TFT's (Q3) are always in an on state, and therefore, the organic EL element 1 in each pixel (PIX) is driven by the drive TFT (Q) in accordance with the relationship between the analog video voltage Vdata which is written in in advance and the triangular wave voltage supplied to the signal line 11.
[Aging Method]
The present embodiment is characterized in that an n type thin film transistor for aging (hereinafter referred to as first transistor) (Q10) and an aging control line 20 are provided within the pixel (PIX).
In the first transistor (Q10), the source electrode (or drain electrode) is connected to the anode electrode of the organic EL element 1 and the drain electrode (or source electrode) is connected to the power supply line 14. In addition, the gate electrode of the first transistor (Q10) is connected to the aging control line 20.
Meanwhile, in the peripheral portion of the organic EL display panel (region shown by arrow A in
In addition, the source electrode (or drain electrode) of an n type tin film transistor for switching aging control signals (hereinafter referred to as second transistor) (Q11) is connected to the aging control line 20.
Furthermore, the drain electrode (or source electrode) of the second transistor (Q11) is connected to the aging control signal line 21 and the gate electrode of the second transistor (Q11) is connected to the aging control signal switching signal line 22.
In the following, the aging method of the present embodiment is described. Here, in the present embodiment, aging is carried out before the drive circuit (DRV) is mounted.
In the present embodiment, an aging control switching signal (S-SE) at an H level is inputted at one end (TC) of the aging control signal switching signal line 22 during aging. As a result, as shown in
In addition, an aging control signal (S-CE) at an H level is inputted at one end (TB) of the aging control signal line 21 during aging. Accordingly, the aging control signal (S-CE) at an H level is inputted into the gate electrode of the first transistor (Q10) via the second transistor (Q11), and thus, the first transistor (Q10) is turned on.
As a result, as shown by arrow A in
Accordingly, as shown in
In addition, an aging control signal (S-CE) at an L level is inputted from the drive circuit (DRV) at one end (TA) of the aging control line 20 during normal operation after the drive circuit (DRV) formed of a semiconductor chip is mounted in accordance with a COG (chip on glass) method. Accordingly, as shown in
In addition, a current flows from the power supply line 14 through the organic EL element 1 via the drive TFT (Q1), as shown by arrow A in
In some cases, the organic EL element 1 has different optimal aging conditions for light of different colors: R (red), G (green) and B (blue).
In the present embodiment, as shown in
As shown in
Therefore, as shown in
In addition, an aging control signal (S-CE) at an L level is outputted from the terminal (T-SE) after a driving circuit (DRV) is mounted, and the first transistor (Q10) is turned off.
Here, in
In the present embodiment, aging is carried out on the basis of the aging control signal outputted from the drive circuit (DRV) after the drive circuit (DRV) is mounted, and therefore, the second transistor (Q11) is not necessary, and thus, the aging control signal switching signal line 22 and the aging control signal lines (21, 21R, 21G, 21B) are not necessary.
Therefore, as shown in
Here, in
In the case where a current is supplied from the power supply line 14 to the organic EL element 1 via the first transistor (Q10) during normal operation, the display quality lowers.
In order to prevent this, it is necessary to reduce the leak current of the aging TFT. In order to do so, it is preferable to use a thin film transistor of an nMOS type, which has little leak current, for the first transistor (Q10). In the present embodiment, two n type thin film transistors Q15 and Q16 are connected in series instead of the first transistor (Q10) so that the leak current is further reduced.
Though aging is usually carried out after a display panel is cut out to an appropriate size, in the present embodiment, as shown in
In the present embodiment, contact of the needle-like dedicated jig with the terminals is possible at the same time, and therefore, it is possible to increase the work efficiency for aging.
Here, though organic EL display devices having a capacitor direct connection type pixel circuit are described in the above embodiments, the present invention is not limited to these, and can be applied to the capacitor separation type pixel circuit described in the above JP2008-40326A.
Though the invention made by the present inventor is concretely described on the basis of the above embodiments, the present invention is not limited to these embodiments, and various modifications are, of course, possible within such a scope as not to deviate from the gist of the present invention.
Number | Date | Country | Kind |
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2008-312346 | Dec 2008 | JP | national |