Patent Application
20250218376
This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0194249, filed on Dec. 28, 2023, the disclosure of which is incorporated herein by reference in its entirety.
The present specification relates to a display device and a dimming method thereof, and more specifically, to a display device that adjusts the brightness of a screen using a duty ratio signal of which a pulse generation position within one frame is spread over time, and a dimming method thereof.
With the development of information technology, many related technologies are being developed in the field of display devices for displaying visual information as video or images. A display device includes a display panel including a plurality of sub pixels, a driving circuit supplying signals for driving the display panel, a power supply unit supplying power to the display panel, and the like, and the driving circuit includes a gate driving circuit and a data driving circuit supplying gate signals and data signals, respectively, to the display panel.
An emission time of a light emitting element may be adjusted using a pulse width modulation (PWM) method by adjusting an on-off duty ratio of an emission signal, which is a gate signal, and thus the brightness of a screen may be adjusted. The inventors of the present disclosure have recognized that when the display device is driven in this way, a position and a point in time of an on section of the emission signal within the display panel vary depending on the operation of a shift register of a gate-in-panel (GIP) circuit, where horizontal band noise is generated on the screen due to luminance deviation between pixel lines and the horizontal band noise has a predetermined position and width depending on the on-off duty ratio of the emission signal.
In order to address the various technical problems in the related art, including the technical problem described above, the present specification is directed to providing a display device for adjusting the brightness of a screen using a duty ratio signal of which a pulse generation position within one frame is spread over time and a dimming method thereof.
The specification disclosure is also directed to providing a display device for adjusting the brightness of a screen by applying a duty ratio signal of which a start position within one frame is moved over time to an emission signal, and a dimming method thereof.
The specification disclosure is also directed to providing a display device for adjusting the brightness of a screen by controlling a movement degree, a movement form, and a time interval of a start position of a duty ratio signal applied to an emission signal within one frame, and a dimming method thereof.
Problems to be solved by the present specification are not limited to those mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.
According to an aspect of the present specification, there is provided a dimming method including generating a first emission signal, generating a duty ratio signal based on a digital brightness value, generating a second emission signal by applying the duty ratio signal to the first emission signal, and adjusting an emission time of a light emitting element using the second emission signal, and a start position of the duty ratio signal within one frame is moved at regular time intervals.
According to another aspect of the present specification, there is provided a display device including a display panel including pixels, a gate driver configured to generate a gate signal including an emission signal and supply the gate signal to the pixels through gate lines, a data driver configured to generate a data signal and supply the data signal to the pixels through data lines, and a timing controller configured to control each of the gate driver and the data driver, and the timing controller generates a duty ratio signal of which a start position within one frame is moved at regular time intervals and adjusts an emission time of a light emitting element through a second emission signal obtained by applying the duty ratio signal to a first emission signal.
Details of other embodiments are included in the detailed description and drawings.
The above and other objects, features and advantages of the present disclosure will become more apparent to those of ordinary skill in the art by describing exemplary embodiments thereof in detail with reference to the accompanying drawings, in which:
Advantages and features of the present disclosure, and methods for achieving the advantages and features will be clarified with reference to embodiments described below in detail together with the accompanying drawings. However, the present disclosure is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms. The present embodiments are only provided to allow disclosure of the present disclosure to be complete, and to completely inform those skilled in the art to which the present disclosure belongs of the scope of the disclosure, and the present disclosure is merely defined by the scope of the claims.
The shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings for describing embodiments of the present disclosure are illustrative, and the present disclosure is not limited to the matters illustrated. Like reference numerals refer to like elements throughout the specification. Furthermore, in describing the present disclosure, when it is determined that the detailed description of the related known technology may obscure the subject matter of the present disclosure, the detailed description thereof will be omitted. When “include,” “have,” “comprise,” etc., mentioned in the present specification are used, other parts may be added unless “only” is used. In describing a component in the singular, cases where the component is plural are included unless expressly stated otherwise.
In interpreting a component, the component is interpreted as including an error range even with no explicit description.
In describing a position relationship, for example, when a position relation between two parts is described as “on,” “over,” “under,” or “next to,” one or more other parts may be disposed between the two parts unless “just” or “directly” is used.
In describing a time relationship, for example, when the temporal order is described as “after,” “subsequent to,” “next to,” or “before,” a case where the time relationship is not a continuous one may be included unless “just” or “immediately” is used.
Features of various embodiments of the present specification may be partially or fully coupled or combined with each other and may be variously inter-operated and driven technically, and embodiments may be carried out independently of each other or may be carried out together in a related manner.
Hereinafter, a display device and a dimming method thereof according to an embodiment of the present specification will be described with reference to the accompanying drawings.
As illustrated in
The image supply unit 110 performs image processing on a data signal and outputs the processed signal together with a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, a clock signal, and the like. The image supply unit 110 supplies the vertical synchronization signal, the horizontal synchronization signal, the data enable signal, the clock signal, the data signal, and the like to the timing controller 120.
The timing controller 120 receives the data signal and the like from the image supply unit 110, and outputs a gate timing control signal GDC for controlling operation timing of the gate driver 130 and a data timing control signal DDC for controlling operation timing of the data driver 140. The timing controller 120 supplies a data signal DATA together with the data timing control signal DDC to the data driver 140.
The timing controller 120 may receive a digital brightness value (DBV), which is information about current driving brightness of the display panel 150 and calculate a duty ratio of a duty ratio signal to be generated and an on time within one frame, that is, an on-pulse time of the duty ratio signal. In addition, the duty ratio signal may be generated based on time information.
The gate driver 130 outputs the gate signal while shifting a level of a gate voltage in response to the gate timing control signal (GDC) supplied from the timing controller 120. The gate driver 130 includes a level shifter and a shift register.
The gate driver 130 supplies the gate signal to the sub-pixels SP included in the display panel 150 through gate lines GL1 to GLm. The gate driver 130 may be formed on the display panel 150 in a gate-in panel method or in the form of an integrated circuit (IC). A part of the gate driver 130 formed using the gate-in-panel method is a shift register.
The gate driver 130 may generate an emission (EM) signal, which is one of the gate signals, and may generate an EM duty ratio signal through combination with the duty ratio signal for controlling the emission time of the light emitting element using a pulse width modulation (PWM) method.
The data driver 140 samples and latches the data signal DATA in response to the data timing control signal DDC supplied from the timing controller 120, converts the digital signal into an analog signal corresponding to the gamma voltage, and outputs the converted signal. The data driver 140 supplies the data signal to the sub-pixels SP included in the display panel 150 through data lines DL1 to DLn. The data driver 140 may be formed in the form of an integrated circuit (IC).
The data driver 140 converts the pixel data of an input image, which is digital data, using a digital to analog converter (hereinafter referred to as a “DAC”) and generates an analog data voltage. The DAC receives the pixel data, which is digital data, and receives a gamma reference voltage from a gamma voltage generation circuit in a power supply unit. The data driver 140 uses a voltage dividing circuit to generate the gamma reference voltage as a gamma compensation voltage corresponding to each gray level of pixel data. The DAC disposed in each channel of the data driver 140 outputs a data voltage by converting the pixel data into the gamma compensation voltage through a switch element array for selecting a voltage corresponding to a bit of the pixel data.
The display panel 150 displays images corresponding to gate signals and data signals output from driving circuits including the gate driver 130 and the data driver 140. The display panel 150 is implemented in a flat shape, a curved shape, or a flexible shape depending on the material of a substrate. The display panel 150 includes a display region defined by a plurality of pixels and a non-display region where various signal wires, pads, or the like are formed. A plurality of pixels defined by a plurality of data lines DL1 to DLn and a plurality of gate lines GL1 to GLm are arranged in the display region of the display panel 150, and one pixel includes a plurality of sub-pixels SP. The sub-pixels SP include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, or include a white sub-pixel, a red sub-pixel, a green sub-pixel, and a blue sub-pixel. The sub-pixels SP may have one or more different emission areas depending on the emission characteristics.
A pixel array of the display panel 150 may be provided with a plurality of horizontal pixel lines, and on each horizontal pixel line, a plurality of pixels that are horizontally adjacent and commonly connected to the gate lines may be disposed. Here, each of the horizontal pixel lines may not be a physical signal line, but may be a pixel block of one line implemented by horizontally neighboring pixels.
A compensation circuit 10 may include a plurality of switch elements and a capacitor. The compensation circuit 10 receives a data voltage Vdata, a scan signal SCAN (e.g., SCAN1, SCAN2, etc.), and an emission signal EM of the pixel data, applies the data voltage Vdata to a gate electrode of a driving element DT, and adjusts the emission time of the light emitting element EL in response to the emission signal.
The compensation circuit 10 may sense a threshold voltage of the driving element DT, compensate for a deviation in the threshold voltage of the driving element DT between sub-pixels, and compensate for changes in the threshold voltage of the driving element DT. One example of the compensation circuit 10 may be the circuit illustrated in
Referring to
The transistors T1 to T5 and DT may be implemented as p-channel transistors, but are not limited thereto. The transistors T1 to T5 and DT include switch elements T1 to T5 and a driving element DT. Each of the switch elements T1 to T5 may be turned on in response to a gate-on voltage VGL and turned off in response to a gate-off voltage VGH.
A driving period of the pixel circuit may be divided into an initialization time Ti during which major nodes n1 to n4 and the capacitor Cst are initialized, a sensing time Ts during which the data voltage Vdata of the pixel data compensated by a threshold voltage Vth of the driving clement DT is charged in the capacitor Cst, and an emission time Tem during which the light emitting element EL is driven by the driving element DT. As illustrated in
The driving element DT drives the light emitting element EL by supplying current to the light emitting element EL according to a gate-source voltage Vgs. The driving element DT includes a gate electrode connected to a second node n2, a first electrode connected to a first power line PL1, and a second electrode connected to a third node n3. A pixel driving voltage EVDD is commonly supplied to the pixels through the first power line PL1.
The light emitting element EL may be implemented as an organic light emitting diode (OLED). The light emitting element EL includes an anode electrode, a cathode electrode, and an organic compound layer formed between the electrodes. The anode electrode of the light emitting element EL is connected to a fourth node n4, and the cathode electrode is connected to a second power line PL2 to which a pixel base voltage EVSS is applied. The organic compound layer may include a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL), but is not limited thereto. When a voltage is applied to the anode electrode and the cathode electrode of the light emitting clement EL, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the emission layer (EML) to form excitons. At this time, visible light is emitted from the emission layer (EML). The light emitting element EL may be implemented in a tandem structure in which a plurality of emission layers is stacked. A tandem-structured light emitting element EL may improve the brightness and lifespan of a pixel.
The capacitor Cst is connected between a first node n1 and the second node n2. The capacitor Cst is charged with a data voltage Vdata compensated by the threshold voltage Vth of the driving element DT.
A first switch element T1 supplies the data voltage Vdata to the first node n1 in response to a gate-on voltage VGL of a first gate signal SCAN1. The first switch element T1 includes a gate electrode connected to a first gate line GL1, a first electrode connected to a data line DL, and a second electrode connected to the first node n1.
The first gate signal SCAN1 includes a pulse of the gate-on voltage VGL that is synchronized with the data voltage Vdata of the pixel data. The pulse of the first gate signal SCAN1 defines the sensing time Ts. During the initialization time Ti and the emission time Tem, the voltage of the first gate signal SCAN1 maintains the gate-off voltage VGH. A pulse width of the first gate signal SCAN1 may be set to one horizontal period (1H). The pulse of the first gate signal SCAN1 may be generated with the gate-on voltage VGL later than a rising edge of a second gate signal SCAN2 and inverted to the gate-off voltage VGH at the same time as the second gate signal SCAN2. The pulse width of the first gate signal SCAN1 is set to be smaller than a pulse width of the second gate signal SCAN2.
A second switch element T2 causes the driving element DT to operate as a diode during the initialization time Ti and the sensing time Ts by connecting the gate electrode of the driving element DT and the second electrode of the driving element DT in response to a gate-on voltage VGL of the second gate signal SCAN2. The second switch element T2 includes a gate electrode connected to a second gate line GL2 to which the second gate signal SCAN2 is applied, a first electrode connected to the second node n2, and a second electrode connected to the third node n3.
The second gate signal SCAN2 may be generated as a pulse of the gate-on voltage VGL. The pulse of the second gate signal SCAN2 defines the initialization time Ti and the sensing time Ts. During the emission time Tem, the voltage of the second gate signal SCAN2 maintains the gate-off voltage VGH.
A third switch element T3 supplies a reference voltage Vref to the first node n1 in response to a gate-on voltage VGL of a third gate signal EM. The reference voltage Vref is commonly supplied to the pixels through a third power line PL3. The third switch element T3 includes a gate electrode connected to a third gate line GL3 to which the third gate signal EM is applied, a first electrode connected to the first node n1, and a second electrode connected to the third power line PL3.
The third gate signal EM includes a pulse of the gate-off voltage VGH. The pulse of the third gate signal EM turns off the third and fourth switch elements T3 and T4 during the sensing time Ts so that a current path between the first node n1 and the third power line PL3 is blocked and a current path between the third node n3 and the fourth node n4 is blocked. In order to precisely express the low-gray luminance of pixels, the third gate signal EM may be generated as a pulse width modulation (PWM) pulse having a duty ratio during the emission time Tem. In this case, the voltage of the third gate signal EM swings between the gate-on voltage VGL and the gate-off voltage VGH according to the duty ratio of the PWM pulse during the emission time Tem.
The fourth switch element T4 forms a current path between the driving element DT and the light emitting element EL during the emission time Tem in response to the gate-on voltage VGL of the third gate signal EM. A gate electrode of the fourth switch element T4 is connected to the third gate line GL3. A first electrode of the fourth switch element T4 is connected to the third node n3, and a second electrode of the fourth switch element T4 is connected to the fourth node n4.
A fifth switch element T5 supplies the reference voltage Vref to the fourth node n4 during the initialization time Ti and the sensing time Ts in response to the gate-on voltage VGL of the second gate signal SCAN2. During the initialization time Ti and the sensing time Ts, the voltage of the anode electrode of the light emitting element EL is initialized to the reference voltage Vref. The light emitting element EL does not emit light because the voltage between the anode electrode and the cathode electrode is less than its threshold voltage during the initialization time Ti and the sensing time Ts. The fifth switch element T5 includes a gate electrode connected to the second gate line GL2, a first electrode connected to a third power line PL3, and a second electrode connected to the fourth node n4.
Hereinafter, a dimming method using an EM duty ratio signal according to one embodiment of the present specification will be described with reference to the drawings.
Referring to
The brightness controller 210 provides the digital brightness value DBV, which is information on the current operating brightness of the display panel. For instance, the digital brightness value DBV may include the numeric representation of the intensity of light in the display panel. In some cases, the digital brightness value DBV may include the numeric representation of the intensity of light at a particular point in a digital image in the display panel. The digital brightness value DBV can indicate how bright or dark a pixel is. For grayscale images, the brightness value of each pixel can be represented by an 8-bit number ranging from 0 to 255. Here, 0represents black (no brightness), and 255 represents white (maximum brightness).
The duty ratio calculator 220 receives the digital brightness value DBV from the brightness controller 210 and calculates a duty ratio and on time information used to generate a duty ratio signal using resolution information.
The duty ratio waveform generator 230 receives on time information about the duty ratio signal output from the duty ratio calculator 220 within one frame and generates the duty ratio signal (c.g., Duty Pulse as shown in
The EM waveform generator 240 generates the emission (EM) signal for driving the display panel.
The output unit 250 (also referred to as an output circuit 250) generates and outputs a final EM duty ratio signal by performing an OR operation (or logical sum operation) on the emission (EM) signal generated in the EM waveform generator 240 and output therefrom and the spread-processed duty ratio signal generated in the duty ratio waveform generator 230 and output therefrom.
For reference, in
Referring to
The duty ratio of the duty ratio signal may be calculated by linear interpolation using a preset duty ratio lookup table (LUT) of the duty ratio signal for the digital brightness value DBV, as shown in
In addition, the on time within one frame may be calculated as a duty ratio for a length of one frame period (VTotal) obtained by receiving driving resolution information about the current display panel. The one frame period is a combined time of an active section (VActive) where an amount of data of input video equivalent to one frame is input and a vertical blank section (VBlank) with no pixel data between an N-th (N is a natural number) frame period and an N+1-th frame period. Hereinafter, a method of calculating a duty ratio and on time information using exemplary values will be described in detail.
For example, when the resolution is 1920×1080 and VBlank=60, HActive=1920 and VActive=1080, and therefore, VTotal=VActive+VBlank=1080+60=1140.
First, the duty ratio may be calculated by linear interpolation using the lookup table as shown in
When DBV (16 bits)=100% (that is, 65535), the values calculated using the lookup table in
When DBV (16 bits)=50% (that is, 32768), the values calculated by linear interpolation using the lookup table in
When DBV (16 bits)=10% (that is, 6554), the values calculated by linear interpolation using the lookup table in
Referring again to
A start position and a width (unit: H) of the emission (EM) signal within one frame are determined according to resolution information. The EM waveform generator 240 may obtain a line count value by counting an input data enable (DE) signal line by line and may generate the emission (EM) signal to have a pulse width as wide as the determined width by being pulsed on at a point where the line count value is equal to a value of the start position of the emission (EM) signal.
Referring again to
Referring again to
The duty ratio signal may be generated to have N cycles (where N is a natural number), and in this case, one cycle may have a length obtained by dividing the length of VTotal within one frame by N. In other words, each cycle of the duty ratio signal generated to have N cycles may have a width of “VTotal/N.” In addition, when the duty ratio signal is generated to have N cycles, the duty ratio is applied to each cycle, and the width of the applied on-pulse may be “On Time/N.”
Referring again to
The first cycle and second cycle of the duty ratio signal generated in this way may be as follows. Since the first cycle has an on-level (low level in
The generated duty ratio signal (Duty Ratio Pulse in
For a duty ratio signal according to one embodiment of the present specification, a start position within one frame may be moved at regular time intervals. In addition, a movement degree of the start position of the duty ratio signal and a time interval for moving the start position thereof within one frame may be adjusted. Further, movement forms of the start position of the duty ratio signal within one frame may be of various forms including a linear form, a zigzag form, and a random form.
The start position of the duty ratio signal within one frame may be linearly, zigzaggedly, or randomly changed, and a degree (unit: H) and speed of change (unit: frames) of the start position may be controlled. The duty ratio signal may be generated in a manner in which the start position of the duty ratio signal is changed in units of H depending on the degree and speed of change (that is, the movement degree of the start position and the time interval for moving the start position) determined when the start position of the duty ratio signal is changed.
Referring again to
Referring to
For example, when the start positions of the duty ratio signal change sequentially from
In one embodiment, when the resolution is 1920×1080, VBlank=60, Cycle=2, the start position=2, and the start position of the duty ratio signal is moved by calculating based on the line count, the time interval for moving the start position may be set to one frame time, and the degree of change in the start position may be set to 12.5%. Since the start position is moved by 12.5% of VTotal every frame time, the start position of the duty ratio signal is moved by 1140×0.125≈143 lines, and when the start position is moved in a linear manner, the start position of the duty ratio signal may be moved in the order of 2-145-288-431-574-717-860-1003- . . . in the line count.
As described above, in one embodiment of the present specification, the movement forms of the start position of the duty ratio signal within one frame may be of various forms including a linear form, a zigzag form, and a random form.
Referring to
As seen so far, in the dimming method according to one embodiment of the present specification, the brightness of the screen is adjusted by applying the duty ratio signal of which a start position within one frame is moved over time to the emission signal and controlling the movement degree, the movement form, and the time interval of the start position of the duty ratio signal within one frame, thereby achieving advantages of reducing the visibility of horizontal band noise of the screen and preventing the horizontal band noise from being visible.
According to embodiments of the present specification, the brightness of a screen can be adjusted by applying a duty ratio signal of which a start position within one frame is moved over time to an emission signal, thereby minimizing deviation between lines in a light emitting region of a light emitting element and thus reducing the visibility of horizontal band noise of the screen.
According to embodiments of the present specification, the brightness of the screen can be adjusted by controlling a movement degree, a movement form, and a time interval of the start position of the duty ratio signal within one frame applied to the emission signal, thereby reducing the visibility of horizontal band noise of the screen.
Effects of the present specification are not limited to those mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the description below.
The embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, but the present disclosure is not necessarily limited to the embodiments, and may be implemented in various modifications without departing from the spirit of the present disclosure. Accordingly, the embodiments disclosed in the present disclosure are not intended to limit the scope of the present disclosure, but to explain the scope, and the scope of the spirit of the present disclosure is not limited by the embodiments. Therefore, it should be appreciated that the embodiments described above are intended to be illustrative in all respects and not restrictive. The scope of the present disclosure should be interpreted based on the accompanying claims, and all technical concepts within the scope equivalent to the claims should be construed as being included in the scope of the present disclosure.
The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.
These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0194249 | Dec 2023 | KR | national |
