Patent Application
20140375622
The present invention relates to display devices, more specifically to an active-matrix display device and a display method in which the order of scanning is changed.
In general liquid crystal display devices, polarity inversion drive is performed in order to suppress liquid crystal deterioration. A known polarity inversion drive scheme is a scheme (frame inversion drive scheme) in which the polarity of a voltage applied to the liquid crystal is inverted every frame. However, this drive scheme is subject to display defects, such as flicker, upon display, and therefore, in the drive schemes employed in recent years, the polarity of an applied voltage is inverted every horizontal scanning line and also every frame (a so-called “line inversion drive scheme”) or the polarity of an applied voltage is inverted every two vertically/horizontally adjacent pixels and also every frame (a so-called “dot inversion drive scheme”).
The dot inversion drive scheme is less prone to the occurrence of flicker, so that high-quality display can be achieved, but the polarity of a video signal to be applied to the liquid crystal panel is switched between predetermined voltages respectively above and below the potential of the common electrode, and therefore, the voltage swing of a video signal outputted by a liquid crystal panel driver is large, so that power consumption tends to be high. Moreover, in the line inversion drive also, more power consumption can be saved as the polarity inversion cycle of a video signal becomes longer (i.e., as the number of inversions per frame decreases).
Accordingly, only the odd scanning lines are sequentially selected in order to output signals from a source driver, and thereafter, polarity inversion is performed, so that only the even scanning lines are sequentially selected in order to output signals from the source driver, whereby line inversion drive or dot inversion drive can be realized by simply performing one polarity inverting operation per frame. Such a drive scheme is called an interlaced scanning scheme or an interlacing drive scheme.
However, even when such a drive scheme is employed, the potentials of video signals might change significantly depending on the image to be displayed, which results in a large voltage swing, so that power consumption tends to become high.
Therefore, Japanese Laid-Open Patent Publication No. 7-64512 discloses the configuration of a liquid crystal drive device in which binary digital video signals are used, and the order of selecting the scanning signal lines is determined such that the number of times the liquid crystal is charged/discharged is minimized. With this configuration, power consumed by charging/discharging the liquid crystal is minimized, resulting in reduced power consumption by the entire device.
However, even when the configuration described in Japanese Laid-Open Patent Publication No. 7-64512 is applied to a general liquid crystal display device using analog data (video signals at multiple grayscale levels), the power consumed by charge/discharge is not always minimized. Even if the number of charges/discharges is minimized, the potentials of video signals might change significantly depending on the image to be displayed, and in such a case, power consumption is increased.
Therefore, an objective of the present invention is to provide a display device and a display method in which analog data is used, and the total amount of potential variation of video signal lines can be reduced.
A first aspect of the present invention is directed to a display device for displaying an image by a plurality of pixel forming portions arranged along a plurality of video signal lines for transmitting a plurality of video signals and a plurality of scanning signal lines crossing the video signal lines, the device comprising:
a video signal line drive circuit for driving the video signal lines on the basis of an image signal representing the image;
a scanning signal line drive circuit for selectively driving the scanning signal lines; and
a scanning order determination circuit for determining order of selecting the scanning signal lines on the basis of the image signal so that the video signal lines are driven with lower power than power required for driving the video signal lines when the scanning signal lines are selected in order of arrangement.
In a second aspect of the present invention, based on the first aspect of the invention, the scanning order determination circuit determines at least a part of the order so as to minimize an integral of absolute values of amounts of potential variation caused for each of at least a part of the video signal lines upon each change of a scanning signal line selected by the scanning signal line drive circuit.
In a third aspect of the present invention, based on the second aspect of the invention, the scanning order determination circuit determines a scanning signal line to be selected next so as to minimize the integral of the absolute values of the amounts of potential variation, and the scanning order determination circuit also determines another scanning signal line to be selected following the selection of the preceding scanning signal line so as to minimize the integral of the absolute values of the amounts of potential variation.
In a fourth aspect of the present invention, based on the third aspect of the invention, the scanning order determination circuit determines a scanning signal line that is to be selected first from among the scanning signal lines to display the image, so as to minimize the integral of the absolute values of the amounts of potential variation, the first scanning signal line being selected next after the last scanning signal line selected so as to display an immediately preceding image.
In a fifth aspect of the present invention, based on the third aspect of the invention, the scanning order determination circuit determines a scanning signal line that is to be selected first from among the scanning signal lines, so as to minimize an integral of absolute values of potential differences of the video signal lines from a predetermined potential.
In a sixth aspect of the present invention, based on the third aspect of the invention, the scanning order determination circuit determines a scanning signal line that is to be selected to display the first row of the image, as the first to be selected from among the scanning signal lines.
In a seventh aspect of the present invention, based on the second aspect of the invention, the scanning order determination circuit calculates the integral on the basis of a predetermined number of upper bits of digital grayscale data included in the image signal and representing potentials to be applied to the video signal lines.
In an eighth aspect of the present invention, based on the first aspect of the invention, after determining the order, the scanning order determination circuit maintains the order until a predetermined wait period passes or until a predetermined start point.
In a ninth aspect of the present invention, based on the eighth aspect of the invention, the scanning order determination circuit sets the start point to be a point of detection of a change in the image or sets the wait period longer when the image is determined to be a still image than when the image is determined to be a video image.
In a tenth aspect of the present invention, based on the first aspect of the invention, the scanning order determination circuit divides the video signal lines into groups of a predetermined number of adjacent scanning signal lines, and determines the order for each group.
In an eleventh aspect of the present invention, based on the tenth aspect of the invention, further comprised is memory with a capacity for storing digital grayscale data specifying potentials to be provided to the video signal lines in one of the groups.
In a twelfth aspect of the present invention, based on the first aspect of the invention, the scanning order determination circuit adds up absolute values of amounts of potential variation for each video signal line selected every predetermined integer multiple of 2 or more from among the video signal lines.
In a thirteenth aspect of the present invention, based on the first aspect of the invention, the scanning signal line drive circuit is an address decoder, and the scanning order determination circuit provides the scanning signal line drive circuit with addresses in accordance with the order.
In a fourteenth aspect of the present invention, based on the first aspect of the invention, the scanning signal line drive circuit is disposed on each end side of the scanning signal lines such that the scanning signal lines are provided with signals at least from one end.
A fifteenth aspect of the present invention is directed to a method for displaying an image by a plurality of pixel forming portions arranged along a plurality of video signal lines for transmitting a plurality of video signals and a plurality of scanning signal lines crossing the video signal lines, the method comprising:
a video signal line drive step for driving the video signal lines on the basis of an image signal representing the image;
a scanning signal line drive step for selectively driving the scanning signal lines; and
a scanning order determination step for determining the order of selecting the scanning signal lines on the basis of the image signal so that the video signal lines are driven with lower power than power required for driving the video signal lines when the scanning signal lines are selected in order of arrangement.
In the first aspect of the present invention, the order of selecting the scanning signal lines is determined such that the video signal lines are driven with lower power than when the scanning signal lines are selected in order of arrangement so that power consumed by driving the video signal lines can be reduced.
In the second aspect of the present invention, at least a part of the order is determined so as to minimize the integral of absolute values of amounts of potential variation caused for each of at least apart of the video signal lines upon each scanning signal line change so that power consumed by driving the video signal lines can be reduced.
In the third aspect of the present invention, the next scanning signal line to be selected so as to minimize the integral of the absolute values of the amounts of potential variation is determined, and the subsequent scanning signal line to be selected following the selection of the preceding scanning signal line so as to minimize the integral of the absolute values of the amounts of potential variation is determined so that power consumed by driving the video signal lines can be reduced.
In the fourth aspect of the present invention, the first to be selected from among the scanning signal lines to display an image is the scanning signal line that is to be selected so as to minimize the integral of the absolute values of the amounts of potential variation, and the first scanning signal line is selected next after the last scanning signal line selected so as to display an immediately preceding image, so that in the configuration where the potentials applied to video signal lines the last time the video signal lines are selected remain unchanged, the integral of the amounts of potential variation of the video signal lines can be minimized even upon switching of images. Thus, power consumed by driving the video signal lines can be reduced significantly.
In the fifth aspect of the present invention, the first to be selected from among the scanning signal lines is the scanning signal line that is to be selected so as to minimize the integral of absolute values potential differences of the video signal lines from a predetermined potential, and therefore, for example, in the case where specific potentials are applied to the video signal lines at the startup, power-on, or standby of the device, or during a vertical blanking period, power consumed by driving the video signal lines can be reduced.
In the sixth aspect of the present invention, the first to be selected from among the scanning signal lines is the scanning signal line that is to be selected to display the first row of the image, and therefore, for example, in the case where the potentials of the video signal lines are not constant during a vertical blanking period, power consumed by driving the video signal lines can be reduced using a simplified configuration.
In the seventh aspect of the present invention, the integral is calculated on the basis of a predetermined number of upper bits of the digital grayscale data, so that computation can be simplified, the speed of the entire computation can be enhanced, and further, power consumed by computation can be reduced.
In the eighth aspect of the present invention, after the order is determined, the determined order is maintained until a predetermined waiting time passes or until a predetermined start point, resulting in less computation and reduced power consumption for computation.
In the ninth aspect of the present invention, the start point is a point of detection of a change in the image, or the wait period is set longer when the image is determined to be a still image than when the image is determined to be a video image, so that computation is reduced appropriately in accordance with, for example, a change in the image, resulting in reduced power consumption for computation.
In the tenth aspect of the present invention, the scanning signal lines are divided into groups of a predetermined number of adjacent scanning signal lines, and the order is determined for each group, so that a hold duration of at least half a frame can be ensured so that satisfactory display quality can be maintained.
In the eleventh aspect of the present invention, the provided memory has a capacity for storing digital grayscale data specifying potentials to be provided to the video signal lines in one group, so that the need for large-sized memory as typified by frame memory can be eliminated, resulting in reduced production cost.
In the twelfth aspect of the present invention, the integral of absolute values of the amounts of potential variation is calculated for each video signal line selected every predetermined integer multiple of 2 or more, so that the amount of computation to obtain the integral can be decreased, resulting in reduced power consumption for computation.
In the thirteenth aspect of the present invention, a general address decoder is used as the scanning signal line drive circuit, so that the device can be produced in a simplified configuration, and the order of selecting scanning signal lines can be changed freely in a simplified manner.
In the fourteenth aspect of the present invention, the scanning signal line drive circuit is positioned on each end side of the scanning signal lines, and therefore, the scale (size) of the circuit (on each side) can be reduced. Further, in the case where scanning signals are provided from both ends, the scanning signals are not distorted, so that the scanning lines can be selected both quickly and reliably.
The fifteenth aspect of the present invention allows a display method to achieve the same effects as those achieved by the first aspect of the present invention.
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
As shown in
The pixel forming portion P(m, n) has liquid crystal capacitance (also referred to as “pixel capacitance”) Clc formed by the pixel electrode Epix and the common electrode Ecom positioned on the opposite side of the liquid crystal layer therefrom. The pixel electrode Epix is positioned between the two video signal lines SL(m) and SL(m+1), and one of the two video signal lines is connected to the pixel electrode Epix via the TFT 10.
Note that the semiconductor layer of the TFT 10 is made of amorphous silicon, which can be produced readily at low cost, but other well-known materials, such as In—Ga—Zn—O (IGZO) based oxides and continuous grain silicon, can also be used. In particular, using an In—Ga—Zn—O (IGZO) based oxide semiconductor as the semiconductor layer results in quick response and extremely low current leakage, so that a low-power consumption drive mode such as low-frequency drive (intermittent drive) can be realized. Therefore, a further reduction in power consumption can be achieved in addition to the effects of the present embodiment.
The display control circuit 200 receives a display data signal DAT and a timing control signal Ts, which are transmitted externally, and outputs digital image signals DV as well as a source start pulse signal SSP, a source clock signal SCK, a latch strobe signal LS, and a gate address signal GA for controlling the timing of displaying an image on the display portion 500, as shown in
Here, the external display data signal DAT includes, for example, parallel data consisting of 18 bits in total, i.e., red, green, and blue display data, which are all 6-bit data, each being provided to a corresponding pixel forming portion. These data are provided to video signal lines for their respectively corresponding colors.
The video signal line drive circuit 300 receives the digital image signals DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS outputted by the display control circuit 200, and applies drive video signals S(1) to S(M) to the video signal lines SL(1) to SL(M) in order to charge the pixel capacitance Clc (and auxiliary capacitance) of the pixel forming portions P(m, n) in the display portion 500. At this time, the video signal line drive circuit 300 sequentially holds the digital image signals DV indicating voltages to be applied to the video signal lines SL(1) to SL(M), with the timing of pulse generation of the source clock signal SCK. Thereafter, the digital image signals DV being held are converted into analog voltages with the timing of pulse generation of the latch strobe signal LS. The analog voltages are applied simultaneously to all of the video signal lines SL(1) to SL(M) as drive video signals. That is, the scheme employed for driving the video signal lines SL(1) to SL(M) in the present embodiment is a line-sequential drive scheme.
Note that for the sake of simplified explanation, the present embodiment employs a line inversion drive scheme, which is a drive scheme in which the polarity of the voltage applied to the pixel liquid crystal is inverted every frame, but the line inversion drive scheme may be a drive scheme in which the polarity of the voltage applied to the pixel liquid crystal is inverted every row of the display portion 500 and also every frame, or even the dot inversion drive scheme as mentioned earlier may be employed.
The scanning signal line drive circuit 400 applies a corresponding one of the active scanning signals G(1) to G(N) to one of the scanning signal lines GL(1) to GL(N) on the basis of the gate address signal GA outputted by the display control circuit 200. More specifically, the scanning signal line drive circuit 400 is an address decoder, which selects one of the scanning signal lines GL(1) to GL(N) in accordance with an address included in a received gate address signal GA, and applies an active scanning signal to the selected scanning signal line. In the following, such an operation will also be expressed as “selecting a row (which is a display row corresponding to the selected scanning signal line)”.
Note that in
As will be described later, the display control circuit 200 sequentially determines addresses such that the scanning signal lines GL(1) to GL(N) are selected one by one until all of the lines are selected ultimately, so as to minimize the total amount (integral) of potential variation of the video signal lines SL(1) to SL(M), and thereafter, the display control circuit 200 outputs a gate address signal GA.
Note that in the present embodiment, to perform the frame inversion drive, an unillustrated common electrode drive circuit is provided so that a common voltage Vcom, which is a voltage to be provided to the common electrode of the liquid crystal, is inverted every frame. Moreover, in the case where the line inversion drive is performed, to suppress voltage swing of the video signal lines, the potential of the common electrode is preferably changed in accordance with the polarity inversion drive. More specifically, in accordance with a polarity inversion signal from the display control circuit 200, the common electrode drive circuit generates a voltage which switches between two reference voltage levels every row and every frame, and supplies it to the common electrode of the display portion 500 as the common voltage Vcom. These features make it possible to realize the line inversion drive scheme.
In this manner, drive video signals are applied to the video signal lines SL(1) to SL(M), and scanning signals are applied to the scanning signal lines GL(1) to GL(N) in an order to be described later, so that the display portion 500 displays an image. Next, the configuration and operation of the display control circuit 200 characterized by the manner in which the order of scanning the scanning signal lines is calculated will be described with reference to
The timing control portion 25 receives an externally transmitted timing control signal Ts, and outputs control signals CT for controlling the operations of the input frame memory 21, the output frame memory 22, the scanning order calculating portion 23, and the scanning order setting portion 24, as well as a source start pulse signal SSP, a source clock signal SCK, and a latch strobe signal LS for controlling the timing of displaying an image on the display portion 500. Further, the timing control portion 25 provides a timing control signal Ts to the address outputting portion 26 as well.
The input frame memory 22 stores an external display data signal DAT for one frame. Further, in accordance with a control signal CT from the timing control portion 25, the frame memory 22 outputs the stored display data signal DAT for one frame to the output frame memory 22 and the scanning order calculating portion 23 with appropriate timing. Thereafter, the input frame memory 22 stores another externally transmitted display data signal DAT for the next frame. As a result, the display data signal DAT stored in the output frame memory 22 is data that precedes the display data signal DAT stored in the input frame memory 21 by one frame. Note that the input frame memory 22 may be included in an unillustrated host controller which provides the display data signal DAT to the display control circuit 200.
On the basis of the external display data signal DAT, the scanning order calculating portion 23 calculates which row is to be selected next after a reference row is selected (i.e., after one horizontal scanning period) in order to minimize the total amount (integral) of potential variation of the video signal lines SL(1) to SL(M). Variations in potential of a video signal line means charge/discharge of the capacitance of the video signal line, including parasitic capacitance, and therefore, the larger the total amount of potential variation, the more power consumption.
For example, power consumption is maximized when a selection operation is repeated such that the minimum potential corresponding to the minimum grayscale value is initially applied to a video signal line, and thereafter (one horizontal scanning period later), the maximum potential corresponding to the maximum grayscale value is applied to the video signal line. However, in this case, the total amount of potential variation of the video signal lines can be reduced by selecting the odd rows sequentially and thereafter selecting the even rows sequentially. In this manner, by changing the order of selection appropriately, the total amount of potential variation of the video signal lines can be reduced. Therefore, the scanning order calculating portion 23 calculates the appropriate order in accordance with the procedure shown in
However, at the time of power-on or standby of the device or during the vertical blanking period, specific potentials might be applied to the video signal lines SL(1) to SL(M). In such a case, if the first row is to be always selected at the beginning, as in the first configuration, the total amount of variation in the potential of a video signal line due to the first row being selected might be increased from such a specific potential. Therefore, in such a case, instead of performing the processing in step S10, the row for which the total amount (integral) of potential variation of the video signal lines SL(1) to SL(M) relative to the specific potential is minimum is preferably selected as the first reference row. This configuration will be referred to as a second configuration.
Furthermore, during the vertical blanking period, instead of applying the specific potential as described above, the potential applied in the row selected at the end of a frame might be maintained on the video signal lines SL(1) to SL(M). In this case also, if the first row is to be always selected at the beginning, as in the first configuration, the total amount of potential variation of the video signal lines due to the first row being selected might be increased. Accordingly, in such a case, instead of performing the processing in step S10, the row for which the total amount (integral) of potential variation of the video signal lines SL(1) to SL(M) relative to the potential applied in the row selected at the end of the frame is minimum is preferably selected as the first reference row. This configuration will be referred to as a third configuration.
In this manner, the first configuration corresponding to the processing in step S10 of the present embodiment might increase the amount of potential variation of the video signal lines depending on the operation mode of the device, and therefore, by employing the second or third configuration depending on the operation mode, power consumption can be further reduced.
Next, for each row, the scanning order calculating portion 23 calculates the total amount (integral) of potential variation of the video signal line due to the next row after the reference row being selected (step S20). Normally, if the total amount of potential variation is not calculated for each row, it is not possible to determine what number row from the reference row is to be selected in order to minimize the total amount of potential variation of the video signal lines SL(1) to SL(M). Therefore, the total amount of potential variation as represented by the following expression (1) is calculated for each row.
However, in expression (1), “a” represents the reference row (whose initial value is 1), “i” represents the number (column number) for the video signal line, and “j” represents the number for the scanning signal line, i.e., the number for the row. Further, “Vji” represents the potential applied to the i'th video signal line (i'th column) when the j'th row (the j'th scanning signal line) is selected.
The scanning order calculating portion 23 sequentially calculates the total amount of variation represented by expression (1) for each row (more specifically, the calculation is performed by sequentially assigning the values in the range of from j=1 to j=N), and calculates the row for which the calculated total amount of potential variation of the video signal lines is the lowest among all of the rows, so that the obtained row is determined as the row that is to be selected next (referred to below as the “subsequent row”) (step S30).
Here, the amounts of potential variation of the video signal lines are computed on the basis of grayscale data corresponding to video signals to be applied to the video signal lines. More specifically, grayscale data corresponding to the columns (the video signal lines) in the reference row and the row for which the computations are to be performed are read from the input frame memory 21, and the total amount (integral) of potential variation is calculated in accordance with expression (1).
Note that if the speed of calculation allows, the total amount of potential variation is preferably obtained by adding up the amounts of potential variation actually having occurred for the video signal lines during each horizontal scanning period. For example, the scanning order calculating portion 23 has a (preset) table (referred to below as a “grayscale voltage table”) showing the correspondence between grayscale values (e.g., from 0 to 255) indicated by display data corresponding to drive video signals to be applied to a video signal line and voltage values for the drive video signal. In accordance with the grayscale voltage table, the scanning order calculating portion 23 calculates the amount of potential variation indicating a change of the potential of a video signal line corresponding to a provided drive video signal compared to the potential during the immediately preceding horizontal scanning period where the drive video signal corresponds to externally received display data.
Subsequently, the scanning order calculating portion 23 sets the subsequent row as a reference row (step S40), and determines whether or not all rows have already been set as the subsequent rows (step S50); if not all of the rows have yet been set (No in step S50), the process returns to step S20 and will be repeated until all of the rows are set (S50→S20→ . . . →S50), or if all of them have already been set (Yes in step S50), the process for one frame ends. Thereafter, a display data signal DAT for the next frame is provided to the input frame memory 21, and a similar operation to the above will be performed.
In this manner, all rows (for one frame) are selected by repeating the following: the row for which the total amount of potential variation relative to the initially set reference row is the lowest is selected as the subsequent row, and the row having been selected as the subsequent row is used as the next reference row in a similar operation to determine the next row to be set as the subsequent row. The scanning order calculating portion 23 generates scanning order data Dso specifying the order of selection, and provides the data to the scanning order setting portion 24.
The scanning order setting portion 24 provides the received scanning order data Dso to the address outputting portion 26 as well as an order control signal Co to the output frame memory 22 in order to control the output frame memory 22 such that digital image signals DV are outputted in order of data corresponding to the order specified by the scanning order data Dso.
The output frame memory 22 receives and stores a display data signal DAT for one frame from the input frame memory 21; the display data signal DAT includes grayscale data which is sequenced on the premise that the scanning signal lines are selected in order of sequence. The scanning order setting portion 24 controls the output frame memory 22 by changing (or rearranging) the order of sequence or by making no rearrangements, such that the data are outputted in order as mentioned above.
Furthermore, the address outputting portion 26 provides an address which specifies its corresponding scanning line to the scanning signal line drive circuit 400, which functions as an address decoder, as a gate address signal GA in accordance with the received scanning order data Dso. The scanning signal line drive circuit 400 selects one of the scanning signal lines GL(1) to GL(N) in accordance with the address included in the received gate address signal GA.
In this manner, the display control circuit 200 selects the scanning signal lines GL(1) to GL(N) in the aforementioned order, and supplies the video signal lines SL(1) to SL(M) with their corresponding drive video signals S(1) to S(M) to be provided when the rows are selected. As a result, the total amount of potential variation of the video signal lines can be minimized. This will be described using a simple and specific example with reference to
As can be appreciated with reference to
As described above, in the present embodiment, the order of selecting all rows (for one frame) is determined by repeating the following: the row for which the total amount of potential variation relative to the initially set reference row is the lowest is selected as the subsequent row, and the row having been selected as the subsequent row is used as the next reference row in a similar operation to determine the next row to be set as the subsequent row, and the scanning signal lines are selected in the determined order. With this configuration, power consumed by driving the video signal lines can be reduced by selecting the scanning signal lines in such an order that the total amount of potential variation of the video signal line becomes smaller than the case where the scanning signal lines are selected in order of arrangement.
Next, a first variant of the present embodiment will be described with reference to
In step S30 shown in
By using the upper bits in this manner, the exact amount of potential variation cannot be calculated because the amount to be represented by the lower bits is removed, but the amount of computation can be reduced, and therefore, this configuration is preferable when the computation speed is not sufficient. Further, even if the computation speed is satisfactory, the configuration is preferable in that power consumed by computation can be reduced.
Note that the upper bits are not limited to three bits so long as the amount of potential variation can be calculated, and the number of upper bits can be set within the range of less than the number of bits in the entire input data.
Furthermore, to reduce the amount of computation, the integral of the amounts of potential variation of all of the video signal lines SL(1) to SL(M) is not calculated, but some of the amounts may be omitted (without computing them). For example, the total amount of potential variation represented by the following expression (2), rather than by expression (1), may be calculated for each row.
Note that in expression (2), computation is performed for every second video signal line, so that the total amount of variation in the potential to be applied to the video signal lines whose orders are multiples of 3 is calculated, but the video signal lines for which computation is to be performed are not specifically limited. However, to perform computation uniformly across the entire screen, every video signal line whose order is an integer multiple of 2 or more is preferably targeted for computation, as in the case of expression (2).
Furthermore, by applying the configuration of the first variant to the configuration of the second variant, it is rendered possible to further reduce power consumption. Note that the method for determining the order may be applied partially.
An active-matrix liquid crystal display device according to the present embodiment has the same configuration as the display device of the first embodiment shown in
The display transition detecting portion 28 shown in
Upon reception of the update control signal Cr from the display transition detecting portion 28, the scanning order calculating portion 23 calculates the order of selecting all rows (for one frame), as in the first embodiment. Operations performed thereafter, for example, in order to select the scanning signal lines, are the same as in the first embodiment.
As described above, in the present embodiment, the scanning order calculating portion 23 calculates the order of selection only upon detection of a change between images by the display transition detecting portion 28. With this configuration, it is possible to reduce the number of times the scanning order calculating portion 23 performs computation, resulting in less power consumed by computation.
The change frequency setting portion 29 shown in
Furthermore, in a conceivable configuration shown in
Note that upon reception of the update control signal Cr from the change frequency setting portion 29, the scanning order calculating portion 23 shown in
As described above, in this variant of the present embodiment, the change frequency setting portion 29 detects whether an image is a still image or a video image, and in the case of a still image, the scanning order calculating portion 23 calculates the order of selection in longer cycles (or with a lower frequency) than in the case of a video image. With this configuration, it is possible to reduce the number of times the scanning order calculating portion 23 performs computation, resulting in less power consumption by computation. Moreover, in the configuration of this variant, unlike in the configuration of the second embodiment where the image is not updated unless it changes significantly, the details of computation are updated, even though such updates occur with a low frequency, so that the total amount of potential variation of the video signal lines can be further reduced even when changes between images are gradual, resulting in a further reduction in power consumption.
An active-matrix liquid crystal display device according to the present embodiment has the same configuration as the display device of the first embodiment shown in
The display control circuit 230 in the present embodiment renders it possible to avoid problems that can be caused in the case of the first embodiment. Such problems will be described below with reference to
Accordingly, the duration in which the pixels selected through the scanning signal line GL(4) in the F frame are displayed lasts only for a period Td until the scanning signal line GL(4) is selected in the following (F+1) frame, as shown in
As can be appreciated by comparing
As can be appreciated with reference to
In the present embodiment, the scanning signal lines are grouped into a plurality of blocks such that the scanning signal lines included in each block are selected appropriately so as to reduce power consumption within that block, but from the viewpoint of reducing power consumption, the selection not by the grouping in the first embodiment is more preferable.
However, since the blocks are sequentially selected in order from the closest to the first row, the period of time from selection of one of the scanning signal lines within a block until selection of one of the scanning signal lines within the same block in the next frame is approximately constant, so that there is an interval of approximately one frame between the selections (if the size of the block is sufficiently small). Accordingly, the duration in which to hold pixel tones in each row is approximately equal to one frame period, and therefore, there arises no severe problem with display quality. Note that in the case where the block size is large, even if the number of blocks is, for example, two, the hold duration is ensured to be a minimum of half a frame, and therefore, still, there arises no severe problem with display quality.
In this respect, in the case of the first embodiment, if the row selected first in the first frame is selected last in the next frame, the duration in which to hold the pixel tones in the same row is approximately equal to a time period for two frames, but if the row selected last in the first frame is selected first in the next frame, the duration in which to hold the pixel tones in the same row is approximately equal to a time period only for a vertical blanking period. In this manner, if there is a significant discrepancy between the durations in which to hold the pixel tones, the screen might be garbled, resulting in a severe problem with display quality. The configuration of the present embodiment renders it possible to avoid this problem.
Furthermore, in the present embodiment, the order of selection is calculated on a block-by-block basis, as in the first embodiment, but once calculation for one block is completed, calculation for the next block starts, so that it is not necessary to hold data for one frame to be outputted, and data for only one block (or two blocks including data in an output buffer) is held. Accordingly, line memory capable of holding such data can be used. Such line memory is small in circuit scale and also inexpensive, and therefore, by using the output line memory 32, it is rendered possible to reduce production cost of the device and also the circuit scale of the display control circuit 230.
As described above, in the present embodiment, the scanning signal lines are grouped into a plurality of blocks, the order of selection within each group is calculated so as to minimize the amount of potential variation of the video signal line, thereby reducing power consumption as in the first embodiment, and the order of selection among the groups is fixed, so that the hold duration can be ensured to be at least half a frame, whereby satisfactory display quality can be maintained.
Note that all or a part of the functions of the display control circuit in each of the embodiments may be included in a host controller or a discrete drive control circuit independent of that. Moreover, such functions can be realized by a microcomputer executing corresponding programs.
The above embodiments have been described taking the active-matrix liquid crystal display device as an example, but this is not limiting, and the present invention can also be applied to display devices using LEDs (light-emitting diodes), such as organic EL (electroluminescence) elements, as well as other flat-panel display devices, so long as they are active-matrix display devices.
The present invention is applied to display devices such as active-matrix liquid crystal display devices, and is particularly suitable for display devices for which low power consumption is required.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2012-27071 | Feb 2012 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP2012/067477 | 7/9/2012 | WO | 00 | 7/31/2014 |
