Patent Grant
9514697
The present invention relates to display devices, more specifically to an active-matrix display device and a display method in which scanning is performed in a different manner from sequential scanning.
Recent liquid crystal display devices have higher definition screens and therefore have increased numbers of video signal lines and scanning signal lines. Accordingly, more power is required for driving these signal lines. In addition, each scanning signal line is selected for a shorter period of time, and therefore, there is difficulty in setting a pause period in which no scanning signal lines are selected during one frame period. As a result, there is also difficulty in reducing power consumption by setting such a pause period.
Therefore, Japanese Laid-Open Patent Publication No. 2005-265869 discloses the configuration of a liquid crystal display device in which reset signals are provided only to scanning signal lines through which pixel forming portions corresponding to pixels whose display states change from their immediately preceding display states (during the immediately preceding frame period) are selected. In this configuration, no reset signal is provided to any pixel whose display state remains unchanged, resulting in reduced power consumption.
Patent Document 1: Japanese Laid-Open Patent Publication No. 2005-265869
Here, in Japanese Laid-Open Patent Publication No. 2005-265869, for any pixel whose display state does not change during two consecutive frame periods, specifically, there is no change in the voltage applied to the pixel forming portion for displaying that pixel. However, normal liquid crystal display devices are driven such that the polarity of the voltage applied to the pixel forming portion is inverted at least on a frame-by-frame basis, and therefore, power consumption can be reduced only in a limited case where the voltage applied to the pixel forming portion remains unchanged before and after polarity inversion. Accordingly, the above conventional configuration is not exactly capable of reducing overall power consumption sufficiently.
Therefore, an objective of the present invention is to provide a display device and method capable of reducing power consumption focusing on changes in voltages applied to pixel forming portions during one frame period in which to display an image.
A first aspect of the present invention is directed to a display device for displaying an image by means of a plurality of pixel forming portions arranged along a plurality of video signal lines for transmitting a plurality of video signals and a plurality of scanning signal lines crossing the video signal lines, the device comprising:
a video signal line drive circuit for driving the video signal lines on the basis of image signals representing the image;
a scanning order determining circuit for determining the order of selecting the scanning signal lines on the basis of the image signals, such that at least two scanning signal lines being equal at each of the video signal lines in terms of a potential applied to the video signal line are selected at the same time; and
a scanning signal line drive circuit for selectively driving the scanning signal lines in accordance with the order determined by the scanning order determining circuit.
In a second aspect of the present invention, based on the first aspect of the invention, when the number of scanning signal lines being equal at each of the video signal lines in terms of the potential applied to the video signal line exceeds a predetermined threshold, the scanning order determining circuit determines the order of selecting the scanning signal lines such that the same number of scanning signal lines as the threshold are selected at the same time.
In a third aspect of the present invention, based on the second aspect of the invention, when the number of scanning signal lines being equal at each of the video signal lines in terms of the potential applied to the video signal line exceeds a predetermined threshold, the scanning order determining circuit determines the order of selecting the scanning signal lines such that the same number of scanning signal lines as the threshold are selected at the same time, and up to the same number of unselected remaining scanning signal lines as the threshold are selected at the same time at an immediately succeeding place within the order.
In a fourth aspect of the present invention, based on the first aspect of the invention, the scanning order determining circuit determines the order of selecting the scanning signal lines such that the scanning signal lines being equal at each of the video signal lines in terms of the potential applied to the video signal line are selected at the same time, and the scanning order determining circuit sets a selection period for the scanning signal lines to be selected at the same time such that the selection period lasts longer as the number of scanning signal lines to be selected at the same time increases, and the selection period corresponding to the scanning signal lines to be selected at the same time is longer than a period in which one scanning signal line is selected.
In a fifth aspect of the present invention, based on the first aspect of the invention, the scanning order determining circuit determines at least a part of the order so as to minimize an integrated value obtained by adding up absolute values of respective amounts of change in potential for at least a part of the video signal lines due to switching among the scanning signal lines to be selected by the scanning signal line drive circuit.
In a sixth aspect of the present invention, based on the fifth aspect of the invention, the scanning order determining circuit determines the next scanning signal line to be selected to minimize the integrated value obtained by adding up the absolute values of the amounts of change in potential, and also determines a scanning signal line to be selected immediately thereafter to minimize the integrated value obtained by adding up the absolute values of the amounts of change in potential.
In a seventh aspect of the present invention, based on the fifth aspect of the invention, the scanning order determining circuit calculates the integrated value on the basis of a predetermined number of upper bits of digital grayscale data included in the image signals and specifying potentials to be applied to the video signal lines.
In an eighth aspect of the present invention, based on the fifth aspect of the invention, the scanning order determining circuit adds up absolute values of respective amounts of change in potential for every predetermined number of video signal lines from among all of the video signal lines, the predetermined number being an integer multiple of two or more.
In a ninth aspect of the present invention, based on the fifth aspect of the invention, once the order is determined, the scanning order determining circuit keeps the determined order until a change in the image is detected.
In a tenth aspect of the present invention, based on the first aspect of the invention, the scanning signal line drive circuit includes an address decoder, and the scanning order determining circuit provides the address decoder with addresses in accordance with the order.
In an eleventh aspect of the present invention, based on the tenth aspect of the invention, the scanning signal line drive circuit further includes a state register for receiving a signal outputted by the address decoder and, when a predetermined control signal is active, outputting a signal to select a corresponding scanning signal line, and the scanning order determining circuit provides the control signal to the state register.
In a twelfth aspect of the present invention, based on the tenth aspect of the invention, the scanning signal line drive circuit further includes: a first state register for receiving a signal outputted by the address decoder and, when a predetermined first control signal is active, outputting a signal in accordance with a state of the signal outputted by the address decoder; and a second state register for receiving the signal outputted by the first state register and, when a predetermined second control signal is active, outputting a signal in accordance with a state of the signal outputted by the first state register in order to select a corresponding scanning signal line, and the scanning order determining circuit provides the first control signal to the first state register and the second control signal to the second state register, the second control signal being at least active during a period in which the address decoder is provided with the addresses.
In a thirteenth aspect of the present invention, based on the first aspect of the invention, the scanning signal line drive circuit selects the scanning signal lines in the order determined by the scanning order determining circuit, and thereafter stops or pauses its operation for a period until the next image is displayed.
In a fourteenth aspect of the present invention, based on the thirteenth aspect of the invention, the video signal line drive circuit stops or pauses its operation during the period in which the scanning signal line drive circuit stops or pauses its operation.
A fifteenth aspect of the present invention is directed to a method for displaying an image on a plurality of pixel forming portions arranged along a plurality of video signal lines for transmitting a plurality of video signals and a plurality of scanning signal lines crossing the video signal lines, the method comprising:
a video signal line drive step of driving the video signal lines on the basis of image signals representing the image;
a scanning order determining step of determining the order of selecting the scanning signal lines on the basis of the image signals, such that at least two scanning signal lines being equal at each of the video signal lines in terms of a potential applied to the video signal line are selected at the same time; and
a scanning signal line drive step of selectively driving the scanning signal lines in accordance with the order determined in the scanning order determining step.
In the first aspect of the present invention, the order of selecting the scanning signal lines is determined such that at least two scanning signal lines being equal at each of the video signal lines in terms of a potential applied to the video signal line are selected at the same time, and therefore, the number of changes in potential for the video signal lines decreases compared to the case where the scanning signal lines are selected one by one in order of arrangement, resulting in a reduced total amount of change in potential. Thus, power consumption for driving the video signal lines can be reduced.
In the second aspect of the present invention, when the number of scanning signal lines being equal at each of the video signal lines in terms of the potential applied thereto exceeds a predetermined threshold, the order of selection is determined such that the same number of scanning signal lines as the threshold are selected at the same time, and therefore, the number of simultaneously selectable rows is limited. Thus, the drive capability of the video signal line drive circuit can be inhibited from being surpassed, thereby preventing display quality from being reduced.
In the third aspect of the present invention, the order of selection is determined such that at an immediately succeeding place within the order after the same number of scanning signal lines as the threshold have been selected at the same time, up to the same number of unselected remaining scanning signal lines as the threshold are selected at the same time, whereby the drive capability of the video signal line drive circuit can be inhibited from being surpassed, and further, the scanning signal lines selected at the immediately succeeding place within the order are equal at each of the video signal lines in terms of the potential applied to the video signal line, so that changes in potential for the video signal lines occur only to such a limited extent, resulting in reduced power consumption for driving the video signal lines.
In the fourth aspect of the present invention, a selection period for the scanning signal lines to be selected at the same time is set such that the selection period lasts longer as the number of scanning signal lines to be selected at the same time increases, and the selection period corresponding to the scanning signal lines to be selected at the same time is longer than a period in which one scanning signal line is selected, so that a sufficiently long charging time is ensured, whereby it is possible to inhibit the drive capability of the video signal line drive circuit from being surpassed, thereby preventing display quality from being reduced.
In the fifth aspect of the present invention, at least a part of the order is determined so as to minimize an integrated value obtained by adding up absolute values of respective amounts of change in potential for at least a part of the video signal lines due to switching among the scanning signal lines, resulting in reduced power consumption for driving the video signal lines.
In the sixth aspect of the present invention, the next scanning signal line to be selected is determined so as to minimize the integrated value obtained by adding up the absolute values of the amounts of change in potential, and a scanning signal line to be selected immediately thereafter is determined so as to minimize the integrated value obtained by adding up the absolute values of the amounts of change in potential, resulting in reduced power consumption for driving the video signal lines.
In the seventh aspect of the present invention, the integrated value is calculated on the basis of a predetermined number of upper bits of digital grayscale data, whereby it is rendered possible to allow simplified computation, enhance the speed of the entire computation, and reduce power consumption for the computation.
In the eighth aspect of the present invention, absolute values of respective amounts of change in potential are added up for every predetermined number of video signal lines from among all of the video signal lines, the predetermined number being an integer multiple of two or more, and therefore, it is possible to reduce the amount of such computation and also reduce power consumption for the computation.
In the ninth aspect of the present invention, once the order is determined, the determined order is kept until a change in the image is detected, and therefore, it is possible to reduce computation appropriately in accordance with such a change in the image, resulting in power consumption for the computation.
The tenth aspect of the present invention renders it possible to use atypical address decoder as the scanning signal line drive circuit, thereby allowing production of a device with a simplified configuration, and also allowing the order of selecting the scanning signal lines to be changed freely with a simple feature.
In the eleventh aspect of the present invention, for example, even if the address decoder outputs a signal without determining an address, the state register does not pass the signal to its output stage, and therefore, a scanning signal can be outputted at an appropriate time.
In the twelfth aspect of the present invention, the second state register receives the second control signal, which is at least active during a period in which the address decoder is provided with addresses, and therefore, the scanning signal can have a shorter inoperative period. Thus, faster drive can be performed, and in the case where the drive frequency is invariable, it is possible to set a longer active period, and therefore, it is possible to ensure a sufficiently long charging time even for (pixel capacitance in) a high-definition display device.
In the thirteenth aspect of the present invention, the scanning signal line drive circuit stops or pauses its operation for a period until the next image is displayed, resulting in a reduction in power consumption.
In the fourteenth aspect of the present invention, the video signal line drive circuit stops or pauses its operation during the aforementioned period, resulting in a further reduction in power consumption.
The fifteenth aspect of the present invention renders it possible to allow a display method to achieve the same effects as those achieved by the first aspect of the invention.
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
<1. First Embodiment>
<1.1 Overall Configuration and Operation of the Liquid Crystal Display Device>
As shown in
The pixel forming portion P(m,n) has liquid crystal capacitance (also referred to as “pixel capacitance”) Clc formed by the pixel electrode Epix and the common electrode Ecom opposite thereto with the liquid crystal layer positioned therebetween. There are two video signal lines SL(m) and SL(m+1) arranged with the pixel electrode Epix positioned therebetween, and one of the two video signal lines is connected to the pixel electrode Epix via the TFT 10.
Note that the TFT 10 includes a semiconductor layer of amorphous silicon, which can be produced readily at low cost, but other well-known materials, such as In—Ga—Zn—O-based oxides and continuous grain silicon, can also be used. Particularly in the case where an In—Ga—Zn—O-based oxide semiconductor is used as the semiconductor layer, such a semiconductor offers a high-speed response and provides extremely low current leakage, and therefore, it is possible to realize a low-power consumption drive mode such as low-frequency drive (intermittent drive). Thus, in addition to the effects of the present embodiment, it is possible to further achieve a reduction in power consumption.
As shown in
Here, the externally derived display data signal DAT includes parallel data, each consisting of, for example, 18 bits in total, including red, green, and blue display data, each of which is 6-bit data to be provided to one pixel forming portion. These data are provided to corresponding video signal lines for the respective colors.
The video signal line drive circuit 300 receives the digital image signals DV, the source start pulse signal SSP, the source clock signal SCK, and the latch strobe signal LS outputted by the display control circuit 200, and applies drive video signals S(1) to S(M) to the video signal lines SL(1) to SL(M) in order to charge the pixel capacitance Clc (and auxiliary capacitance) of each pixel forming portion P(m, n) in the display portion 500. At this time, the video signal line drive circuit 300 sequentially holds the digital image signals DV, which specify the voltages to be applied to the video signal lines SL(1) to SL(M), with the timing of pulsation of the source clock signal SCK. Moreover, an unillustrated A/D conversion circuit converts the digital image signals DV being held into analog voltages with the timing of pulsation of the latch strobe signal LS. These analog voltages are applied simultaneously to all of the video signal lines SL(1) to SL(M) as the drive video signals via an unillustrated output amplifier circuit (or buffer circuit). That is, the present embodiment employs a line-sequential drive method as the method for driving the video signal lines SL(1) to SL(M).
Note that for simplification of explanation, the present embodiment is assumed to employ a frame inversion drive method in which the polarity of a voltage applied to the pixel liquid crystal is inverted every frame, but a line inversion drive method in which the polarity is inverted every frame and also every row of the display portion 500 or a dot inversion drive method in which the polarity is inverted every row and also every column may be employed.
In accordance with the gate address signal GA outputted by the display control circuit 200, the scanning signal line drive circuit 400 applies an active scanning signal, i.e., one of GL(1) to GL(N), to a corresponding one of the scanning signal lines GL(1) to GL(N). More specifically, the scanning signal line drive circuit 400 is an address decoder and selects one or more of the scanning signal lines GL(1) to GL(N) in accordance with an address(es) included in a received gate address signal GA, and applies an active scanning signal(s) to the selected scanning signal line(s) while the transfer signal GT is in active state. In the following, such an operation will also be expressed as selecting a row (which is a display row corresponding to a scanning signal line to be selected).
In
As will be described later, in the case where more than one of all display rows have the same display content, the display control circuit 200 keeps changes in potential low for the video signal lines SL(1) to SL(M) by selecting two or more scanning signal lines corresponding to a part or all of such rows from among the scanning signal lines GL(1) to GL(N), determining addresses of the scanning signal lines sequentially, such that all of the scanning signal lines are selected ultimately, and outputting gate address signals GA.
Note that in the present embodiment, an unillustrated common electrode drive circuit is provided for performing frame inversion drive in which a common voltage Vcom, which is a voltage is to be provided to the common electrode of the liquid crystal panel, is inverted every frame. On the other hand, if the line inversion drive is to be performed here, the potential of the common electrode is preferably changed in accordance with the voltage inversion drive in order to keep the voltage swing of the video signal line low. More specifically, the common electrode drive circuit generates a voltage which switches between two reference voltage values every row and also every frame in accordance with a polarity inversion signal from the display control circuit 200, and supplies the voltage to the common electrode of the display portion 500 as the common voltage Vcom. With the above configurations, the line-inversion drive method can be realized.
In this manner, drive video signals are applied to the video signal lines SL(1) to SL(M), and scanning signals are applied to the scanning signal lines GL(1) to GL(N) in an order as will be described later, so that an image is displayed on the display portion 500. The configuration and the operation of the display control circuit 200 characterized by performing control such that a plurality of scanning signal lines are selected at the same time in a predetermined case will be described next with reference to
<1.2 Configuration and Operation of the Display Control Circuit>
The timing control portion 25 receives an externally transmitted timing control signal TS, and outputs a control signal CT for controlling the operation of each of the input frame memory 21, the output frame memory 22, the scanning order calculating portion 23, and the scanning order setting portion 24, as well as a source start pulse signal SSP, a source clock signal SCK, and a latch strobe signal LS for controlling the timing of displaying an image on the display portion 500. Moreover, the timing control portion 25 provides the timing control signal TS to the address output portion 26.
The input frame memory 21 stores an external display data signal DAT for one frame. Moreover, in accordance with the control signal CT from the timing control portion 25, the input frame memory 21 provides the stored display data signal DAT for one frame to the output frame memory 22 and the scanning order calculating portion 23 with appropriate timing. Thereafter, the input frame memory 21 stores a display data signal DAT subsequently transmitted from outside for the next frame. Accordingly, the display data signal DAT stored in the output frame memory 22 is data that precedes the display data signal DAT stored in the input frame memory 21 by one frame. Note that the input frame memory 21 may be provided in an unillustrated host controller for providing the display data signal DAT to the display control circuit 200.
On the basis of the externally derived display data signal DAT, the scanning order calculating portion 23 determines whether, of all display rows, there are a plurality of rows with the same display content, and if there are, the scanning order calculating portion 23 determines two or more scanning signal lines corresponding to the rows from among the scanning signal lines GL(1) to GL(N), such that the determined lines are selected at the same time, and also determines addresses of all of the scanning signal lines, such that they are all selected ultimately.
For example, power consumption is maximized when the following selection operation is repeated: a minimum potential corresponding to a minimum grayscale value is initially applied to a video signal line, and then (after one horizontal scanning period), a maximum potential corresponding to a maximum grayscale value is applied to that video signal line. However, in this case, if odd rows are selected at the same time, and thereafter, even rows are selected at the same time, such an operation renders it possible to reduce the total amount of change in potential for the video signal line. In this manner, in all cases, including the case where a plurality of video signal lines are selected at the same time, by appropriately changing the order of selecting video signal lines, it is rendered possible to reduce the total amount of change in potential for the video signal lines. Therefore, the scanning order calculating portion 23 calculates such an appropriate order by the procedure shown in
Next, the scanning order calculating portion 23 determines for each row whether or not the row has the same display content as the reference row, and extracts such a row having the same display content (step S12). Note that to avoid any overlap, any row having been extracted once is excluded from the target for determination.
Here, the rows with the same display content encompass not only rows which have the same display content in that they have the same grayscale value and color across all columns but also rows which have the same display content in that they have the same grayscale values in the same (corresponding) columns. Examples of such rows include rows that are displayed with the same changes in grayscale value (i.e., the same gradations) in the direction of changes of the columns, as well as rows that are displayed in the same stripe. The scanning order calculating portion 23 compares pixel grayscale values (grayscale data) between a reference row and a row to be determined, and extracts the row as having the same data if it is identical to the reference row in all respects.
Subsequently, the scanning order calculating portion 23 assigns the same place in the order to all extracted rows with the same data, and stores the place in the order for each row (step S14). Note that the place in the order to be assigned is the same as the place of the reference row in the order, i.e., the lowest row number.
Next, the scanning order calculating portion 23 sets the subsequent row whose place in the order has not yet been determined, as a reference row (step S16), and determines whether all rows have already been set as such subsequent rows (step S18), and if the determination is negative (No in step S18), the procedure returns to step S12, which is repeated until all rows are set (S18→S12→ . . . →S18), or if the determination is that all rows have already been set (Yes in step S18), the process for one frame is complete. Thereafter, a display data signal DAT for the next frame is provided to the input frame memory 21, and a similar operation will be performed.
In this manner, any row with the same data as the initially set reference row is extracted, and the subsequent row whose place in the order has not yet been determined is used as the next reference row to perform a similar process of determining the next row to be set as a subsequent row; such a process will be repeated until all rows (for one frame) are selected. The scanning order calculating portion 23 generates scanning order data Dso specifying the order of selection (in which a plurality of rows might be selected at the same time), and provides the data to the scanning order setting portion 24.
Upon reception of the scanning order data Dso, the scanning order setting portion 24 provides the data to the address output portion 26, and also provides an order control signal Co to the output frame memory 22, thereby controlling the output frame memory 22 such that digital image signals DV are outputted in order of data corresponding to the order specified by the scanning order data Dso.
The output frame memory 22 receives and stores a display data signal DAT for one frame from the input frame memory 21, and the display data signal DAT has grayscale data arranged in a sequence on the premise that the scanning signal lines are selected in order of arrangement. The scanning order setting portion 24 controls the output frame memory 22 such that the data are outputted in the order as described above by changing (rearranging) the sequence (or without performing rearrangement if not necessary).
Furthermore, in accordance with the received scanning order data Dso, the address output portion 26 provides a gate address signal GA, which includes an address(es) specifying a corresponding scanning line(s), to the scanning signal line drive circuit 400, which includes an address decoder. In addition, a transfer signal GT, which is a timing signal to perform control such that a scanning signal is outputted when the timing signal is active, is provided to the scanning signal line drive circuit 400.
In accordance with the address(es) included in the received gate address signal GA, the scanning signal line drive circuit 400 selects one or more of the scanning signal lines GL(1) to GL(N) while the transfer signal GT is active. The configuration and the operation of the scanning signal line drive circuit 400 will be described in detail with reference to
The address decoder 410 receives a gate address signal GA and outputs an active signal to select from among the scanning signal lines GL(1) to GL(N) one or more lines corresponding to an address(es) specified by address data AD included in the received signal.
The state register 420 receives a transfer signal GT and conveys to its output stage the state of the signal received from the address decoder 410 to select one or more of the scanning signal lines GL(1) to GL(N), while the transfer signal is active. More specifically, an active output signal is provided as a scanning signal to a corresponding (selected) one or more of the scanning signal lines GL(1) to GL(N). With this configuration, even if the address decoder 410 outputs a signal without determining an address, the state register 420 does not pass the signal to the output stage, and therefore, a scanning signal can be outputted at an appropriate time. These signals will be further described with reference to
Thereafter, during the period from time t2 to time t3, the transfer signal GT is kept active, so that the state register 420 passes the state signal being held to the output stage. Here, assuming that the address specified by the address data AD(n) represents the n'th scanning signal line to be selected, a scanning signal provided to the scanning signal line GL(n) corresponding to that address is kept active during the period from time t2 to time t3. During this period, a digital image signal DV, including DATA(n) which is corresponding grayscale data having been rearranged as described earlier, is outputted, and therefore, the corresponding grayscale data is provided to pixel forming portions corresponding to the row to be selected. Note that the row to which the n'th scanning signal line to be selected corresponds in the actual order of arrangement is determined by the number of rows with the same display content.
In this manner, the display control circuit 200 selects the scanning signal lines GL(1) to GL(N) in the order as described above, such that the rows with the same display content are selected at the same time, and further, the display control circuit 200 provides drive video signals S(1) to S(M) which are to be provided when the rows are selected, to their corresponding video signal lines SL(1) to SL(M). By doing so, it is rendered possible to reduce changes in potential for the video signal lines. This will be described using a simple and concrete example with reference to
As can be appreciated with reference to
<1.3 Effects>
As described above, in the present embodiment, the scanning signal lines are selected such that rows with the same display content are selected at the same time, and therefore, the number of changes in potential for the video signal lines becomes lower than in the case where the scanning signal lines are selected one by one in order of arrangement, resulting in a reduced total amount of change in potential. Thus, it is possible to reduce power consumption for driving the video signal lines.
<1.4 Variants of the First Embodiment>
<1.4.1 First Variant>
Next, a first variant of the present embodiment will be described. In the first variant, the configuration of the scanning signal line drive circuit differs in detail from that in the first embodiment in that the scanning signal has a shorter inoperative period. This will be described below with reference to
More specifically, the address decoder 410 operates in the same manner as in the first embodiment, and the first state register 421 has the same configuration as the state register 420 in the first embodiment, although the first state register 421 receives the first transfer signal GT1, which is different from the transfer signal for the state register 420. Moreover, the second state register 422 operates differently from the state register 420 in the first embodiment, but they have the same configuration.
Accordingly, while the first transfer signal GT1 is active, the first state register 421 conveys to its output stage the state of a signal received from the address decoder 410 to select one or more of the scanning signal lines GL(1) to GL(N). Moreover, while the second transfer signal GT2 is active, the second state register 422 similarly conveys to its output stage the state of the signal received from the first state register 421 to select one or more of the scanning signal lines GL(1) to GL(N). These signals will be further described with reference to
More specifically, as shown in
In this manner, as in the first embodiment, the display control circuit 200 selects the scanning signal lines GL(1) to GL(N) in the order as described above, such that rows with the same display content are selected at the same time, and further, the display control circuit 200 provides the drive video signals S(1) to S(M) which are to be provided when the rows are selected, to their corresponding video signal lines SL(1) to SL(M), whereby the amount of change in potential for the video signal lines can be reduced similarly.
Furthermore, the scanning signal line drive circuit 450 is capable of outputting a scanning signal even during the period in which the address data AD is included, by means of the configuration and operation as shown in
<1.4.2 Second Variant>
Next, a second variant of the present embodiment will be described. In the second variant, rather than all rows with the same display content being selected at the same time, the number of simultaneously selectable rows is limited to two. More specifically, after all rows with the same data are extracted in step S12 shown in
Similar to
As can be appreciated with reference to
Note that if the scanning signal line GL(6) takes another place in the order of selection, rather than the next place to the scanning signal lines GL(1) and GL(3) within the order of selection, the number of changes in potential is four, so that the total amount of change in potential increases slightly, but as a whole, the total amount of change in potential is lower than in the case where the scanning signal lines are selected one by one in order of arrangement, and therefore, the above configuration is still advantageous.
With the above configuration, it is possible to reduce power consumption for driving the video signal lines, as in the first embodiment, and by limiting the number of simultaneously selectable rows, it is rendered possible for the drive capability of the video signal line drive circuit 300 not to be surpassed, whereby it is possible to prevent display quality from being reduced.
Here, in the above example, the number of simultaneously selectable rows is set at two, but this number is preferably determined in accordance with the drive capability of the video signal line drive circuit 300, and specifically, it is calculated in the following manner. When the capacitance of a single video signal line SL(m) to be driven by the video signal line drive circuit 300 is Csbl, the pixel capacitance of a pixel forming portion is Cpix, and other capacitance, including parasitic capacitance, is Cp, the load capacitance Cload_s as seen from the video signal line drive circuit 300 at the time of driving the video signal line SL(m) can be represented by expression (1) below.
Cload_s=Csbl+Cpix+Cp (1)
Furthermore, the load capacitance Cload_m as seen from the video signal line drive circuit 300 at the time of driving n scanning signal lines GL(n) can be represented by expression (2) below based on expression (1).
Cload_m=Csbl+n·Cpix+Cp (2)
Here, the value n is obtained as the highest integer at which the load capacitance ratio (Cload_m/Cload_s) is less than or equal to a predetermined design value Rcm (e.g., 1.2). The value n is set as the number of simultaneously selectable rows. By doing so, it is rendered possible for the drive capability of the video signal line drive circuit 300 not to be surpassed. Note that the above calculation example is merely illustrative, and various design techniques can be used as calculation bases.
<1.4.3 Third Variant>
Next, a third variant of the present embodiment will be described. In the third variant, all rows with the same display content are selected at the same time, as in the first embodiment, but the selection period is lengthened in accordance with the number of rows to be selected at the same time. By doing so, it is rendered possible to ensure a sufficiently long charging time during a normal selection period even if the drive capability of the video signal line drive circuit 300 is surpassed because of a large number of rows being selected at the same time, and therefore, it is possible to prevent display quality from being reduced. This will be described below with reference to
Furthermore, the selection period from time t4 to time t5 in which two scanning signal lines are selected at the same time is longer than the selection period from time t2 to time t3, which is a normal period in which one scanning signal line is selected, and the selection period from time t1 to time t2 in which three scanning signal lines are selected at the same time is further longer than the selection period from time t4 to time t5 in which two scanning signal lines are selected at the same time. Accordingly, as the number of scanning signal lines to be selected at the same time increases, the duration of a corresponding selection period is set longer, so that a sufficiently long charging time can be ensured.
Note that as can be appreciated with reference to
With the above configuration, it is possible to reduce power consumption for driving the video signal lines, as in the first embodiment, and as the number of rows to be selected at the same time increases, the duration of a corresponding selection period is set longer, whereby it is possible for the drive capability of the video signal line drive circuit 300 not to be surpassed, thereby preventing display quality from being reduced.
Here, in the example shown in
Furthermore, such a period is preferably set in accordance with the drive capability of the video signal line drive circuit 300, as in the second variant, and more specifically, it can be calculated on the basis of expressions (1) and (2) by multiplying the duration Is of a normal selection period by the aforementioned additional capacitance ratio (Cload_m/Cload_s) (along with an appropriate coefficient). This calculation renders it possible for the drive capability of the video signal line drive circuit 300 not to be surpassed. Note that the above calculation example is merely illustrative, and various design techniques can be used as calculation bases.
Furthermore, in the third variant, the number of simultaneously selectable rows is not specifically limited, but the number of selectable rows may be limited as in the second variant. In such a case, the number of simultaneously selectable rows may be set considering the duration of the selection period that is set to be longer than a normal selection period.
<1.4.4 Fourth Variant>
Next, a fourth variant of the present embodiment will be described. In the fourth variant, the mode of selecting the scanning signal lines is the same as in the first embodiment, except that a part or all of the address decoder and the state register included in the scanning signal line drive circuit 400 are set in a pause or halt state during a time period after all scanning signal lines have been selected until selection of the next scanning signal line starts in the next frame period (such a period will be referred to below as a “pause period”; for example, the period from time t5 to time t7 shown in
More specifically, the output amplifier circuits coupled to the video signal lines are connected commonly to an enable line, and when the potential of the enable line is set at an inactive level, all of the output amplifier circuits are brought into a non-operating state. In addition, the enable line is connected to the display control circuit 200, and the display control circuit 200 performs control such that the potential of the enable line is at an inactive level during the pause period. By doing so, the operation of the output amplifier circuits is paused during the pause period, resulting in reduced power consumption.
Note that the circuits that are to be set in the state of pausing outputs are the output amplifier circuits, but this is merely an illustrative example, and all or a part of the circuits included in the video signal line drive circuit 300, such as the A/D conversion circuit and latch circuits, may be set in a pause or halt state. Alternatively, at least a part of the circuits in the display device, including all other circuits in addition to the above, may be set in a pause or halt state. Moreover, to set the circuits in a pause or halt state, various well-known configurations, such as a configuration in which the potential of a power line is changed, can also be employed in addition to the configuration in which state transitions are caused by means of a control line.
<2. Second Embodiment>
<2.1 Overall Configuration and Operation>
The configuration and operation of the display device in the present embodiment are approximately the same as those of the display device shown in
The display control circuit 200 in the present embodiment outputs gate address signals GA after determining the order of selecting the scanning signal lines such that scanning signal lines corresponding to rows with the same display content are selected at the same time, and then determining addresses sequentially such that the scanning signal lines GL(1) to GL(N) are selected one by one or a plurality sets of rows with the same display content are selected sequentially, so that all of the scanning signal lines are selected ultimately, in such a manner that the total amount (integrated value) of change in potential for the video signal lines SL(1) to SL(M) is minimized. Accordingly, the scanning order calculating portion 23 included in the display control circuit 200 in the present embodiment operates differently from that in the first embodiment. Details will be given below.
The scanning order calculating portion 23 extracts rows with the same display content and determines an order of selection in which the extracted rows are selected at the same time, as in the first embodiment, and thereafter, the scanning order calculating portion 23 further determines an order as described below. Specifically, on the basis of an externally derived display data signal DAT, the scanning order calculating portion 23 calculates which row is to be selected next after a reference row is selected (i.e., after one horizontal scanning period) in order to minimize the total amount (integrated value) of change in potential for the video signal lines SL(1) to SL(M). Changes in potential of a video signal line means charge/discharge of the capacitance of the video signal line, including parasitic capacitance, and therefore, power consumption increases as the total amount of change in potential increases.
For example, power consumption is maximized when the following selection operation is repeated: a minimum potential corresponding to a minimum grayscale value is initially applied to a video signal line, and then (after one horizontal scanning period), a maximum potential corresponding to a maximum grayscale value is applied to the video signal line. However, in this case, the total amount of change in potential for the video signal lines can be reduced by selecting odd rows sequentially and thereafter selecting even rows sequentially. In this manner, the total amount of change in potential for the video signal lines can be reduced by changing the order of selection appropriately. Therefore, the scanning order calculating portion 23 calculates such an appropriate order by the procedure shown in
However, in some cases, a specific potential might be applied to the video signal lines SL(1) to SL(M) at the time of power-on or standby of the device or during a vertical blanking period. In such a case, if the first row is to be always selected at the beginning, as in the first configuration, the total amount of change in potential for the video signal lines with respect to the specific potential due to the first row being selected might be significant. Therefore, in such a case, instead of performing the processing in step S20, a row with the lowest total amount (integrated value) of change in potential for the video signal lines SL(1) to SL(M) relative to the specific potential is preferably selected as the initial reference row. This configuration will be referred to as a second configuration.
Furthermore, in some cases, during the vertical blanking period, rather than the specific potential being applied as described above, a potential applied to the row selected at the end of a frame might be maintained on the video signal lines SL(1) to SL(M). In this case also, if the first row is to be always selected at the beginning, as in the first configuration, the total amount of change in potential for the video signal lines due to the first row being selected might become significant. Therefore, in such a case, a preferable configuration is such that instead of performing the processing in step S20, a row with the lowest total amount (integrated value) of change in potential for the video signal lines SL(1) to SL(M) relative to the potential applied to the row selected at the end of the frame is selected as the initial reference row. This configuration will be referred to as a third configuration.
In this manner, the first configuration which corresponds to the processing in step S20 in the present embodiment might increase the amount of change in potential for the video signal lines depending on the operation mode of the device, and therefore, the second or third configuration is employed in accordance with the operation mode in order to further reduce power consumption.
Next, for each row, the scanning order calculating portion 23 calculates the total amount (integrated value) of change that occurs in potential for the video signal lines upon selection of the next row after the reference row (step S22). Note that thereafter, one or more than one subsequent rows to which the same place in the order is assigned, i.e., they have the same display content, might be selected at a time, but for simplification of explanation, an example where there are (by chance) no rows with the same display content will be described.
Here, if the total amount of change in potential is not calculated for each row, normally, it is not possible to determine what number row from the reference row is to be selected in order to minimize the total amount of change in potential for the video signal lines SL(1) to SL(M). Therefore, the total amount of change in potential as represented by expression (3) below is calculated for each row.
In expression (3), “a” represents the reference row (whose initial value is 1), “i” represents the number (column number) for the video signal line, and “j” represents the number for the scanning signal line, i.e., the number for the row. In addition, “Vji” represents the potential applied to the i'th video signal line (i'th column) when the j'th row (the j'th scanning signal line) is selected.
The scanning order calculating portion 23 calculates the total amount of change represented by expression (3) sequentially for each row (more specifically, the calculation is performed by sequentially assigning the values in the range of from j=1 to j=N), and obtains the row with the lowest of all of the total amounts of change in potential for the video signal lines calculated for all rows, so that the obtained row is set as the row that is to be selected next (hereinafter, referred to as the “subsequent row”) (step S24).
Here, the amounts of change in potential for the video signal lines is computed on the basis of grayscale data corresponding to video signals to be applied to the video signal lines. More specifically, for both the reference row and the row for which computations are to be performed, grayscale data corresponding to the columns (the video signal lines) are read from the input frame memory 21, and the total amounts (integrated values) of change in potential are calculated in accordance with expression (3).
Note that if the speed of calculation allows, the total amount of change in potential is preferably obtained by adding up the amounts of change in potential actually having occurred for the video signal lines during each horizontal scanning period. For example, the scanning order calculating portion 23 has a (preset) table (referred to below as a “grayscale voltage table”) showing the correspondence between grayscale values (e.g., from 0 to 255) indicated by display data corresponding to drive video signals to be applied to video signal lines and voltage values for the drive video signals. On the basis of the grayscale voltage table, the scanning order calculating portion 23 calculates the amount of change in potential that indicates a change in potential from the immediately preceding horizontal scanning period for a video signal line provided with a corresponding drive video signal for externally received display data.
Subsequently, the scanning order calculating portion 23 sets the aforementioned subsequent row as a reference row (step S26), and determines whether or not all rows have already been set as the subsequent rows (step S28); if not all of the rows have yet been set (No in step S28), the process returns to step S22 and will be repeated until all of the rows are set (S28→S22→ . . . →S28), or if all of the rows have already been set (Yes in step S28), the process for one frame ends. Thereafter, a display data signal DAT for the next frame is provided to the input frame memory 21, and a similar operation to the above will be performed.
In this manner, all rows (for one frame) are selected by repeating the following: the row with the lowest total amount of change in potential relative to the initially set reference row is selected as a subsequent row, and the row having been selected as the subsequent row is used as the next reference row in a similar operation to determine the next row to be set as a subsequent row. The scanning order calculating portion 23 generates scanning order data Dso specifying the order of selection, and provides the data to the scanning order setting portion 24.
The scanning order setting portion 24 provides the received scanning order data Dso to the address outputting portion 26 as well as an order control signal Co to the output frame memory 22 in order to control the output frame memory 22 such that digital image signals DV are outputted in the order of data corresponding to the order specified by the scanning order data Dso. Note that as described earlier, there are a plurality of rows to which the same place within the scanning order is assigned.
The output frame memory 22 receives and stores a display data signal DAT for one frame from the input frame memory 21, and the display data signal DAT has grayscale data arranged in a sequence on the premise that the scanning signal lines are selected in order of arrangement. The scanning order setting portion 24 controls the output frame memory 22 such that the data are outputted in the order as described above by changing (rearranging) the sequence or without performing rearrangement.
Furthermore, in accordance with the received scanning order data Dso, the address output portion 26 provides a gate address signal GA, which includes an address(es) specifying a corresponding scanning line(s), to the scanning signal line drive circuit 400, which functions as an address decoder. The scanning signal line drive circuit 400 selects one of the scanning signal lines GL(1) to GL(N) in accordance with the address included in the received gate address signal GA.
In this manner, the display control circuit 200 selects the scanning signal lines GL(1) to GL(N) in the aforementioned order, and supplies the video signal lines SL(1) to SL(M) with their corresponding drive video signals S(1) to S(M) to be provided when the rows are selected. By doing so, the total amount of change in potential for the video signal lines can be minimized. This will be described using a simple and specific example with reference to
Similar to
Furthermore, in the above configuration, for convenience of explanation, after a plurality of rows with the same display content are extracted and numbered in sequence, the order of the rows is determined such that the total amount of change in potential is minimized, as described above, but the order can be determined by a series of processing tasks.
<2.2 Effects>
As described above, in the present embodiment, the order of selecting all rows (for one frame) is determined by repeating the following: the row with the lowest total amount of change in potential relative to a reference row is selected as a subsequent row, and the row having been selected as the subsequent row is used as the next reference row in a similar operation to determine the next row to be set as a subsequent row, and the scanning signal lines are selected in the determined order. With this configuration, power consumption for driving the video signal lines can be reduced by selecting the scanning signal lines in such an order that the total amount of change in potential for the video signal lines becomes smaller than in the case where the scanning signal lines are selected in order of arrangement.
<2.3 Variants of the Second Embodiment>
<2.3.1 First Variant>
Next, a first variant of the present embodiment will be described with reference to
In step S22 shown in
By using the upper bits in this manner, the exact amount of change in potential cannot be calculated because the amount to be represented by the lower bits is removed, but the amount of computation can be reduced, and therefore, this configuration is preferable when the computation speed is not sufficient. Further, even if the computation speed is satisfactory, the configuration is still preferable in that power consumption for computation can be reduced.
Note that the upper bits are not limited to three bits so long as the amount of change in potential can be calculated, and the number of upper bits can be set within the range of less than the number of bits in the entire input data.
<2.3.2 Second Variant>
Furthermore, to reduce the amount of computation, an integrated value of the amounts of change in potential for some of the video signal lines SL(1) to SL(M), rather than for all of them, may be calculated by skipping their changes in potential (without computing them). For example, the total amount of change in potential represented by expression (4) below, rather than by expression (3), may be calculated for each row.
Note that in expression (4), computation is performed for every third video signal line, so that the total amount of change in the potential to be applied to every video signal line corresponding to a multiple of 3 is calculated, but the video signal lines for which computation is to be performed are not specifically limited. However, to perform computation uniformly across the entire screen, it is preferable to perform computation for every video signal line corresponding to an integer multiple of 2 or more, as shown in expression (4).
Furthermore, by applying the configuration of the first variant to the configuration of the second variant, it is rendered possible to further reduce power consumption. Note that the approach to determine the order may be applied partially.
<3. Third Embodiment>
<3.1 Overall Configuration and Operation of the Liquid Crystal Display Device>
An active-matrix liquid crystal display device according to the present embodiment operates in the same manner as the display device of the first embodiment shown in
<3.2 Operation of the Display Transition Detecting Portion>
The display transition detecting portion 28 shown in
Upon reception of the update control signal Cr from the display transition detecting portion 28, the scanning order calculating portion 23 calculates the order of selecting all rows (for one frame), as in the first or second embodiment. Operations performed thereafter, for example, in order to select the scanning signal lines, are the same as in the first or second embodiment.
<3.3 Effects>
As described above, in the present embodiment, the scanning order calculating portion 23 calculates the order of selection only upon detection of a change in the image by the display transition detecting portion 28. With this configuration, it is possible to reduce the number of times the scanning order calculating portion 23 performs computation, resulting in reduced power consumption for computation.
<4. Variants of the Embodiments>
All or apart of the functions of the display control circuits in the above embodiments may be included in host controllers or different individual drive control circuits. Alternatively, the functions may be realized by a microcomputer executing corresponding programs.
Furthermore, the above embodiments have been described by taking the active-matrix liquid crystal display device as an example, but the example is not limiting, so long as the display device is of an active-matrix type, and the present invention can be applied similarly to display devices using LEDs (Light Emitting Diodes), such as organic EL (Electro Luminescence) elements, and other flat-panel display devices.
The present invention is applied to active-matrix display devices, and is particularly suitable for active-matrix display devices, such as liquid crystal display devices, in which scanning is performed in a different manner from sequential scanning.
10 TFT (switching element)
21 input frame memory
22 output frame memory
23 scanning order calculating portion
24 scanning order setting portion
25 timing control portion
26 address output portion
28 display transition detecting portion
200, 250 display control circuit
300 video signal line drive circuit
400, 450 scanning signal line drive circuit
410 address decoder
420 state register
500 display portion
DAT display data signal (image signal)
DV digital image signal
Epix pixel electrode
GL(n) scanning signal line (n=1 to N)
SL(m) data line (m=1 to M)
P(m,n) pixel forming portion (n=1 to N, and m=1 to M)
| Number | Date | Country | Kind |
|---|---|---|---|
| 2012-153791 | Jul 2012 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2013/064191 | 5/22/2013 | WO | 00 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2014/010313 | 1/16/2014 | WO | A |
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|---|---|---|---|
| 20020093473 | Tanaka et al. | Jul 2002 | A1 |
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| 20060238552 | Chuang | Oct 2006 | A1 |
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| Number | Date | Country |
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| 2002-278523 | Sep 2002 | JP |
| 2005-265869 | Sep 2005 | JP |
| 2007-033584 | Feb 2007 | JP |
| 2008-151986 | Jul 2008 | JP |
| 2010-113050 | May 2010 | JP |
| Entry |
|---|
| Official Communication issued in International Patent Application No. PCT/JP2013/064191, mailed on Jun. 25, 2013. |
| Number | Date | Country | |
|---|---|---|---|
| 20150145842 A1 | May 2015 | US |
