Patent Application
20240251640
This application claims the priority benefit of Republic of Korea Patent Application No. 10-2023-0009714, filed on Jan. 25, 2023, in the Korean Intellectual Property Office, which is incorporated herein by reference in its entirety.
The present disclosure relates to electronic devices, and more particularly, to a display device and a display panel including one or more optical electronic devices not exposed on front surfaces thereof.
As display technology advances, display devices can provide increased functions, such as an image capture function, a sensing function, and the like, as well as an image display function. To provide these functions, a display device may need to include one or more optical electronic devices, such as a camera, a sensor for detecting an image, and the like.
In order to receive light passing through a front surface of a display device, it may be desirable for such an optical electronic device to be located in an area of the display device where incident light coming from the front surface can be increasingly received and detected. To achieve the foregoing, in a typical display device, an optical electronic device has been designed to be located in a front portion of the display device to allow a camera, a sensor, and/or the like as the optical electronic device to be increasingly exposed to incident light. In order to install an optical electronic device in a display device in this manner, a bezel area of the display device may be increased, or a notch or a hole may be needed to be formed in a display area of an associated display panel.
Therefore, as a display device includes an optical electronic device to receive or detect incident light, and perform an intended function, a size of the bezel in the front portion of the display device may be increased, or a substantial disadvantage may be encountered in designing the front portion of the display device.
In addition, in instances where an optical electronic device is configured in a display device, the quality of images may be unexpectedly decreased and the performance of the optical electronic device may be impaired according to structures in which the optical electronic device is configured in the display device. For example, in an instance where the optical electronic device is a camera, image quality acquired by the camera may be decreased.
One or more embodiments of the present disclosure may provide a display panel and a display device that include a light transmission structure for enabling one or more optical electronic devices to normally receive light (e.g., visible light, infrared light, ultraviolet light, or the like) while not being exposed in a front surface of the display device.
One or more embodiments of the present disclosure may provide a display panel and a display device that are capable of preventing a pixel shrinkage phenomenon by shielding incident ultraviolet light from being transmitted inside of the display panel due to a structure in which one or more optical electronic devices are located under, or in a lower portion of, a display area of the display panel.
One or more embodiments of the present disclosure may provide a display panel and a display device that are capable of enabling a camera, which is an optical electronic device under, or in a lower portion of, a display area of the display panel, to acquire high quality images.
According to aspects of the present disclosure, a display device can be provided that includes an optical area included in a display area in which images can be displayed and allowing light to be transmitted, a normal area included in the display area and located outside of the optical area, a cathode electrode commonly disposed in the optical area and the normal area and including a plurality of cathode holes in the optical area, and a composite patterning layer corresponding to a corresponding one of the plurality of cathode holes and including a cathode patterning material and a ultraviolet light absorbing material.
According to aspects of the present disclosure, a display panel can be provided that includes a plurality of transmission areas included in a display area in which images can be displayed and allowing light to be transmitted, a cathode electrode including a plurality of cathode holes respectively corresponding to the plurality of transmission areas, and a composite patterning layer corresponding to a corresponding one of the plurality of cathode holes and including a cathode patterning material and a ultraviolet light absorbing material.
According to one or more embodiments of the present disclosure, a display panel and a display device may be provided that include a light transmission structure for enabling one or more optical electronic devices to normally receive light (e.g., visible light, infrared light, ultraviolet light, or the like) while not being exposed in a front surface of the display device.
According to one or more embodiments of the present disclosure, a display panel and a display device may be provided that are capable of preventing a pixel shrinkage phenomenon by shielding incident ultraviolet light from being transmitted inside of the display panel due to a structure in which one or more optical electronic devices are located under, or in a lower portion of, a display area of the display panel.
According to one or more embodiments of the present disclosure, a display panel and a display device may be provided that are capable of operating with low power consumption by preventing a pixel shrinkage phenomenon and improving the lifetime of pixels.
According to one or more embodiments of the present disclosure, a display panel and a display device may be provided that are capable of enabling a camera, which is an optical electronic device under, or in a lower portion of, a display area of the display panel, to acquire high quality images.
Additional features and aspects will be set forth in part in the description which follows and in part will become apparent from the description or may be learned by practice of the inventive concepts provided herein. Other features and aspects of the inventive concepts may be realized and attained by the structure particularly pointed out in, or derivable from, the written description, the claims hereof, and the appended drawings. Other systems, methods, features and advantages will be, or will become, apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the present disclosure, and be protected by the appended claims. Nothing in this section should be taken as a limitation on those claims.
It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are illustrative and explanatory and are not intended to limit the scope of the disclosure.
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of the disclosure, illustrate aspects of the disclosure and together with the description serve to explain principles of the disclosure. In the drawings:
The advantages and features of the present disclosure and methods of achieving the same will be apparent by referring to embodiments of the present disclosure as described below in detail with reference to the accompanying drawings. The present disclosure may however, be embodied in different forms and should not be construed as limited to the example embodiments set forth herein. Rather, these example embodiments are provided so that this disclosure may be sufficiently thorough and complete to assist those skilled in the art to fully understand the scope of the present disclosure. Further, the protected scope of the present disclosure is defined by claims and their equivalents.
Shapes, sizes, ratios, angles, numbers, and the like, which are illustrated in the drawings to describe various example embodiments of the present disclosure are merely given by way of example. Therefore, the present disclosure is not limited to the illustrations in the drawings. Like reference numerals designate like elements throughout, unless otherwise specified. Names of the respective elements used in the following explanations are selected only for convenience of writing the specification and may thus be different from those used in actual products. In the following description, where the detailed description of the relevant known function or configuration may unnecessarily obscure aspects of the present disclosure, a detailed description of such known function or configuration may be omitted. Where the terms “comprise,” “have,” “include,” “contain,” “constitute,” “make up of,” “formed of,” and the like are used, one or more other elements may be added unless the term, such as “only,” is used. An element described in the singular form is intended to include a plurality of elements, and vice versa, unless the context clearly indicates otherwise.
In construing an element, the element is to be construed as including an error or tolerance range even where no explicit description of such an error or tolerance range is provided. Further, the term “may ” fully encompasses all the meanings of the term “can.”
Where positional relationships are described, for example, where the positional relationship between two parts is described using “on,” “over,” “under,” “above,” “below,” “beside,” “next,” or the like, one or more other parts may be located between the two parts unless a more limiting term, such as “immediate(ly),” “direct(ly),” or “close(ly)” is used. For example, where an element or layer is disposed “on” another element or layer, a third element or layer may be interposed therebetween. Furthermore, the terms “left,” “right,” “top,” “bottom, “downward,” “upward,” “upper,” “lower,” and the like refer to an arbitrary frame of reference. For the expression that an element or layer “contacts,” “overlaps,” or the like with another element or layer, the element or layer can not only directly contact, overlap, or the like with another element or layer, but indirectly contact, overlap, or the like with another element or layer with one or more intervening elements or layers “disposed” or “interposed” between the elements or layers, unless otherwise specified.
Time relative terms, such as “after,” “subsequent to,” “next to,” “before,” or the like, used to describe a temporal relationship between events, operations, or the like are generally intended to include events, situations, cases, operations, or the like that do not occur consecutively unless the terms, such as “directly,” “immediately,” or the like, are used. In describing a temporal relationship, when the temporal order is described as, for example, “after,” “subsequent,” “next,” or “before,” a case which is not continuous may be included unless a more limiting term, such as “just,” “immediate(ly),” or “direct(ly),” is used.
Although the terms “first,” “second,” and the like may be used herein to describe various elements, these elements should not be interpreted to be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope.
For the expression that an element or layer is “connected,” “coupled,” or “adhered” to another element or layer, the element or layer can not only be directly connected, coupled, or adhered to another element or layer, but also be indirectly connected, coupled, or adhered to another element or layer with one or more intervening elements or layers “disposed” or “interposed” between the elements or layers, unless otherwise specified.
Hereinafter, various example embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In addition, for convenience of description, a scale in which each of elements is illustrated in the accompanying drawings may differ from an actual scale. Thus, the illustrated elements are not limited to the specific scale in which they are illustrated in the drawings. In describing example embodiments of the present disclosure, equated or corresponding elements or configurations as embodiment previously described will not be repeatedly discussed. Discussions on example embodiments of the present disclosure are provided below.
Referring to
The display panel 110 may include a display area DA in which one or more images can be displayed and a non-display area NDA in which an image is not displayed.
A plurality of subpixels may be arranged in the display area DA, and several types of signal lines for driving the plurality of subpixels may be arranged therein.
The non-display area NDA may refer to an area outside of the display area DA. Several types of signal lines may be arranged in the non-display area NDA, and several types of driving circuits may be connected thereto. At least a portion of the non-display area NDA may be bent to be invisible from the front surface of the display device 100 or may be covered by a case or housing (not shown) of the display device 100. The non-display area NDA may be also referred to as a bezel or a bezel area.
Referring to
Light can enter the front surface (the viewing surface) of the display panel 110, pass through the display panel 110, reach one or more optical electronic devices (11 and/or 12) located under, or in the lower portion of, the display panel 110 (the opposite side of the viewing surface). Light passing through the display panel 110 may include, for example, visible light, infrared light, or ultraviolet light.
The one or more optical electronic devices (11 and/or 12) may be devices capable of receiving or detecting light passing through the display panel 110 and perform a predefined function based on the received light. For example, the one or more optical electronic devices (11 and/or 12) may include one or more of the following: an image capture device such as a camera (an image sensor), and/or the like; or a sensor such as a proximity sensor, an illuminance sensor, and/or the like. Such a sensor may be, for example, an infrared sensor capable of detecting infrared light.
Referring to
According to an example of
According to an example of
According to an example of
In the display panel 110 or the display device 100 according to aspects of the present disclosure, it may be desirable that both an image display structure and a light transmission structure are implemented in the one or more optical areas (OA1 and/or OA2). For example, since the one or more optical areas (OA1 and/or OA2) are portions of the display area DA, it is therefore desirable that light emitting areas of subpixels for displaying one or more images are disposed in the one or more optical areas (OA1 and/or OA2). Further, to enable light to be transmitted through the one or more optical electronic devices (11 and/or 12), it may be desirable that a light transmission structure is implemented in the one or more optical areas (OA1 and/or OA2).
It should be noted that even though the one or more optical electronic devices (11 and/or 12) are devices that need to receive light, the one or more optical electronic devices (11 and/or 12) may be located on the back of the display panel 110 (e.g., on an opposite side of the viewing surface thereof), and thereby, can receive light that has passed through the display panel 110. For example, the one or more optical electronic devices (11 and/or 12) may not be exposed in the front surface (viewing surface) of the display panel 110 or the display device 100. Accordingly, when a user faces the front surface of the display device 110, the one or more optical electronic devices (11 and/or 12) are located so that they cannot be visible to the user.
The first optical electronic device 11 may be, for example, a camera, and the second optical electronic device 12 may be, for example, a sensor. The sensor may be a proximity sensor, an illuminance sensor, an infrared sensor, and/or the like. In one or more embodiments, the camera may be a camera lens, an image sensor, or a unit including at least one of the camera lens and the image sensor, and the sensor may be an infrared sensor capable of detecting infrared light. In another embodiment, the first optical electronic device 11 may be a sensor, and the second optical electronic device 12 may be a camera.
Hereinafter, for convenience of descriptions related to the optical electronic devices (11 and 12), the first optical electronic device 11 is considered to be a camera, and the second optical electronic device 12 is considered to be an infrared sensor. It should be, however, understood that the scope of the present disclosure includes examples where the first optical electronic device 11 is an infrared sensor, and the second optical electronic device 12 is a camera. The camera may be, for example, a camera lens, an image sensor, or a unit including at least one of the camera lens and the image sensor.
In an example where the first optical electronic device 11 is a camera, this camera may be located on the back of (e.g., under, or in a lower portion of) the display panel 110, and be a front camera capable of capturing objects or images in a front direction of the display panel 110. Accordingly, the user can capture an image or object through the camera that is invisible on the viewing surface while looking at the viewing surface of the display panel 110.
Although the normal area NA and the one or more optical areas (OA1 and/or OA2) included in the display area DA in each of
Accordingly, the one or more optical areas (OA1 and/or OA2) can have a transmittance greater than or equal to a predetermined level, i.e., a relatively high transmittance, and the normal area NA can have a transmittance less than the predetermined level or not have light transmittance.
For example, the one or more optical areas (OA1 and/or OA2) may have a resolution, a subpixel arrangement structure, a number of subpixels per unit area, an electrode structure, a line structure, an electrode arrangement structure, a line arrangement structure, and/or the like different from that/those of the normal area NA.
In one embodiment, the number of subpixels per unit area in the one or more optical areas (OA1 and/or OA2) may be less than the number of subpixels per unit area in the normal area NA. For example, the resolution of the one or more optical areas (OA1 and/or OA2) may be lower than that of the normal area NA. In this example, the number of subpixels per unit area may have the same meaning as a resolution, a pixel density, or a degree of integration of pixels. For example, the unit of the number of subpixels per unit area may be pixels per inch (PPI), which represents the number of pixels within 1 inch.
In the examples of
In one or more embodiments, as a method for increasing respective transmittance of at least one of the first optical area OA1 and the second optical area OA2, a pixel density differentiation design scheme as described above may be applied in which a difference in densities of pixels (or subpixels) or in degrees of integration of pixels (or subpixels) between the first optical area OA1, the second optical area OA2, and the normal area NA can be produced. According to the pixel density differentiation design scheme, in an embodiment, the display panel 110 may be configured or designed such that the number of subpixels per unit area of at least one of the first optical area OA1 and the second optical area OA2 is greater than the number of subpixels per unit area of the normal area NA.
In one or more embodiments, as another method for increasing respective transmittance of at least one of the first optical area OA1 and the second optical area OA2, a pixel size differentiation design scheme may be applied in which a difference in sizes of pixels (or subpixels) between the first optical area OA1, the second optical area OA2, and the normal area NA can be produced. According to the pixel size differentiation design scheme, the display panel PNL may be configured or designed such that while the number of subpixels per unit area of at least one of the first optical area OA1 and the second optical area OA2 is equal to or similar to the number of subpixels per unit area of the normal area NA, a size of each subpixel (i.e., a size of a corresponding light emitting area) disposed in at least one of the first optical area OA1 and the second optical area OA2 is smaller than a size of each subpixel (i.e., a size of a corresponding light emitting area) disposed in the normal area NA.
In one or more aspects, for convenience of description, discussions that follow are provided based on the pixel density differentiation design scheme of the two schemes (i.e., the pixel density differentiation design scheme and the pixel size differentiation design scheme) for increasing respective transmittance of at least one of the first optical area OA1 and the second optical area OA2, unless explicitly stated otherwise. It should be therefore understood that in descriptions that follow, a small number of subpixels per unit area may be considered as corresponding to a small size of subpixel, and a large number of subpixels per unit area may be considered as corresponding to a large size of subpixel.
In the examples of
Referring to
According to one or more aspects of the present disclosure, when the display device 100 has a structure in which the first optical electronic device 11 such as a camera, and the like is located under, or in a lower portion of, the display panel 100 without being exposed to the outside, such a display device may be referred to as a display to which a under-display camera (UDC) technology is applied.
The display device 100 to which such an under-display camera (UDC) technology is applied can provide an advantage of preventing a reduction of an area or size of the display area DA because a notch or a camera hole for exposing a camera need not be formed in the display panel 110. Indeed, since a notch or a camera hole for camera exposure need not be formed in the display panel 110, the display device 100 can provide further advantages of reducing the size of a bezel area, and improving the degree of freedom in design because such limitations to the design are removed.
Although the one or more optical electronic devices (11 and/or 12) are located on the back of (e.g., under, or in a lower portion of) the display panel 110 of the display device 100 (e.g., hidden or not exposed to the outside), the one or more optical electronic devices (11 and/or 12) are required to perform their normal predefined functionalities by receiving or detecting light.
Further, although one or more optical electronic devices (11 and/or 12) are located on the back of (e.g., under, or in a lower portion of) the display panel 110 to be hidden and located to be overlap the display area DA, it is desirable that the display device 100 is configured to normally display one or more images in the one or more optical areas (OA1 and/or OA2) overlapping the one or more optical electronic devices (11 and/or 12) in the display area DA. Thus, even though one or more optical electronic devices (11 and/or 12) are located on the back of the display panel, the display device 100 according to aspects of the present disclosure can be configured to display images in a normal manner (e.g., without reduction in image quality) in the one or more optical areas (OA1 and/or OA2) overlapping the one or more optical electronic devices (11 and/or 12) in the display area DA.
Since the foregoing first optical area OA1 is configured or designed as a transmittable area, the quality of image display in the first optical area OA1 may be different from the quality of image display in the normal area NA.
Further, when designing the first optical area OA1 for the purpose of improving the quality of image display, there may be caused a situation that the transmittance of the first optical area OA1 is reduced.
To address these issues, as described below, one or more embodiments may provide a structure of the first optical area OA1 that is capable of preventing the occurrence of a difference (e.g., non-uniformity) in image quality between the first optical area OA1 and the normal area NA, and improving the transmittance of the first optical area OA1.
Further, one or more embodiments may provide not only the structure of the first optical area OA1, but a structure of the second optical area OA2 that is capable of improving the image quality of the second optical area OA2, and improving the transmittance of the second optical area OA2.
It should be also noted that the first optical area OA1 and the second optical area OA2 included in the display device 100 or the display panel 110 according to aspects of the present disclosure may be differently implemented or have different utilization examples while having a similarity in terms of light transmittable areas. Taking account of such a distinction, the structure of the first optical area OA1 and the structure of the second optical area OA2 in the display device 100 according to aspects of the present disclosure may be configured or designed differently from each other.
Referring to
The display driving circuit may be a circuit for driving the display panel 110, and include a data driving circuit 220, a gate driving circuit 230, a display controller 240, and other circuit components.
The display panel 110 may include a display area DA in which one or more images can be displayed and a non-display area NDA in which an image is not displayed. The non-display area NDA may be an area outside of the display area DA, and may also be referred to as an edge area or a bezel area. All or a portion of the non-display area NDA may be an area visible from the front surface of the display device 100, or an area that is bent and invisible from the front surface of the display device 100.
The display panel 110 may include a substrate SUB and a plurality of subpixels SP disposed on the substrate SUB. The display panel 110 may further include various types of signal lines to drive the plurality of subpixels SP.
In one or more embodiments, the display device 100 according to aspects of the present disclosure may be a liquid crystal display device, or the like, or a self-emission display device in which light is emitted from the display panel 110 itself. In the example where the display device 100 according to aspects of the present disclosure is implemented as a self-emission display device, each of the plurality of subpixels SP may include a light emitting element. For example, the display device 100 according to aspects of the present disclosure may be an organic light emitting display device implemented with one or more organic light emitting diodes (OLED). In another example, the display device 100 according to aspects of the present disclosure may be an inorganic light emitting display device implemented with one or more inorganic material-based light emitting diodes. In further another example, the display device 100 according to aspects of the present disclosure may be a quantum dot display device implemented with quantum dots, which are self-emission semiconductor crystals.
The structure of each of the plurality of subpixels SP may be differently configured or designed according to types of the display devices 100. For example, in an example where the display device 100 is a self-emission display device including self-emission subpixels SP, each subpixel SP may include a self-emission light emitting element, one or more transistors, and one or more capacitors.
In one or more embodiments, various types of signal lines arranged in the display device 100 may include, for example, a plurality of data lines DL for carrying data signals (which may be referred to as data voltages or image signals), a plurality of gate lines GL for carrying gate signals (which may be referred to as scan signals), and the like.
The plurality of data lines DL and the plurality of gate lines GL may intersect each other. Each of the plurality of data lines DL may extend in a first direction. Each of the plurality of gate lines GL may extend in a second direction different from the first direction. For example, the first direction may be a column or vertical direction, and the second direction may be a row or horizontal direction. In another example, the first direction may be the row or horizontal direction, and the second direction may be the column or vertical direction.
The data driving circuit 220 may be a circuit for driving the plurality of data lines DL, and can supply data signals to the plurality of data lines DL. The gate driving circuit 230 may be a circuit for driving the plurality of gate lines GL, and can supply gate signals to the plurality of gate lines GL.
The display controller 240 may be a device for controlling the data driving circuit 220 and the gate driving circuit 230, and can control driving times for the plurality of data lines DL and driving times for the plurality of gate lines GL.
The display controller 240 can supply a data driving control signal DCS to the data driving circuit 220 to control the data driving circuit 220, and supply a gate driving control signal GCS to the gate driving circuit 230 to control the gate driving circuit 230.
The display controller 240 can receive input image data from a host system 250 and supply image data Data to the data driving circuit 220 based on the input image data.
The data driving circuit 220 can receive digital image data Data from the display controller 240, convert the received image data Data into analog data signals, and supply the resulting analog data signals to the plurality of data lines DL.
The gate driving circuit 230 can receive a first gate voltage corresponding to a turn-on level voltage and a second gate voltage corresponding to a turn-off level voltage along with various gate driving control signals GCS, generate gate signals, and supply the generated gate signals to the plurality of gate lines GL.
In one or more embodiments, the data driving circuit 220 may be connected to the display panel 110 in a tape automated bonding (TAB) type, or connected to a conductive pad such as a bonding pad of the display panel 110 in a chip on glass (COG) type or a chip on panel (COP) type, or connected to the display panel 110 in a chip on film (COF) type.
In one or more embodiments, the gate driving circuit 230 may be connected to the display panel 110 in the tape automated bonding (TAB) type, or connected to a conductive pad such as a bonding pad of the display panel 110 in the chip on glass (COG) type or the chip on panel (COP) type, or connected to the display panel 110 in the chip on film (COF) type. In another embodiment, the gate driving circuit 230 may be disposed in the non-display area NDA of the display panel 110 in a gate in panel (GIP) type. The gate driving circuit 230 may be disposed on the substrate, or connected to the substrate. That is, in the case of the GIP type, the gate driving circuit 230 may be disposed in the non-display area NDA of the substrate. In the case of the chip on glass (COG) type, the chip on film (COF) type, or the like, the gate driving circuit 230 may be connected to the substrate.
In one or more embodiments, at least one of the data driving circuit 220 and the gate driving circuit 230 may be disposed in the display area DA of the display panel 110. For example, at least one of the data driving circuit 220 and the gate driving circuit 230 may be disposed such that it does not overlap subpixels SP, or disposed such that it overlaps one or more, or all, of the subpixels SP, or at least respective one or more portions of one or more subpixels.
The data driving circuit 220 may be located in, and/or electrically connected to, but not limited to, only one side or portion (e.g., an upper edge or a lower edge) of the display panel 110. In one or more embodiments, the data driving circuit 220 may be located in, and/or electrically connected to, but not limited to, two sides or portions (e.g., an upper edge and a lower edge) of the display panel 110 or at least two of four sides or portions (e.g., the upper edge, the lower edge, a left edge, and a right edge) of the display panel 110 according to driving schemes, panel design schemes, or the like.
The gate driving circuit 230 may be located in, and/or electrically connected to, but not limited to, only one side or portion (e.g., a left edge or a right edge) of the display panel 110. In one or more embodiments, the gate driving circuit 230 may be located in, and/or electrically connected to, but not limited to, two sides or portions (e.g., a left edge and a right edge) of the panel 110 or at least two of four sides or portions (e.g., an upper edge, a lower edge, the left edge, and the right edge) of the panel 110 according to driving schemes, panel design schemes, or the like.
The display controller 240 may be implemented in a separate component from the data driving circuit 220, or incorporated in the data driving circuit 220 and thus implemented in an integrated circuit.
The display controller 240 may be a timing controller used in the typical display technology or a controller or a control device capable of performing other control functions in addition to the function of the typical timing controller. In one or more embodiments, the display controller 140 may be a controller or a control device different from the timing controller, or a circuitry or a component included in the controller or the control device. The display controller 240 may be implemented with various circuits or electronic components such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a processor, and/or the like.
The display controller 240 may be mounted on a printed circuit board, a flexible printed circuit, and/or the like and be electrically connected to the gate driving circuit 220 and the data driving circuit 230 through the printed circuit board, flexible printed circuit, and/or the like.
The display controller 240 may transmit signals to, and receive signals from, the data driving circuit 220 via one or more predefined interfaces. For example, such interfaces may include a low voltage differential signaling (LVDS) interface, an embedded clock point-point interface (EPI), a serial peripheral interface (SPI), and the like.
In one or more embodiments, in order to further provide a touch sensing function, as well as an image display function, the display device 100 according to aspects of the present disclosure may include at least one touch sensor, and a touch sensing circuit capable of detecting the occurrence of a touch event by a touch object such as a finger, a pen, or the like, or of detecting a corresponding touch position (or touch coordinates), by sensing the touch sensor.
The touch sensing circuit may include: a touch driving circuit 260 capable of generating and providing touch sensing data by driving and sensing the touch sensor; a touch controller 270 capable of detecting the occurrence of a touch event or detecting a touch position (or touch coordinates) using the touch sensing data; and one or more other components.
The touch sensor may include a plurality of touch electrodes. The touch sensor may further include a plurality of touch lines for electrically connecting the plurality of touch electrodes to the touch driving circuit 260.
The touch sensor may be implemented in the form of a touch panel outside of the display panel 110 or be integrated inside of the display panel 110. In the example where the touch sensor is implemented in the form of the touch panel outside of the display panel 110, such a touch sensor may be referred to as an add-on type. In the example where the add-on type of touch sensor is disposed in the display device 100, the touch panel and the display panel 110 may be separately manufactured and combined in an assembly process. The add-on type of touch panel may include a touch panel substrate and a plurality of touch electrodes on the touch panel substrate.
In the example where the touch sensor is integrated inside of the display panel 110, the touch sensor may be formed on the substrate SUB together with signal lines and electrodes related to display driving during a process of manufacturing the display panel 110.
The touch driving circuit 260 can supply a touch driving signal to at least one of a plurality of touch electrodes, and sense at least one of the plurality of touch electrodes to generate touch sensing data.
The touch sensing circuit can perform touch sensing using a self-capacitance sensing technique or a mutual-capacitance sensing technique.
In the example where the touch sensing circuit performs touch sensing using the self-capacitance sensing technique, the touch sensing circuit can perform touch sensing based on capacitance between each touch electrode and a touch object (e.g., a finger, a pen, and the like). According to the self-capacitance sensing technique, each of the plurality of touch electrodes can serve as both a driving touch electrode and a sensing touch electrode. The touch driving circuit 260 can drive all, or one or more, of the plurality of touch electrodes and sense all, or one or more, of the plurality of touch electrodes.
In the example where the touch sensing circuit performs touch sensing using the mutual-capacitance sensing technique, the touch sensing circuit can perform touch sensing based on capacitance between touch electrodes. According to the mutual-capacitance sensing technique, the plurality of touch electrodes are divided into driving touch electrodes and sensing touch electrodes. The touch driving circuit 260 can drive the driving touch electrodes and sense the sensing touch electrodes.
The touch driving circuit 260 and the touch controller 270 included in the touch sensing circuit may be implemented in separate devices or in a single device. Further, the touch driving circuit 260 and the data driving circuit 220 may be implemented in separate devices or in a single device.
The display device 100 may further include a power supply circuit for supplying various types of power to the display driving circuit and/or the touch sensing circuit.
In one or more embodiments, the display device 100 according to aspects of the present disclosure may represent, but not limited to, a mobile terminal, such as a smart phone, a tablet, or the like, a monitor, a television (TV), or the like. Embodiments of the present disclosure are not limited thereto. In one or more embodiments, the display device 100 may be display devices, or include displays, of various types, sizes, and shapes for displaying information or images.
As described above, the display area DA of the display panel 110 may include the normal area NA and the one or more optical areas (OA1 and/or OA2) as illustrated in
As discussed above with respect to the examples of
Referring to
Referring to
Referring to
The driving transistor DT may include the first node N1 to which a data voltage is applied, a second node N2 electrically connected to the light emitting element ED, and a third node N3 to which a driving voltage ELVDD through a driving voltage line DVL is applied. In the driving transistor DT, the first node N1 may be a gate node, the second node N2 may be a source node or a drain node, and the third node N3 may be the drain node or the source node. For convenience of description, descriptions that follow will be provided based on examples where the first, second and third nodes (N1, N2 and N3) of the driving transistor DT are gate, source and drain nodes, respectively, unless explicitly stated otherwise. However, it should be understood that the scope of the present disclosure includes examples where the first, second and third nodes (N1, N2 and N3) of the driving transistor DT are gate, drain and source nodes, respectively.
The light emitting element ED may include an anode electrode AE, an emission layer EL, and a cathode electrode CE. The anode electrode AE may represent a pixel electrode disposed in each subpixel SP, and may be electrically connected to the second node N2 of the driving transistor DT of each subpixel SP. The cathode electrode CE may represent a common electrode being disposed in the plurality of subpixels SP in common, and a base voltage ELVSS such as a low-level voltage, a ground voltage, or the like may be applied to the cathode electrode CE.
For example, the anode electrode AE may be a pixel electrode, and the cathode electrode CE may be a common electrode. In another example, the anode electrode AE may be a common electrode, and the cathode electrode CE may be a pixel electrode. For convenience of description, discussions that follow will be provided based on examples where the anode electrode AE is a pixel electrode, and the cathode electrode CE is a common electrode unless explicitly stated otherwise. However, it should be understood that the scope of the present disclosure includes examples where the anode electrode AE is a common electrode, and the cathode electrode CE is a pixel electrode.
The light emitting element ED may include a light emitting area EA having a predetermined size or area. The light emitting area EA of the light emitting element ED may be defined as, for example, an area in which the anode electrode AE, the emission layer EL, and the cathode electrode CE overlap one another.
The light emitting element ED may be, for example, an organic light emitting diode (OLED), an inorganic light emitting diode, a quantum dot light emitting element, or the like. In the example where an organic light emitting diode (OLED) is used as the light emitting element ED, the emission layer EL thereof may include an organic emission layer including an organic material.
The scan transistor ST can be turned on and off by a scan signal SCAN, which is a gate signal applied through a gate line GL, and be electrically connected between the first node N1 of the driving transistor DT and a data line DL.
The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DT.
The pixel circuit SPC may be configured with two transistors (2T: DRT and SCT) and one capacitor (1C: Cst) (which may be referred to as a “2T1C structure”) as shown in
In one or more embodiments, the storage capacitor Cst, which may be present between the first node N1 and the second node N2 of the driving transistor DT, may be an external capacitor intentionally configured or designed to be located outside of the driving transistor DT, other than internal capacitors, such as parasitic capacitors (e.g., a gate-to-source capacitance Cgs, a gate-to-drain capacitance Cgd, and the like). Each of the driving transistor DT and the scan transistor ST may be an n-type transistor or a p-type transistor.
Since circuit elements (in particular, a light emitting element ED implemented with an organic light emitting diode including an organic material) included in each subpixel SP are vulnerable to external moisture or oxygen, an encapsulation layer ENCAP may be disposed in the display panel 110 in order to prevent external moisture or oxygen from penetrating into such circuit elements. The encapsulation layer ENCAP may be disposed such that it covers the light emitting element ED.
Hereinafter, for convenience of description, the term “optical area OA” is used instead of distinctly describing the first optical area OA1 and the second optical area OA2 described above. Thus, it should be noted that an optical area described below may represent any one or both of the first and second optical area OA1 and OA2 described above, unless explicitly stated otherwise.
Likewise, for convenience of description, the term “optical electronic device” is used instead of distinctly describing the first optical electronic device 11 and the second optical electronic device 12 described above. Thus, it should be noted that an optical electronic device described below may represent any one or both of the first and second optical electronic device 11 and 12 described above, unless explicitly stated otherwise.
Hereinafter, an example first type of optical area OA will be described with reference to
The first type of optical area OA and the second type of optical area OA are briefly described as follows.
In the case of the first type of optical area OA, one or more pixel circuits SPC for driving one or more light emitting elements ED disposed in the optical area OA may be disposed in an area outside of the optical area OA without being in the optical area OA.
In the case of the second type of optical area OA, one or more pixel circuits SPC for driving one or more light emitting elements ED disposed in the optical area OA may be disposed the optical area OA.
Referring to
Referring to
The optical area OA of the type shown in
In other words, when the optical area OA is implemented in the first type, the display area DA may include the optical area OA, the normal area NA located outside of the optical area OA, and the optical bezel area OBA between the optical area OA and the normal area NA.
Referring to
The light passing through the optical area OA may include light of a single wavelength band or light of various wavelength bands. For example, the optical area OA may be configured to allow, but not limited to, at least one of visible light, infrared light, ultraviolet light, and the like to be transmitted.
An optical electronic device disposed in the optical area OA can receive light passing through the optical area OA and perform a predefined operation using the received light. The light received by the optical electronic device through the optical area OA may include at least one of visible light, infrared light, and ultraviolet light.
For example, in an example where the optical electronic device is a camera, the light used for the predefined operation of the optical electronic device, which has passed through the optical area OA, may include visible light.
In another example, in an example where the optical electronic device is an infrared sensor, the light used for the predefined operation of the optical electronic device, which has passed through the optical area OA, may include infrared (also referred to as infrared light).
Referring to
For example, the optical bezel area OBA may be disposed outside of only a portion of an edge of the optical area OA, or disposed outside of the entire edge of the optical area OA.
In the example where the optical bezel area OBA is disposed outside of the entire edge of the optical area OA, the optical bezel area OBA may have a ring shape surrounding the optical area OA.
For example, the optical area OA may have various shapes such as a circular shape, an elliptical shape, a polygonal shape, an irregular shape, or the like. The optical bezel area OBA may have various ring shapes (e.g., a circular ring shape, an elliptical ring shape, a polygonal ring shape, an irregular ring shape, or the like) surrounding the optical area OA having various shapes.
Referring to
For example, the plurality of light emitting areas EA may include a first color light emitting area emitting light of a first color, a second color light emitting area emitting light of a second color, and a third color light emitting area emitting light of a third color.
At least one of the first color light emitting area, the second color light emitting area, and the third color light emitting area may have a different area or size from the remaining one or more light emitting areas.
The first color, the second color, and the third color may be different colors from one another, and may be various colors. For example, the first color, second color, and third color may be or include red, green, and blue, respectively.
Hereinafter, for convenience of description, the first color, the second color, and the third color are considered to be red, green, and blue, respectively. However, embodiments of the present disclosure are not limited thereto.
In the example where the first color, the second color, and the third color are red, green, and blue, respectively, an area of a blue light emitting area EA_B may be greater than an area of a red light emitting area EA_R and an area of a green light emitting area EA_G.
A light emitting element ED disposed in the red light emitting area EA_R may include an emission layer EL emitting red light. A light emitting element ED disposed in the green light emitting area EA_G may include an emission layer EL emitting green light. A light emitting element ED disposed in the blue light emitting area EA_B may include an emission layer EL emitting blue light.
An organic material included in the emission layer EL emitting blue light may be more easily degraded in terms of material than respective organic materials included in the emission layer EL emitting red light and the emission layer EL emitting green light.
In one or more embodiments, as the blue light emitting area EA_B is configured or designed to have the largest area or size, current density supplied to the light emitting element ED disposed in the blue light emitting area EA_B may be the least. Therefore, a degradation degree of a light emitting element ED disposed in the blue light emitting area EA_B may be similar to a degradation degree of a light emitting element ED disposed in the red light emitting area EA_R and a degradation degree of a light emitting element ED disposed in the green light emitting area EA_G.
In consequence, a difference in degradation between the light emitting element ED disposed in the red light emitting area EA_R, the light emitting elements ED disposed in the green light emitting area EA_G, and the light emitting elements ED disposed in the blue light emitting area EA_B cannot be produced or can be reduced, and therefore, the display device 100 or the display panel 110 according to aspects of the present disclosure can provide an advantage of improving image quality. In addition, as a difference in degradation between the light emitting element ED disposed in the red light emitting area EA_R, the light emitting elements ED disposed in the green light emitting area EA_G, and the light emitting elements ED disposed in the blue light emitting area EA_B is eliminated or reduced, the display device 100 or the display panel 110 according to aspects of the present disclosure can therefore provide an advantage of reducing a difference in lifespan between the light emitting element ED disposed in the red light emitting area EA_R, the light emitting elements ED disposed in the green light emitting area EA_G, and the light emitting elements ED disposed in the blue light emitting area EA_B.
Referring to
Referring to
In one or more embodiments, the cathode electrode CE may not include a cathode hole CH in the optical bezel area OBA. That is, in the optical bezel area OBA, the cathode electrode CE may not include a cathode hole CH.
In the optical area OA, the plurality of cathode holes CH formed in the cathode electrode CE may be referred to as a plurality of transmission areas TA or a plurality of opening areas. Although
It should be understood here that each of the pixel circuits (SPC1, SPC2, SPC3, and SPC4) may include transistors (DT and ST), a storage capacitor Cst, and the like as shown in
Referring to
As one example of such structural differences, one or more pixel circuits (SPC1, SPC2, SPC3, and/or SPC4) may be disposed in the optical bezel area OBA and the normal area NA, but a pixel circuit may not be disposed in the optical area OA. For example, the optical bezel area OBA and the normal area NA may be configured to allow one or more transistors (DT1, DT2, DT3, and/or DT4) to be disposed therein, but the optical area OA may be configured not to allow a transistor to be disposed therein.
Transistors and storage capacitors included in the pixel circuits (SPC1, SPC2, SPC3, and SPC4) may be components causing transmittance to be reduced. Thus, since a pixel circuit (e.g., SPC1, SPC2, SPC3, or SPC4) is not disposed in the optical area OA, the transmittance of the optical area OA can be more improved.
In one or more embodiments, although the pixel circuits (SPC1, SPC2, SPC3, and SPC4) may be disposed only in the normal area NA and the optical bezel area OBA, the light emitting elements (ED1, ED2, ED3, and ED4) may be disposed in the normal area NA, the optical bezel area OBA, and the optical area OA.
Referring to
Referring to
Hereinafter, the normal area NA, the optical area OA, and the optical bezel area OBA will be described in more detail.
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
The anode extension line AEL may electrically extend or connect an anode electrode AE of the first light emitting element ED1 to a second node N2 of the first driving transistor DT1 in the first pixel circuit SPC1.
As described above, in one or more embodiments, in the display panel 110 according to aspects of the present disclosure, the first pixel circuit SPC1 for driving the first light emitting element ED1 disposed in the optical area OA may be disposed in the optical bezel area OBA, not in the optical area OA. Such a structure may be referred to as an anode extension structure. Likewise, the first type of the optical area OA may be also referred to as an anode extension type.
In an embodiment where the display panel 110 according to aspects of the present disclosure has such an anode extension structure, all or a portion of the anode extension line AEL may be disposed in optical area OA, and the anode extension line AEL may include a transparent material, or be or include a transparent line. Accordingly, even when the anode extension line AEL for connecting the first pixel circuit SPC1 to the first light emitting element ED1 is disposed in the optical area OA, the display device or the display panel 110 according to aspects of the present disclosure can prevent the transmittance of the optical area OA from being reduced.
Referring to
Referring to
Referring to
Referring to
Referring to
Referring to
All or a portion of the anode extension line AEL may be disposed in the optical area OA, and the anode extension line AEL may include a transparent material, or be or include a transparent line.
As described above, the first pixel circuit SPC1 disposed in the optical bezel area OBA may be configured to drive one light emitting element ED1 disposed in the optical area OA. Such a circuit connection scheme may be referred to as a one-to-one (1:1) circuit connection scheme.
As a result, the number of pixel circuits SPC disposed in the optical bezel area OBA may be increased significantly. Further, the structure of the optical bezel area OBA may become complicated, and an open area (or an aperture ratio, or a light emitting area) of the optical bezel area OBA may be reduced. Herein, the open area may be referred to as a light emitting area, and may also be referred to as an open ratio or an aperture ratio.
In order to increase an open area of the optical bezel area OBA while having an anode extension structure, in one or more embodiments, the display device 100 according to aspects of the present disclosure may be configured in a 1:N (where N is 2 or more) circuit connection scheme.
According to the 1:N circuit connection scheme, the first pixel circuit SPC1 disposed in the optical bezel area OBA may be configured to drive two light emitting elements ED disposed in the optical area OA concurrently or together.
In one or more embodiments, referring to
Referring to
Accordingly, even when the display panel 110 has an anode extension structure, the number of pixel circuits SPC disposed in the optical bezel area OBA can be reduced, and thereby, an opening area and a light emitting area of the optical bezel area OBA can be increased.
In the example of
Referring to
Referring to
Referring to
The cathode electrode CE may include a plurality of cathode holes CH, and the plurality of cathode holes CH of the cathode electrode CE may be disposed in the optical area OA.
The normal area NA and the optical bezel area OBA may be areas through which light cannot be transmitted, and the optical area OA may be an area through which light can be transmitted. Accordingly, the transmittance of the optical area OA may be higher than respective transmittance of the optical bezel area OBA and the normal area NA.
All of the optical area OA may be an area through which light can be transmitted, and the plurality of cathode holes CH of the optical area OA may be transmittable areas TA through which light can be transmitted more effectively. For example, the remaining area except for the plurality of cathode holes CH in the optical area OA may be an area through which light can be transmitted, and respective transmittance of the plurality of cathode holes CH in the optical area OA may be higher than the transmittance of the remaining area except for the plurality of cathode holes (CH) in the optical area OA.
In another example, the plurality of cathode holes CH in the optical area OA may be transmission areas TA through which light can be transmitted, and the remaining area except for the plurality of cathode holes CH in the optical area OA may be an area through which light cannot be transmitted.
Referring to
Referring to
Referring to
Referring to
In one or more embodiments, the display panel 110 according to aspects of the present disclosure may further include a cathode electrode (e.g., the cathode electrode CE in
In one or more embodiments, the display panel 110 according to aspects of the present disclosure may include a first emission layer EL1 disposed in the optical area OA, a second emission layer EL2 disposed in the optical bezel area OBA, a third emission layer EL3 disposed in the normal area NA, and a fourth emission layer EL4 disposed in the optical area OA.
The first to fourth emission layers EL4 may be emission layers emitting light of a same color. In these embodiments, the first to fourth emission layers EL1 to EL4 may be disposed as separate emission layers or be integrated into a single emission layer.
Referring to
Hereinafter, a cross-sectional structure taken along line X-Y of
A portion indicated by line X-Y in
The portion indicated by line X-Y in
Referring to
The transistor forming part may include a substrate SUB, a first buffer layer BUF1 on the substrate SUB, various types of transistors DT1 and DT2 formed on the first buffer layer BUF, a storage capacitor Cst, and various electrodes and signal lines.
The substrate SUB may include, for example, a first substrate SUB1 and a second substrate SUB2, and may include an intermediate layer INTL interposed between the first substrate SUB1 and the second substrate SUB2. In this example, the intermediate layer INTL may be an inorganic layer and can serve to prevent moisture permeation.
A lower shield metal BSM may be disposed over the substrate SUB. The lower shield metal BSM may be located under a first active layer ACT1 of a first driving transistor DT1.
The first buffer layer BUF1 may include a stack of a single layer or a stack of multiple layers. In an example where the first buffer layer BUF1 includes a stack of multilayer, the first buffer layer BUF1 may include a multi-buffer layer MBUF and an active buffer layer ABUF.
Various types of transistors (DT1, DT2, and the like), at least one storage capacitor Cst, and various electrodes or signal lines may be disposed on the first buffer layer BUF1.
For example, the transistors DT1 and DT2 formed on the first buffer layer BUF1 may include a same material, and be located in one or more same layers. In another example, as shown in
Referring to
For example, the first driving transistor DT1 may represent a driving transistor included in the first pixel circuit SPC1 for driving the first light emitting element ED1 included in the optical area OA, and the second driving transistor DT2 may represent a driving transistor included in the second pixel circuit SPC2 for driving the second light emitting element ED2 included in the optical bezel area OBA.
Stackup configurations of the first driving transistor DT1 and the second driving transistor DT2 will be described below.
The first driving transistor DT1 may include the first active layer ACT1, a first gate electrode G1, a first source electrode S1, and a first drain electrode D1.
The second driving transistor DT2 may include a second active layer ACT2, a second gate electrode G2, a second source electrode S2, and a second drain electrode D2.
The second active layer ACT2 of the second driving transistor DT2 may be located in a higher location in the stackup configuration than the first active layer ACT1 of the first driving transistor DT1.
The first buffer layer BUF1 may be disposed under the first active layer ACT1 of the first driving transistor DT1, and the second buffer layer BUF2 may be disposed under the second active layer ACT2 of the second driving transistor DT2.
For example, the first active layer ACT1 of the first driving transistor DT1 may be located on the first buffer layer BUF1, and the second active layer ACT2 of the second driving transistor DT2 may be located on the second buffer layer BUF2. In this case, the second buffer layer BUF2 may be placed in a higher location than the first buffer layer BUF.
The first active layer ACT1 of the first driving transistor DT1 may be disposed on the first buffer layer BUF1, and a first gate insulating layer GI1 may be disposed on the first active layer ACT1 of the first driving transistor DT1. The first gate electrode G1 of the first driving transistor DT1 may be disposed on the first gate insulating layer GI1, and a first interlayer insulating layer ILD1 may be disposed on the first gate electrode G1 of the first driving transistor DT1.
In this implementation, the first active layer ACT1 of the first driving transistor DT1 may include a first channel region overlapping the first gate electrode G1, a first source connection region located on one side of the first channel region, and a first drain connection region located on the other side of the first channel region.
The second buffer layer BUF2 may be disposed on the first interlayer insulating layer ILD1.
The second active layer ACT2 of the second driving transistor DT2 may be disposed on the second buffer layer BUF2, and a second gate insulating layer GI2 may be disposed on the second active layer ACT2. The second gate electrode G2 of the second driving transistor DT2 may be disposed on the second gate insulating layer GI2, and a second interlayer insulating layer ILD2 may be disposed on the second gate electrode G2.
In this implementation, the second active layer ACT2 of the second driving transistor DT2 may include a second channel region overlapping the second gate electrode G2, a second source connection region located on one side of the second channel region, and a second drain connection region located on the other side of the second channel region.
The first source electrode S1 and the first drain electrode D1 of the first driving transistor DT1 may be disposed on the second interlayer insulating layer ILD2. The second source electrode S2 and the second drain electrode D2 of the second driving transistor DT2 may be also disposed on the second interlayer insulating layer ILD2.
The first source electrode S1 and the first drain electrode D1 of the first driving transistor DT1 may be respectively connected to the first source connection region and the first drain connection region of the first active layer ACT1 through through-holes formed in the second interlayer insulating layer ILD2, the second gate insulating layer GI2, the second buffer layer BUF2, the first interlayer insulating layer ILD1, and the first gate insulating layer GI1.
The second source electrode S2 and the second drain electrode D21 of the second driving transistor DT2 may be respectively connected to the second source connection region and the second drain connection region of the second active layer ACT2 through through-holes formed in the second interlayer insulating layer ILD2 and the second gate insulating layer GI2.
It should be understood that
Referring to
The first capacitor electrode PLT1 may be electrically connected to the second gate electrode G2 of the second driving transistor DT2, and the second capacitor electrode PLT2 may be electrically connected to the second source electrode S2 of the second driving transistor DT2.
In one or more embodiments, referring to
The lower metal BML may be electrically connected to, for example, the second gate electrode G2. In another example, the lower metal BML can serve as a light shield for shielding light traveling from a lower location than the lower metal BML. In this implementation, the lower metal BML may be electrically connected to the second source electrode S2.
Even though the first driving transistor DT1 is a transistor for driving the first light emitting element ED1 disposed in the optical area OA, the first driving transistor DT1 may be disposed in the optical bezel area OBA, not the optical area OA.
The second driving transistor DT2, which is a transistor for driving the second light emitting element ED2 disposed in the optical bezel area OBA, may be disposed in the optical bezel area OBA.
Referring to
Referring to
Referring to
The first relay electrode RE1 may represent an electrode for relaying an electrical interconnection between the first source electrode S1 of the first driving transistor DT1 and a first anode electrode AE1 of the first light emitting element ED1. The second relay electrode RE2 may represent an electrode for relaying an electrical interconnection between the second source electrode S2 of the second driving transistor DT2 and a second anode electrode AE2 of the second light emitting element ED2.
The first relay electrode RE1 may be electrically connected to the first source electrode S1 of the first driving transistor DT1 through a hole formed in the first planarization layer PLN1. The second relay electrode RE2 may be electrically connected to the second source electrode S2 of the second driving transistor DT2 through another hole formed in the first planarization layer PLN1.
Referring to
Referring to
In one or more embodiments, referring to
Referring to
Referring to
Referring to
Referring to
In the example of
Referring to
Referring to
The second anode electrode AE2 may be connected to the second relay electrode RE2 through a hole formed in the second planarization layer PLN2.
The first anode electrode AE1 may be connected to an anode extension line AEL extending from the optical bezel area OBA to the optical area OA through another hole formed in the second planarization layer PLN2.
The fourth anode electrode AE4 may be connected to another anode extension line AEL extending from the optical bezel area OBA to the optical area OA through further another hole formed in the second planarization layer PLN2.
Referring to
The bank BK may include a plurality of bank holes, and respective portions of the first anode electrode AE1, the second anode electrode AE2, and the fourth anode electrode AE4 may be exposed through respective bank holes. That is, the plurality of bank holes formed in the bank BK may respectively overlap the respective portions of the first anode electrode AE1, the second anode electrode AE2, and the fourth anode electrode AE4.
Referring to
Referring to
Referring to
Referring to
Since the composite patterning layer MVL includes ultraviolet light absorbing material, a pixel shrinkage phenomenon can be prevented because the composite patterning layer MVL absorbs ultraviolet light incident through the optical area OA, particularly a cathode hole CH, and shields the transmission of the ultraviolet light inside of the display panel.
The weight ratio of the cathode patterning material to the ultraviolet light absorbing material included in the composite patterning layer MVL may be in a range from 1:1 to 10:1. If the weight ratio of the cathode patterning material to the ultraviolet light absorbing material included in the composite patterning layer is less than about 1:1, since the content of the ultraviolet light absorbing material is relatively greater than the content of the cathode patterning material, a material forming the cathode electrode CE may adhere to the composite patterning layer, and thereby, the cathode hole may not be formed uniformly. If the weight ratio of the cathode patterning material to the ultraviolet light absorbing material included in the composite patterning layer is greater than about 10:1, since the content of the ultraviolet light absorbing material is relatively small, a sufficient quantity of ultraviolet light cannot be absorbed, and thereby, the pixel shrinkage phenomenon may be caused.
The cathode patterning material may include an organic material. For example, the cathode patterning material may include a polycyclic compound that may optionally include one or more heteroatoms such as nitrogen (N), sulfur (S), oxygen (0), phosphorus (P), and aluminum (Al). The polycyclic compound may be a polycyclic aromatic compound that does not contain a hetero atom, or a polycyclic hetero aromatic compound in which at least one carbon atom is substituted with a hetero atom.
The polycyclic compound may contain at least one fluorine (F) atom. For example, the polycyclic compound may contain 1, 2, 3, 4 or more fluorine atoms. The Polycyclic compound may contain 1 to 3 fluorine atoms.
The ultraviolet light absorbing material may include a material that can absorb ultraviolet light with wavelengths in the range from 200 to 400 nm. For example, the ultraviolet light absorbing material may be at least one of a benzophenone-based compound, a benzotriazole-based compound, a benzoate-based compound, a cyanoacrylate-based compound, a triazine-based compound, an oxanilide-based compound, and a salicylate-based compound.
The benzophenone-based compound may include 2,4-dihydroxybenzophenone, 2-hydroxy-4-methoxybenzophenone, 2-hydroxy-4-octylbenzophenone, 4-dodecyloxy-2-hydroxybenzophenone, 4-benzyloxy-2-hydroxybenzophenone, 2,2′,4,4′-tetrahydroxybenzophenone, 2,2′-dihydroxy 4, 4′-dimethoxybenzophenone, and the like.
The benzotriazole-based compound may include 2-(5-methyl-2-hydroxyphenyl)benzotriazole, 2-[2-hydroxy-3,5-bis(α, α-dimethylbenzyl)phenyl]-2H-benzotria Sol, 2-(3,5-di-t-butyl-2-hydroxyphenyl)benzotriazole, 2-(3-t-butyl-5-methyl2-hydroxyphenyl)-5-chlorobenzotriazole, 2-(3,5-di-t-butyl-2-hydroxyphenyl)-5-chlorobenzotriazole, 2-(3,5-di-t-acyl-2-hydroxyphenyl)benzotriazole, 2-(2′-hydroxy5′-t-octylphenyl)benzotriazole, and the like.
The benzoate-based compound may include 2,4-di-t-butylphenyl-3′, 5′-di-t-butyl-4-hydroxybenzoate, and the like.
The triazine-based compound may include 2-[4-[(2-hydroxy-3-dodecyloxypropyl)oxy]-2-hydroxyphenyl]-4, 6-bis(2,4-dimethylphenyl)1, 3,5-triazine, and the like.
The salicylate-based compound may include phenyl salicylate, 4-t-butylphenyl salicylate, and the like.
For example, the benzophenone-based compound and the benzotriazole-based compound may have a hydroxyl group (—OH). However, a material or compound having a hydroxyl group (—OH) according to embodiments of the present disclosure is not limited to the benzophenone-based compound and the benzotriazole-based compound. For example, the materials used for absorbing ultraviolet light described above may also have a hydroxyl group. As such ultraviolet light absorbing materials are formed of monomolecular substances having a hydroxyl group (—OH), which is a functional group capable of hydrogen bonding, the ultraviolet light absorbing materials can absorb ultraviolet light incident from the outside through an excited-state intramolecular proton transfer (ESIPT) phenomenon.
For example, in the ultraviolet light absorbing materials, atoms having an unshared electron pair, such as an oxygen (O) atom or a nitrogen (N) atom, can be present adjacent to a hydroxyl group (—OH) in a molecule, and hydrogen bonds between the atoms having the unshared electron pair with the hydroxyl group (—OH) can be formed. In this situation, the ultraviolet light absorbing materials in an excited state by absorbing ultraviolet light can be led to phototautomerization in which protons move in excited molecules, and thus, as hydrogen (H) from the hydroxyl group (—OH) is escaped, can become keto-form molecules in a stable state, resulting in heat release occurring. As a result, ultraviolet light incident on the ultraviolet light absorbing materials can be converted into thermal energy and emitted to the outside, thereby, the ultraviolet light can be shielded from penetrating inside of the display panel.
One cathode hole CH illustrated in
Referring to
Referring to
Referring to
Since the second encapsulation layer PCL is implemented using an organic material, the second encapsulation layer PCL can serve as a planarization layer.
In one or more embodiments, a touch sensor may be integrated into the display panel 110 according to aspects of the present disclosure. In these embodiments, the display panel 110 according to aspects of the present disclosure may include a touch sensor layer TSL disposed on the encapsulation layer ENCAP.
Referring to
The sensor buffer layer S-BUF may be disposed on the encapsulation layer ENCAP. The bridge metals BRG may be disposed on the sensor buffer layer S-BUF, and the sensor interlayer insulating layer S-ILD may be disposed on the bridge metals BRG.
The touch sensor metals TSM may be disposed on the sensor interlayer insulating layer S-ILD. One or more of the touch sensor metals TSM may be connected to one or more respective bridge metals BRG among the bridge metals BRG through one or more respective holes formed in the sensor interlayer insulating layer S-ILD.
Referring to
A plurality of touch sensor metals TSM may be configured as one touch electrode (or one touch electrode line). For example, the plurality of touch sensor metals TSM may be arranged in a mesh pattern and therefore electrically connected to one another. One or more of the touch sensor metals TSM and the remaining one or more touch sensor metals TSM may be electrically connected through one or more respective bridge metals BRG, and thereby, be configured as one touch electrode (or one touch electrode line).
The sensor protective layer S-PAC may be disposed such that it covers the touch sensor metals TSM and the bridge metals BRG.
In an embodiment where a touch sensor is integrated into the display panel 110, at least one of the touch sensor metals TSM, or at least a portion of at least one of the touch sensor metals TSM, located on the encapsulation layer ENCAP may extend along an inclined surface formed in an edge of the encapsulation layer ENCAP, and be electrically connected to a pad located in an edge of the display panel 110 that is further away from the inclined surface of the edge of the encapsulation layer ENCAP. The pad may be disposed in the non-display area NDA and may be a metal pattern to which the touch driving circuit 260 is electrically connected.
In one or more embodiments, the display panel 110 according to aspects of the present disclosure may include a bank (e.g., the bank BK) disposed on a first anode electrode (e.g., the first anode electrode AE1) and having a bank hole exposing a portion of the first anode electrode AE1, and an emission layer (e.g., the emission layer EL) disposed on the bank BK and contacting the portion of the first anode electrode AE1 exposed through the bank hole.
The bank hole formed in the bank BK may not overlap a plurality of cathode holes CH. For example, the bank BK may not be depressed or perforated (i.e., remained in a flat state) at places where the plurality of cathode holes CH are present. Thus, at places where the plurality of cathode holes CH are present, the second planarization layer PLN and the first planarization layer PLN1 located under the bank BK may not be depressed or perforated as well (i.e., remained in a flat state).
The flat state of the respective portion of the upper surface of the bank BK located under any one of the plurality of cathode holes CH may mean that one or more insulating layers or one or more metal patterns (e.g., one or more electrode, one or more lines, and/or the like), or the emission layers EL located under any one of the plurality of cathode holes CH have not been damaged by the process of forming the plurality of cathode holes CH in the cathode electrode CE.
A brief description for the process of forming cathode holes CH in the cathode electrode CE is as follows. A specific mask pattern may be deposited at respective locations where the cathode holes CH are to be formed, and then, a cathode electrode material may be deposited thereon. Accordingly, the cathode electrode material may be deposited only in an area where the specific mask pattern is not located, and thereby, the cathode electrode CE including the cathode holes CH can be formed. The specific mask pattern may include, for example, an organic material. The cathode electrode material may include a magnesium-silver (Mg-Ag) alloy.
In one or more embodiments, after the cathode electrode CE having the cathode holes CH is formed, the display panel 110 may be in a situation in which the specific mask pattern is completely removed, partially removed (where a portion of the specific mask pattern remains), or not removed (where all of the specific mask pattern remains without being removed).
In one or more embodiments, the display panel 110 according to aspects of the present disclosure may include the first driving transistor DT1 disposed in the optical bezel area OBA to drive the first light emitting element ED1 disposed in the optical area OA, and the second driving transistor DT2 disposed in the optical bezel area OBA to drive the second light emitting element ED2 disposed in the optical bezel area OBA.
In one or more embodiments, the display panel 110 according to aspects of the present disclosure may further include the first planarization layer PLN1 disposed on the first driving transistor DT1 and the second driving transistor DT2, a first relay electrode (e.g., the first relay electrode RE1) disposed on the first planarization layer PLN1 and electrically connected to the first source electrode S1 of the first driving transistor DT1 through a hole formed in the first planarization layer PLN1, a second relay electrode (e.g., the second relay electrode RE2) disposed on the first planarization layer PLN1 and electrically connected to the second source electrode S2 of the second driving transistor DT2 through another hole formed in the first planarization layer PLN1, and the second planarization layer PLN2 disposed on the first relay electrode RE1 and the second relay electrode RE2.
In one or more embodiments, the display panel 110 according to aspects of the present disclosure may further include an anode extension line (e.g., the anode extension line AEL) interconnecting the first relay electrode RE1 and the first anode electrode AE1, and located on the first planarization layer PLN1.
The second anode electrode AE2 may be electrically connected to the second relay electrode RE2 through a hole formed in the second planarization layer PLN2, and the first anode electrode AE1 may be electrically connected to the anode extension line AEL through another hole formed in the second planarization layer PLN2.
All or a portion of the anode extension line AEL may be disposed in the optical area OA, and the anode extension line AEL may include a transparent material, or be or include a transparent line.
The first pixel circuit SPC1 may include the first driving transistor DT1 for driving the first light emitting element ED1, and the second pixel circuit SPC2 may include the second driving transistor DT2 for driving the second light emitting element ED2.
The first active layer ACT1 of the first driving transistor DT1 may be located in a different layer from the second active layer ACT2 of the second driving transistor DT2.
In one or more embodiments, the display panel 110 according to aspects of the present disclosure may further include the substrate SUB, the first buffer layer BUF1 disposed between the substrate SUB and the first driving transistor DT1, and the second buffer layer BUF2 disposed between the first driving transistor DT1 and the second driving transistors DT2.
The first active layer ACT1 of the first driving transistor DT1 may include a different semiconductor material from the second active layer ACT2 of the second driving transistor DT2.
For example, the second active layer ACT2 of the second driving transistor DT2 may include an oxide semiconductor material. For example, such an oxide semiconductor material may include indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), zinc oxide (ZnO), cadmium oxide (CdO), indium oxide (InO), zinc tin oxide (ZTO), zinc indium tin oxide (ZITO), and/or the like.
For example, the first active layer ACT1 of the first driving transistor DT1 may include a different semiconductor material from the second active layer ACT2 of the second driving transistor DT2.
For example, the first active layer ACT1 of the first driving transistor DT1 may include a silicon-based semiconductor material. For example, the silicon-based semiconductor material may include low-temperature polycrystalline silicon (LTPS) or the like.
In one or more embodiments, the display panel 110 according to aspects of the present disclosure may further include an encapsulation layer (e.g., the encapsulation layer ENCAP) located on the first light emitting element ED1, the second light emitting element ED2, and the third light emitting element ED3, and one or more touch sensor metals TSM located on the encapsulation layer ENCAP.
The touch sensor metals TSM may be disposed in the normal area NA and the optical bezel area OBA. For example, the touch sensor metals TSM may not be disposed in the optical area OA. In another example, the touch sensor metals TSM may be disposed in the optical area OA, the normal area NA and the optical bezel area OBA such that the optical area OA has a lower touch sensor metal density than each of the normal area NA and the optical bezel area OBA.
Referring to
The optical electronic device overlapping the optical area OA may be the first optical electronic device 11 and/or the second optical electronic device 12 discussed above. For example, the optical electronic device may include a camera, an infrared sensor, an ultraviolet sensor, and/or the like. For example, the optical electronic device may be a device capable of receiving visible light and performing a predetermined operation, or a device capable of receiving light (e.g., infrared light, and/or ultraviolet light) different from visible light and performing a predetermined operation.
Referring to
The cross-sectional view of
Referring to
Accordingly, as illustrated in
Referring to
Referring to
Referring to
In the optical area OA, the non-transmission area NTA may represent an area except for the plurality of transmission areas TA.
Referring to
Further, a plurality of pixel circuits SPC for driving the plurality of light emitting elements ED may be disposed in the non-transmission area NTA in the optical area OA. Thus, the plurality of pixel circuits SPC may be disposed in the non-transmission area NTA in the optical area OA. In contrast, in the case of the first type, the plurality of subpixel circuits SPC are not disposed in the optical area OA.
In the case of the second type, the transistors (DT, ST) and the storage capacitors Cst may be disposed in the optical area OA. In the case of the first type, the transistors (DT, ST) and the storage capacitors Cst may not be disposed in the optical area OA.
Referring to
One or more embodiments, referring to
A cathode electrode (e.g., the cathode electrode CE in
Since the optical area OA includes the plurality of transmission areas TA, the optical area OA may have higher transmittance than the normal area NA.
All or a portion of the optical area OA may overlap an optical electronic device.
The optical electronic device overlapping the optical area OA may be the first optical electronic device 11 and/or the second optical electronic device 12 discussed above. For example, the optical electronic device may include a camera, an infrared sensor, an ultraviolet sensor, and/or the like. For example, the optical electronic device may be a device capable of receiving visible light and performing a predetermined operation, or a device capable of receiving light (e.g., infrared light, and/or ultraviolet light) different from visible light and performing a predetermined operation.
Referring to
The non-transmission area NTA may include a plurality of light emitting areas EA.
A respective light emitting element ED may be disposed in each of the plurality of light emitting areas EA.
A plurality of pixel circuits SPC for driving the plurality of light emitting elements ED may be disposed in the non-transmission area NTA.
In the second type of optical area OA, the light emitting elements ED and the pixel circuits SPC may partially overlap each other.
In the case of the second type of optical area OA, data lines (DL1, DL2 and DL3) and gate lines (GL1, GL2, GL3, and GL4) may run across the optical area OA.
In the optical area OA, the data lines (DL1, DL2 and DL3) may be arranged in a row direction (or a column direction) while avoiding one or more transmission areas TA, which correspond to one or more respective cathode holes CH.
In the optical area OA, the gate lines (GL1, GL2, GL3, and GL4) may be arranged in the column direction (or the row direction) while avoiding one or more transmission areas TA, which correspond to one or more respective cathode holes CH.
The data lines (DL1, DL2 and DL3) and the gate lines (GL1, GL2, GL3, and GL4) may be connected to pixel circuits (SPC1, SPC2, and SPC3) disposed in the optical area OA.
For example, four light emitting elements (EDr, EDg1, EDg2, and EDb) may be disposed in a portion of the non-transmission area NTA between four adjacent transmission areas TA. The four light emitting elements (EDr, EDg1, EDg2, and EDb) may include one red light emitting element EDr, two green light emitting elements EDg1 and EDg2, and one blue light emitting element EDb.
For example, a pixel circuit SPC1 for driving the one red light emitting element EDR may be connected to a first data line DL1 and a first gate line GL1. A pixel circuit SPC2 for driving the two green light emitting elements EDg1 and EDg2 may be connected to a second data line DL2, a second gate line GL2, and a third gate line GL3. A pixel circuit SPC3 for driving the one blue light emitting element EDb may be connected to a third data line DL3 and a fourth gate line GL4.
Metal layers and insulating layers in the cross-sectional structure of
Referring to
Referring to
Referring to
A pixel circuit SPC may be configured to drive the first light emitting element ED1, and be disposed to overlap all or a portion of the first light emitting element ED1 in the optical area OA.
Referring to
A pixel circuit SPC may be configured to drive the second light emitting element ED2, and be disposed to overlap all or a portion of the second light emitting element ED2 in the optical area OA.
Referring to
Referring to
The first light emitting element ED1 may be configured (i.e., made up) in an area where a first anode electrode AE1, an emission layer (e.g., the emission layer EL discussed above), and a cathode electrode (e.g., the cathode electrode CE discussed above) overlap one another.
The first source electrode S1 of the first driving transistor DT1 may be connected to the first anode electrode AE1 through a first relay electrode RE1.
The first storage capacitor Cst1 may include a first capacitor electrode PLT1 and a second capacitor electrode PLT2.
The first source electrode S1 of the first driving transistor DT1 may be connected to the second capacitor electrode PLT2 of the first storage capacitor Cst1.
The first gate electrode G1 of the first driving transistor DT1 may be connected to the first capacitor electrode PLT1 of the first storage capacitor Cst1.
The active layer ACT1s of the first scan transistor ST1 may be located on the first buffer layer BUF1 and be located in a lower location than the first active layer ACT1 of the first driving transistor DT1.
A semiconductor material included in the active layer ACT1s of the first scan transistor ST1 may be different from a semiconductor material included in the first active layer ACT1 of the first driving transistor DT1. For example, the semiconductor material included in the first active layer ACT1 of the first driving transistor DT1 may be an oxide semiconductor material, and the semiconductor material included in the active layer ACT1s of the first scan transistor ST1 may be a silicon-based semiconductor material (e.g., a low-temperature polycrystalline silicon (LTPS)).
Referring to
The second light emitting element ED2 may be configured (i.e., made up) in an area where a second anode electrode AE2, the emission layer EL, and the cathode electrode CE overlap one another.
The second source electrode S2 of the second driving transistor DT2 may be connected to the second anode electrode AE2 through a second relay electrode RE2.
The second storage capacitor Cst2 may include a first capacitor electrode PLT1 and a second capacitor electrode PLT2.
The second source electrode S2 of the second driving transistor DT1 may be connected to the second capacitor electrode PLT2 of the second storage capacitor Cst2.
The second gate electrode G2 of the second driving transistor DT2 may be connected to the first capacitor electrode PLT1 of the second storage capacitor Cst2.
An active layer ACT2s of the second scan transistor ST2 may be located on the first buffer layer BUF1 and be located in a lower location than the second active layer ACT2 of the second driving transistor DT2.
A semiconductor material included in the active layer ACT2s of the second scan transistor ST2 may be different from a semiconductor material included in the second active layer ACT2 of the second driving transistor DT2. For example, the semiconductor material included in the second active layer ACT2 of the second driving transistor DT2 may be an oxide semiconductor material, and the semiconductor material included in the active layer ACT2s of the second scan transistor ST2 may be a silicon-based semiconductor material (e.g., a low-temperature polycrystalline silicon (LTPS)).
A plurality of cathode holes CH of the cathode electrode CE may be located to respectively correspond to the transmission area TA of the optical area OA.
A bank hole formed in the bank BK may not overlap any one of the cathode holes CH.
An upper surface of the bank BK located in a lower location than the cathode holes CH may be flat without being depressed or etched. For example, the bank BK may not be depressed or perforated (i.e., remained in the flat state) at places where cathode holes CH are present. Thus, at places where cathode holes CH are present, the second planarization layer PLN2 and the first planarization layer PLN1 located in a lower location than the bank BK may not be depressed or perforated as well (i.e., remained in a flat state).
The flat state of the respective portions of the upper surface of the bank BK located under the cathode holes CH may mean that one or more insulating layers or one or more metal patterns (e.g., one or more electrode, one or more lines, and/or the like), or the emission layer EL located under the cathode electrode CE have not been damaged by the process of forming the cathode holes CH in the cathode electrode CE.
The process of forming the plurality of cathode holes CH in the cathode electrode CE may be the same as the process of forming the plurality of cathode holes CH in the illustration of
Referring to
In a situation where the patterning layer 1100 is deposited on the substrate 1000, an electrode material can be deposited on an area of the substrate where the patterning material is not present.
The electrode material can move toward the substrate 1000 by an evaporator 1120 containing the electrode material. In this situation, a mask 1110 (e.g., an open metal mask OMM) can be disposed in a moving path of the electrode material so that the electrode material can be incident on both the patterning layer 1100 where the patterning material is deposited and the area where the patterning material is not deposited. After the electrode material passes through the mask 1100, the electrode material may not be deposited on the patterning layer 1100 where the patterning material is deposited, but may be deposited in an area except for the patterning layer 1100. As a result, a corresponding electrode layer 1200 can be formed.
Meanwhile, the patterning layer 1100 may be selectively removed from the substrate 1000.
Referring to
Since the portion of the upper surface of the bank BK is formed as the uneven surface EMB, at least one of both surfaces of the composite patterning layer MVL may also be formed as an uneven surface EMB on the bank BK. Therefore, the area of the upper surface of the bank BK can increase due to the shape of the uneven surface EMB, and the area of the composite patterning layer MVL formed on the bank BK can also increase, this leading a surface area for absorbing incident ultraviolet light to increase.
Referring to
The ultraviolet light absorbing layer UVA may be disposed on a bank BK. For example, an emission layer EL may be disposed on the bank BK, and the ultraviolet light absorbing layer UVA may be disposed on the emission layer EL.
An area where the ultraviolet light absorbing layer UVA is disposed may not be limited to an area overlapping the cathode hole CH. For example, the ultraviolet light absorbing layer UVA may be disposed on the entire surface of the emission layer EL. Since the ultraviolet light absorbing layer UVA is formed on the entire surface of the emission layer EL, ultraviolet light incident to other areas except for the cathode hole CH, as well as the cathode hole CH, can be absorbed.
The metal patterning layer MPL may be formed on the ultraviolet light absorbing layer UVA. As the metal patterning layer MPL is formed on the ultraviolet light absorbing layer UVA, a cathode CE may be formed in an area except for the metal patterning layer MPL, and the cathode hole CH may be formed to correspond to the metal patterning layer MPL.
Referring to
In an example where the composite patterning layer MVL includes a stack of a single layer, the process of forming the composite patterning layer MVL may include a process of depositing a mixture of the cathode patterning material and the ultraviolet light absorbing material, and a process of concurrently depositing each of the cathode patterning material and the ultraviolet light absorbing material. However, embodiments of the present disclosure are not limited thereto.
First,
Referring to
A fine metal mask 1010 having openings corresponding to a respective size of each cathode hole CH can be disposed in a moving path of the flux of the mixture. The flux of the mixture can be selectively incident on the surface of a substrate 1000 through the openings of the fine metal mask 1010, and thereby, a composite patterning layer 1300 can be formed. The composite patterning layer 1300 includes recesses 1301 that extends from a surface 1302 of the composite patterning layer 1300 distal from the substrate 1000 toward the substrate 1000.
In a situation where the composite patterning layer 1300 is deposited on the substrate 1000, a cathode electrode material can be deposited on an area of the substrate where the cathode patterning material is not present.
The cathode electrode material can be moved toward the substrate 1000 by the evaporator 1120 containing the cathode electrode material. In this situation, an open metal mask 1110 may be disposed in a moving path of the cathode electrode material. After the cathode electrode material passes through the open metal mask 1110, while not being deposited on the composite patterning layer 1300 where the mixture is deposited, the cathode electrode material can be deposited in an area except for the composite patterning layer 1300, e.g., the recesses 1301, and thereby, a cathode 1200 can be formed.
First,
First, the cathode patterning material and the ultraviolet light absorbing material can be concurrently evaporated or sublimated under vacuum by an evaporator 1020 containing the cathode patterning material and an evaporator 1021 containing the ultraviolet light absorbing material, respectively. In this situation, respective contents of the cathode patterning material and the ultraviolet light absorbing material of the composite patterning layer may be adjusted by adjusting a deposition rate of the cathode patterning material to the ultraviolet light absorbing material to be evaporated (sublimated). For example, the ratio of a cathode patterning material deposition rate to a ultraviolet light absorbing material deposition rate may be adjusted to be 1:1, 2:1, 5:1, or 10:1, and therefore, the ratio of a cathode patterning material content of the composite patterning layer to a ultraviolet light absorbing material content of the composite patterning layer may be adjusted to be 1:1, 2:1, 5:1, or 10:1.
A fine metal mask 1010 having openings corresponding to a respective size of each cathode hole CH can be disposed in moving paths of respective fluxes of the cathode patterning material and the ultraviolet light absorbing material. The fluxes of the cathode patterning material and the ultraviolet light absorbing material can be selectively incident on the surface of a substrate 1000 through the openings of the fine metal mask 1010, and thereby, a composite patterning layer 1300 can be formed.
In a situation where the composite patterning layer 1300 is deposited on the substrate 1000, a cathode electrode material can be deposited on an area of the substrate where the cathode patterning material is not present.
The cathode electrode material can be moved toward the substrate 1000 by the evaporator 1120 containing the cathode electrode material. In this situation, an open metal mask 1110 can be disposed in a moving path of the cathode electrode material. After the cathode electrode material passes through the open metal mask 1110, while not being deposited on the composite patterning layer 1300 where the cathode patterning material and the ultraviolet light absorbing material are deposited, the cathode electrode material can be deposited in an area except for the composite patterning layer 1300, and thereby, a cathode 1200 can be formed.
Referring to
First, an ultraviolet light absorbing material can be evaporated or sublimated under vacuum by an evaporator 1021 containing the ultraviolet light absorbing material. In this situation, an open metal mask 1011 can be disposed in a moving path of the ultraviolet light absorbing material. The ultraviolet light absorbing material can pass through the open metal mask 1011, and be deposited on a substrate 1000 to form an ultraviolet light absorbing layer 1400.
A fine metal mask 1010 having openings corresponding to a respective size of each cathode hole CH can be disposed in a moving path of a cathode patterning material. The cathode patterning material can be selectively incident on the surface of the ultraviolet light absorbing layer 1400 deposited on the substrate 1000 through the openings of the fine metal mask 1010, and thereby, a metal patterning layer 1100 can be formed. The metal patterning layer 1100 includes recesses 1101 that extends from a surface 1102 of the metal patterning layer 1100 distal from the substrate 1000 toward ultraviolet light absorbing layer 1400.
A cathode electrode material can be moved toward the substrate 1000 by an evaporator 1120 containing the cathode electrode material. In this situation, an open metal mask 1110 can be disposed in a moving path of the cathode electrode material. After the cathode electrode material passes through the open metal mask 1110, while not being deposited on the metal patterning layer 1100 where the cathode patterning material is deposited, the cathode electrode material can be deposited in an area except for the metal patterning layer 1100, e.g., the recesses 1101, and thereby, a cathode 1200 can be formed.
Meanwhile, the open metal mask 1011 used to form the ultraviolet light absorbing layer 1400 and the open metal mask 1011 used to form the cathode may be the same mask or may be different masks.
Referring to
Referring to
The cathode hole CH may be located on the bank BK.
The bank BK may be located under the cathode hole CH and may include an open area OP1 exposing a portion of the second planarization layer PLN2.
A composite patterning layer MVL may be disposed in the open area OP1 of the bank BK. In this implementation, the composite patterning layer MVL may be disposed on the second planarization layer PLN2 in the open area OP1 of the bank BK.
Referring to
Referring to
Referring to
The cathode hole CH may be located on the bank BK.
The bank BK may be located under the cathode hole CH and may include an open area OP1 exposing a portion of the second planarization layer PLN2.
A composite patterning layer MVL may be disposed in the open area OP1 of the bank BK.
The composite patterning layer MVL may include a stack of two layers including an ultraviolet light absorbing layer UVA including an ultraviolet light absorbing material and a metal patterning layer MPL located on the ultraviolet light absorbing layer UVA and including a cathode patterning material.
The ultraviolet light absorbing layer UVA may be disposed in the open area OP1 of the bank BK. For example, an emission layer EL may be disposed in the open area OP1 of the bank BK and on the bank BK, and the ultraviolet light absorbing layer UVA may be disposed on the emission layer EL.
An area where the ultraviolet light absorbing layer UVA is disposed may not be limited to an area overlapping the cathode hole CH. For example, the ultraviolet light absorbing layer UVA may be disposed on the entire surface of the emission layer EL. Since the ultraviolet light absorbing layer UVA is formed on the entire surface of the emission layer EL, ultraviolet light incident to other areas except for the cathode hole CH, as well as the cathode hole CH, can be absorbed.
The metal patterning layer MPL may be disposed on the ultraviolet light absorbing layer UVA in the open area OP1 of the bank BK. In this implementation, the metal patterning layer MPL may be disposed on the second planarization layer PLN2 in the open area OP1 of the bank BK.
Referring to
Referring to
Referring to
The cathode hole CH may be located in a portion of the bank BK, and/or be located on the bank BK.
The bank BK may be located under the cathode hole CH and may include an open area OP1 exposing a portion of the second planarization layer PLN2.
The planarization layer PLN may be located under the open area OP1 of the bank BK and include an open area OP2 of the second planarization layer PLN2 exposing a portion of the first planarization layer PLN1.
A composite patterning layer MVL may be disposed in the open area OP2 of the second planarization layer PLN2. The composite patterning layer MVL may be in contact with a side surface of the cathode hole CH and may be also in contact with the light emitting layer EL.
In this implementation, the composite patterning layer MVL may be disposed on the first planarization layer PLN1 in the open area OP2 of the second planarization layer PLN2.
Referring to
Referring to
Referring to
The cathode hole CH may be located in a portion of the bank BK.
The bank BK may be located under the cathode hole CH and may include an open area OP1 exposing a portion of the second planarization layer PLN2.
The planarization layer PLN may be located under the open area OP1 of the bank BK and include an open area OP2 of the second planarization layer PLN2 exposing a portion of the first planarization layer PLN1.
A composite patterning layer MVL may be disposed in the open area OP2 of the second planarization layer PLN2.
The composite patterning layer MVL may include a stack of two layers including an ultraviolet light absorbing layer UVA including an ultraviolet light absorbing material and a metal patterning layer MPL located on the ultraviolet light absorbing layer UVA and including a cathode patterning material.
The ultraviolet light absorbing layer UVA may be disposed in the open area OP2 of the second planarization layer PLN2. For example, an emission layer EL may be formed in the open area OP2 of the second planarization layer PLN2, on the second planarization layer PLN2, on one or more side surfaces of the bank BK, and on the bank BK, and the ultraviolet light absorbing layer UVA may be formed on the emission layer EL.
An area where the ultraviolet light absorbing layer UVA is disposed may not be limited to an area overlapping the cathode hole CH. For example, the ultraviolet light absorbing layer UVA may be disposed on the entire surface of the emission layer EL. Since the ultraviolet light absorbing layer UVA is formed on the entire surface of the emission layer EL, ultraviolet light incident to other areas except for the cathode hole CH, as well as the cathode hole CH, can be absorbed.
In this implementation, the metal patterning layer MPL may be disposed on the first planarization layer PLN1 in the open area OP2 of the second planarization layer PLN2.
Referring to
The embodiments described above will be briefly described as follows.
According to aspects of the present disclosure, a display device can be provided that includes an optical area included in a display area in which images can be displayed and allowing light to be transmitted, a normal area included in the display area and located outside of the optical area, a cathode electrode commonly disposed in the optical area and the normal area and including a plurality of cathode holes in the optical area, and a composite patterning layer corresponding to a corresponding one of the plurality of cathode holes and including a cathode patterning material and an ultraviolet light absorbing material.
The weight ratio of the cathode patterning material to the ultraviolet light absorbing material included in the composite patterning layer may be in a range from 1:1 to 10:1.
The composite patterning layer may include an ultraviolet light absorbing layer including the ultraviolet light absorbing material, and a metal patterning layer located on the ultraviolet light absorbing layer and including the cathode patterning material.
The display device may further include an anode electrode, a bank disposed on the anode electrode and including a bank hole exposing a portion of the anode electrode, and an emission layer disposed on the bank and contacting the portion of the anode electrode exposed through the bank hole. A cathode electrode may be located on the emission layer, and the plurality of cathode holes may be located on the bank.
A portion of the upper surface of the bank located under the corresponding one of the plurality of cathode holes may be formed as an uneven surface, and the composite patterning layer may be disposed on the uneven surface.
The display device may further include a planarization layer disposed under the bank. The bank may include an open area located under the corresponding one of the plurality of cathode holes and exposing a portion of the planarization layer, and the composite patterning layer may be disposed in the open area of the bank.
The composite patterning layer may include an ultraviolet light absorbing layer including the ultraviolet light absorbing material and a metal patterning layer located on the ultraviolet light absorbing layer and including the cathode patterning material in the open area of the bank.
The planarization layer may include a first planarization layer and a second planarization layer disposed on the first planarization layer. The second planarization layer may include an open area located under the open area of the bank and exposing a portion of the first planarization layer. The composite patterning layer may be disposed in the open area of the second planarization layer.
The composite patterning layer may include an ultraviolet light absorbing layer including the ultraviolet light absorbing material, and a metal patterning layer located on the ultraviolet light absorbing layer and including the cathode patterning material in the open area of the second planarization layer.
The display device may further include an encapsulation layer on the cathode electrode and touch sensor metals on the encapsulation layer. At least one of the touch sensor metals may be disposed in the normal area. The touch sensor metals may not be disposed in the optical area, or the optical area may include touch sensor metals at a lower density than the normal area.
The display device may further include an optical bezel area between the optical area and the normal area. One or more light emitting elements may be disposed in the optical area, and one or more pixel circuits for driving the one or more light emitting elements disposed in the optical area may be disposed in the optical bezel area. The pixel circuit may include at least one transistor and at least one storage capacitor. The plurality of cathode holes may overlap an area of the optical area where the light emitting elements are not disposed.
The optical area of the display device may include a plurality of transmission areas and a non-transmission area. A plurality of light emitting elements and a plurality of pixel circuits may be disposed in the non-transmission area, each of the plurality of pixel circuits may include least one transistor and at least one storage capacitor. The plurality of cathode holes may overlap the plurality of transmission areas.
The display device may further include an optical electronic device overlapping the optical area and can obtain an image using light passing through the optical area.
According to aspects of the present disclosure, a display panel can be provided that includes a plurality of transmission areas included in a display area in which images can be displayed and allowing light to be transmitted, a cathode electrode including a plurality of cathode holes respectively corresponding to the plurality of transmission areas, and a composite patterning layer corresponding to a corresponding one of the plurality of cathode holes and including a cathode patterning material and an ultraviolet light absorbing material.
The weight ratio of the cathode patterning material to the ultraviolet light absorbing material included in the composite patterning layer may be in a range from 1:1 to 10:1.
The composite patterning layer may include an ultraviolet light absorbing layer including the ultraviolet light absorbing material and a metal patterning layer located on the ultraviolet light absorbing layer and including the cathode patterning material.
The display panel may further include an anode electrode, a bank disposed on the anode electrode and including a bank hole exposing a portion of the anode electrode, and an emission layer disposed on the bank and contacting the portion of the anode electrode exposed through the bank hole. A cathode electrode may be located on the emission layer, and the plurality of cathode holes may be located on the bank.
A portion of the upper surface of the bank located under the corresponding one of the plurality of cathode holes may be formed as an uneven surface, and the composite patterning layer may be disposed on the uneven surface.
According to aspects of the present disclosure, a display device can be provided that includes an anode electrode, a bank structure on the anode electrode, a bank hole in the bank structure that exposes a portion of the anode electrode, a light emitting layer on the bank structure, the light emitting layer overlapping the anode electrode in the bank hole, a cathode electrode on the light emitting layer, a cathode hole in the cathode electrode, the cathode hole overlying the bank and being offset from the bank hole and a composite patterning layer in cathode hole, the composite patterning layer including a metal patterning layer and an ultraviolet light absorbing layer.
The composite patterning layer can be in contact with the light emitting layer and the cathode electrode.
According to aspects of the present disclosure, a method can be provided that includes forming an anode electrode over a substrate, forming a bank structure on the anode electrode, forming a bank hole in the bank structure that exposes a portion of the anode electrode, forming a light emitting layer on the bank structure, the light emitting layer overlapping the anode electrode in the bank hole, forming a composite patterning layer on a substrate using an evaporator and a mask, the composite patterning layer including a cathode patterning material and an ultraviolet light absorbing material, and including recesses that each extend away from the composite patterning layer and forming a cathode electrode by depositing cathode electrode material in the recesses.
The forming the composite patterning layer can include forming a layer of the ultraviolet light absorbing material on the substrate using an open metal mask, forming a layer of the cathode patterning material on the layer of the ultraviolet light absorbing material using the fine metal mask, wherein the recesses each can extend from a surface of the layer of the cathode patterning material distal to the substrate toward the layer of the ultraviolet light absorbing material.
The mask ican be a fine metal mask.
The step of forming a cathode electrode by depositing cathode electrode material in the recesses can include using an open metal mask.
According to the embodiments described herein, the display panel and the display device may be provided that include a light transmission structure for enabling one or more optical electronic devices to normally receive light (e.g., visible light, infrared light, ultraviolet light, or the like) while not being exposed in a front surface of the display device.
According to the embodiments described herein, the display panel and the display device may be provided that are capable of preventing a pixel shrinkage phenomenon by shielding incident ultraviolet rays from being transmitted inside of the display panel due to a structure in which one or more optical electronic devices are located under, or in a lower portion of, a display area of the display panel.
According to the embodiments described herein, the display panel and the display device may be provided that are capable of enabling a camera, which is an optical electronic device under, or in a lower portion of, a display area of the display panel, to acquire high quality images.
Additional features and aspects will be set forth in part in the description which follows and in part will become apparent from the description or may be learned by practice of the inventive concepts provided herein. Other features and aspects of the inventive concepts may be realized and attained by the structure particularly pointed out in, or derivable from, the written description, the claims hereof, and the appended drawings. Other systems, methods, features and advantages will be, or will become, apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the present disclosure, and be protected by the appended claims. Nothing in this section should be taken as a limitation on those claims. It is to be understood that both the foregoing general description and the following detailed description of the present disclosure are examples and explanatory and are intended to provide further explanation of the inventive concepts as claimed.
The above description has been presented to enable any person skilled in the art to make, use and practice the technical features of the present disclosure, and has been provided in the context of a particular application and its requirements as examples. Various modifications, additions and substitutions to the described embodiments will be readily apparent to those skilled in the art, and the principles described herein may be applied to other embodiments and applications without departing from the scope of the present disclosure. The above description and the accompanying drawings provide examples of the technical features of the present disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical features of the present disclosure.
The various embodiments described above can be combined to provide further embodiments. All of the U.S. patents , U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications and non-patent publications referred to in this specification and/or listed in the Application Data Sheet are incorporated herein by reference, in their entirety. Aspects of the embodiments can be modified, if necessary to employ concepts of the various patents, applications and publications to provide yet further embodiments.
These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0009714 | Jan 2023 | KR | national |
