Patent Grant
11557251
The disclosure relates to display devices, more specifically to a current-driven display device, such as an organic EL (electro-luminescent) display device, which is provided with display elements to be driven by currents, and also relates to a method for driving the same.
In recent years, organic EL display devices provided with pixel circuits which include organic EL elements (also referred to as organic light-emitting diodes (OLEDs)) have been put into practical use. In addition to the organic EL elements, the pixel circuits in the organic EL display devices include drive transistors, write control transistors, holding capacitors, etc. As the drive transistors and the write control transistors, thin-film transistors are used, and the drive transistors are connected at gate terminals, which serve as control terminals, to the holding capacitors, to which drive circuits supply data voltages via data signal lines; the data voltages are voltages corresponding to video signals that represent images to be displayed (more specifically, voltages that specify gradation values for pixels to be formed by the pixel circuits). The organic EL elements are self-luminous display elements which emit light with intensities corresponding to currents flowing therethrough. The drive transistors are provided in series with the organic EL elements and configured to control the currents flowing through the organic EL elements in accordance with voltages being held by the holding capacitors.
On the other hand, there are known low-power display devices in which pause drive (also called intermittent drive or low-frequency drive) is performed. Pause drive is a drive method using a drive period (refresh period) and a pause period (non-refresh period) when the same image is continuously displayed, and the drive period and the pause period are set such that a drive circuit operates during the drive period but stops operating during the pause period. Pause drive can be applied when transistors in pixel circuits offer good off-state leakage characteristics (i.e., off-state leakage current is low). Such a display device which performs pause drive is described in, for example, Patent Document 1.
Patent Document 1: JP 2004-78124 A
Patent Document 2: JP 2017-83813 A
Patent Document 3: JP 2013-3569 A
The organic EL elements and the drive transistors are susceptible to variations and shifts in characteristics. Accordingly, in order for the organic EL display devices to achieve high-quality image display, it is necessary to compensate for such variations and shifts in element characteristics. In an organic EL display device in which element characteristics are compensated for within pixel circuits for such a purpose, for example, the pixel circuits are configured such that voltages on gate terminals of drive transistors, i.e., voltages that are being held by holding capacitors, are initialized to a predetermined level, and thereafter the holding capacitors are charged with data voltages via drive transistors in diode connection. The pixel circuit thus configured is provided with an initialization transistor for initializing the voltage that is being held by the holding capacitor, which is connected at a terminal to an initialization voltage supply line via the initialization transistor (the terminal also being connected to the gate terminal of the drive transistor).
In the case of a display device provided with pixel circuits as described above, when pause drive as described earlier is performed, the luminance of the organic EL element is decreased or increased during the pause period and returns to the original value upon each start of the drive period. In pause drive, the pause period lasts much longer than a normal frame period ( 1/60 of a second), and essentially, when compared to in normal drive, the drive frequency of the display device is significantly reduced (e.g., to 10 Hz or less). Once the drive frequency is significantly reduced due to pause drive, as described above, the luminance of the organic EL element changes due to repetitive switching between the pause period and the drive period, and such luminance changes might be perceived as flickering.
Therefore, it is desired to enable a current-driven display device to provide satisfactory display without flickering even when pause drive is performed.
Several embodiments of the disclosure provide a display device having a plurality of data signal lines, a plurality of scanning signal lines crossing the data signal lines, and a plurality of pixel circuits arranged in a matrix along the data signal lines and the scanning signal lines, the device including:
first and second power supply lines;
a data signal line drive circuit configured to drive the data signal lines;
a scanning signal line drive circuit configured to selectively drive the scanning signal lines; and
a threshold control circuit provided outside the pixel circuits or inside each of the pixel circuits, wherein,
each pixel circuit corresponds to one of the scanning signal lines and one of the data signal lines,
each pixel circuit includes a current-driven display element, a holding capacitor, and a drive transistor,
the drive transistor includes a main control terminal for controlling a current flowing through the drive transistor and a threshold control terminal for controlling a threshold of the drive transistor,
the main control terminal of the drive transistor is connected to the first power supply line via the holding capacitor,
each pixel circuit is configured such that:
for each pixel circuit, the threshold control circuit provides the threshold control terminal with a threshold control voltage during the emission period for the display element, the threshold control voltage causing the threshold of the drive transistor to change so as to compensate for a change of the voltage being held by the holding capacitor due to a leakage current within the pixel circuit.
Several other embodiments of the disclosure provide a method for driving a display device having a plurality of data signal lines, a plurality of scanning signal lines crossing the data signal lines, first and second power supply lines, and a plurality of pixel circuits arranged in a matrix along the data signal lines and the scanning signal lines, the method including:
a data signal line driving step of driving the data signal lines;
a scanning signal line driving step of selectively driving the scanning signal lines; and
a threshold control step of controlling a threshold of drive transistors included in the pixel circuits, wherein,
each pixel circuit corresponds to one of the scanning signal lines and one of the data signal lines,
each pixel circuit includes a current-driven display element, a holding capacitor, and the drive transistor,
the drive transistor includes a main control terminal for controlling a current flowing through the drive transistor and a threshold control terminal for controlling the threshold of the drive transistor,
the main control terminal of the drive transistor is connected to the first power supply line via the holding capacitor,
each pixel circuit is configured such that:
in the threshold control step, for each pixel circuit, the threshold control terminal is provided with a threshold control voltage during the emission period for the display element, the threshold control voltage causing the threshold of the drive transistor to change so as to compensate for a change of the voltage being held by the holding capacitor due to a leakage current within the pixel circuit.
In the above embodiments of the disclosure, for each pixel circuit of the display device, after a data voltage is written to the holding capacitor in the pixel circuit upon selection on a scanning signal line corresponding to the pixel circuit, even if the voltage that is being held by the holding capacitor changes due to a leakage current within the pixel circuit during the emission period, the threshold control voltage is provided to the threshold control terminal so as to change the threshold of the drive transistor and thereby compensate for the change of the voltage that is being held by the holding capacitor, i.e., a voltage change at the main control terminal of the drive transistor. As a result, the drive current can be inhibited from changing due to the change of the voltage that is being held by the holding capacitor. Thus, it is possible to prevent the occurrence of flickering due to the luminance of the display element changing in the refresh cycle. Moreover, flickering can be prevented even when the refresh cycle lasts long, as in the case of pause drive, and therefore the above embodiments in combination with pause drive makes it possible to display a satisfactory image without flickering being perceived while reducing power consumption.
Hereinafter, embodiments will be described with reference to the accompanying drawings. It should be noted that in each transistor to be mentioned below, a gate terminal thereof serves as a control terminal, and drain and source terminals thereof serve as first and second conductive terminals, respectively, or vice versa. Moreover, in the following embodiments, all transistors will be described as P-channel transistors, but the disclosure is not limited to this. Further, in the following embodiments, the transistors are, for example, thin-film transistors, but the disclosure is not limited to this. Still further, unless otherwise specified, the term “connection” as used herein is intended to mean “electrical connection” regardless of whether the connection is made directly or indirectly via another element without departing from the scope of the disclosure.
<1.1 Overall Configuration>
As shown in
The display portion 11 is provided with m (where m is an integer of 2 or more) data signal lines D1 to Dm and n+1 (where n is an integer of 2 or more) scanning signal lines G0 to Gn crossing the data signal lines, and also includes n emission control lines (emission lines) E1 to En provided along the n respective scanning signal lines G1 to Gn. Moreover, the display portion 11 is provided with m×n pixel circuits 15 arranged in a matrix along the m data signal lines D1 to Dm and the n scanning signal lines G1 to Gn, and each pixel circuit 15 corresponds to one of the m data signal lines D1 to Dm and one of the n scanning signal lines G1 to Gn (to distinguish each pixel circuit 15 from the others, the pixel circuit that corresponds to the i'th scanning signal line Gi and the j'th data signal line Dj will also be referred to below as the “i'th-row, j'th-column pixel circuit” and denoted by the symbol “Pix(i,j)”). In the present embodiment, in addition to the above, the display portion 11 also includes n threshold control lines TC1 to TCn provided along the n respective scanning signal lines G1 to Gn. The n emission control lines E1 to En correspond to the n respective scanning signal lines G1 to Gn, and the n threshold control lines TC1 to TCn also correspond to the n respective scanning signal lines G1 to Gn. Accordingly, each pixel circuit 15 also corresponds to one of the n emission control lines E1 to En, and one of the n threshold control lines TC1 to TCn.
Moreover, the display portion 11 includes unillustrated power supply lines shared among the pixel circuits 15. More specifically, there is a power supply line for supplying a high-level power supply voltage ELVDD to drive organic EL elements to be described later (this power supply line will be referred to below as the “high-level power supply line” and denoted by the same symbol as the high-level power supply voltage, i.e., “ELVDD”), and there is also a power supply line for supplying a low-level power supply voltage ELVSS to drive the organic EL elements (this power supply line will be referred to below as the “low-level power supply line” and denoted by the same symbol as the low-level power supply voltage, i.e., “ELVSS”). More specifically, the low-level power supply line ELVSS acts as a common cathode for the pixel circuits 15. Further, the display portion 11 includes an unillustrated initialization voltage supply line provided for supplying an initialization voltage Vini to be used for a reset operation (also referred to as an “initialization operation”) for initializing each pixel circuit 15 (this line will be denoted by the same symbol as the initialization voltage, i.e., “Vini”). The high-level power supply voltage ELVDD, the low-level power supply voltage ELVSS, and the initialization voltage Vini are supplied by the power supply circuit 50.
The display control circuit 20 receives an input signal Sin, which includes image information representing an image to be displayed and timing control information for image display, from outside the display device 10, generates a data control signal Scd and a scanning control signal Scs on the basis of the input signal Sin, and outputs the data control signal Scd to the data-side drive circuit (data signal line drive circuit) 30 and the scanning control signal Scs to the scanning-side drive circuit (scanning signal line drive circuit/emission control circuit) 40. Moreover, the display control circuit 20 includes a threshold control circuit 22 for generating and applying threshold control signals TC(1) to TC(n) to the threshold control lines TC1 to TCn, respectively, in the display portion 11 on the basis of the input signal Sin. The threshold control signals TC(1) to TC(n) will be described in detail later.
The data-side drive circuit 30 drives the data signal lines D1 to Dm in accordance with the data control signal Scd from the display control circuit 20. More specifically, in accordance with the data control signal Scd, the data-side drive circuit 30 outputs m data signals D(1) to D(m), which represent the image to be displayed, in parallel to the respective data signal lines D1 to Dm.
The scanning-side drive circuit 40 functions as a scanning signal line drive circuit for driving the scanning signal lines G0 to Gn and also as an emission control circuit for driving the emission control lines E1 to En, in accordance with the scanning control signal Scs from the display control circuit 20.
More specifically, in accordance with the scanning control signal Scs, the scanning-side drive circuit 40 serving as the scanning signal line drive circuit sequentially selects each of the scanning signal lines G0 to Gn for a predetermined time period, which corresponds to one horizontal period, during each frame period, and applies an active signal (low-level voltage) to the scanning signal line Gk that is being selected and inactive signals (high-level voltages) to the scanning signal lines that are not being selected. As a result, m pixel circuits Pix(k,1) to Pix(k,m) corresponding to the scanning signal line Gk that is being selected (where 1≤k≤n) are collectively selected. Consequently, during the period for which the scanning signal line Gk is being selected (referred to below as the “k'th scanning selection period”), voltages of the m data signals D(1) to D(m) applied to the data signal lines D1 to Dm by the data-side drive circuit 30 (these voltages will also be simply referred to below as the “data voltages” without distinction) are written to the respective pixel circuits Pix(k,1) to Pix(k,m) as pixel data.
Furthermore, in accordance with the scanning control signal Scs, the scanning-side drive circuit 40 serving as the emission control circuit applies an emission control signal (high-level voltage) that designates “non-emission” to the i'th emission control line Ei during the i'th horizontal period and an emission control signal (low-level voltage) that designates “emission” to the i'th emission control line Ei during other periods (see
<1.2 Overall Operation>
Next, the overall operation of the display device 10 according to the present embodiment will be described with reference to
The externally supplied input signal Sin includes an operation mode signal Sm designating the operation mode, either the normal or pause drive mode as described above, in which the display portion 11 is driven. The operation mode signal Sm is provided to the scanning-side drive circuit 40 as a portion of the scanning control signal Scs and also to the data-side drive circuit 30 as a portion of the data control signal Scd. The scanning-side drive circuit 40 drives the scanning signal lines G0 to Gn and the emission control lines E1 to En in accordance with the operation mode designated by the operation mode signal Sm, and the data-side drive circuit 30 drives the data signal lines D1 to Dn in accordance with the operation mode designated by the operation mode signal Sm. Moreover, the display control circuit 20 (i.e., the threshold control circuit 22 therein) drives the threshold control lines TC1 to TCn in accordance with the operation mode designated by the operation mode signal Sm.
In the present embodiment, for each pixel circuit Pix(i,j), the emission control line Ei is driven (where i=1 to N) such that a data writing operation is performed when the scanning signal line Gi corresponding to the pixel circuit Pix(i,j) is being selected, a reset operation is performed when the scanning signal line Gi−1 immediately preceding the scanning signal line Gi is being selected, and the pixel circuit Pix(i,j) is not lit up during periods in which the data writing operation or the reset operation is performed on the pixel circuit Pix(i,j). Specifically, during the RF period, each of the emission control lines E1 to En is sequentially activated for two horizontal periods in synchronization with the driving of the scanning signal lines G0 to Gn, as shown in
Furthermore, in the normal drive mode, the voltage on each threshold control line TCi is maintained at a predetermined initial threshold control voltage VtcI, as shown in
On the other hand, in the pause drive mode, the voltage on each threshold control line TCi is gradually increased over time during the NRF period (non-refresh period) and then decreased to the initial threshold control voltage VtcI during the following RF period (refresh period), as shown in
<1.3 Configuration of the Pixel Circuit>
Next, the configuration of the pixel circuit 15 in the present embodiment will be described with reference to
The pixel circuit 15 is connected to a scanning signal line Gi corresponding thereto (also referred to below as a “corresponding scanning signal line” in descriptions focusing on the pixel circuit), a scanning signal line Gi−1 immediately preceding the corresponding scanning signal line Gi (this scanning signal line immediately precedes in order of scanning among the scanning signal lines G1 to Gn and will also be referred to below as the “preceding scanning signal line” in descriptions focusing on the pixel circuit), an emission control line Ei corresponding to the pixel circuit (also referred to below as a “corresponding emission control line” in descriptions focusing on the pixel circuit), a threshold control line TCi corresponding to the pixel circuit (also referred to below as a “corresponding threshold control line” in descriptions focusing on the pixel circuit), a data signal line Dj corresponding to the pixel circuit (also referred to below as a “corresponding data signal line” in descriptions focusing on the pixel circuit), an initialization voltage supply line Vini, a high-level power supply line ELVDD, and a low-level power supply line ELVSS.
In the pixel circuit 15, the drive transistor T1 is connected at a source terminal to the corresponding data signal line Dj via the write control transistor T2 and also to the high-level power supply line ELVDD via the first emission control transistor T5, as shown in
As described above, the drive transistor T1 includes the top gate electrode TG and the bottom gate electrode BG, the top gate electrode TG is positioned opposite to one surface (in the figure, the top surface) of the channel region (intrinsic semiconductor layer) 122 with the gate insulating film TGI positioned therebetween, and the bottom gate electrode BG is positioned opposite to the other surface of the channel region 122 with the gate insulating film BGI positioned therebetween (see
The drive transistor T1 is operated in the saturation region, and the organic EL element OL has a drive current I1, as given by equation (1) below, flowing therethrough during the emission period. Equation (1) includes a gain β of the drive transistor T1, which is given by equation (2) below.
I1=(β/2)(|Vgs|−|Vth|)2
=(β/2)(|Vg−ELVDD|−|Vth|)2 (1)
β=μ×(W/L)×Cox (2)
In equations (1) and (2), Vgs, Vth, μ, W, L, and Cox respectively represent a gate-source voltage, a threshold, a mobility, a gate width, a gate length, and a gate insulating film capacitance per unit area of the drive transistor T1.
<1.4 Operation of the Pixel Circuit>
Next, the operation of the pixel circuit 15 in the present embodiment will be described with reference to
For the i'th-row, j'th-column pixel circuit Pix(i,j), once the voltage on the emission control line Ei is changed from L to H level at time t1, as shown in
At time t2, the voltage on the preceding scanning signal line Gi−1 is changed from H to L level, with the result that the preceding scanning signal line Gi−1 is selected. Accordingly, the first initialization transistor T4 transitions to an ON state. Consequently, the voltage on the main gate terminal of the drive transistor T1, i.e., the gate voltage Vg, is initialized to the initialization voltage Vini. The initialization voltage Vini is a voltage large enough to maintain the drive transistor T1 in an ON state while the data voltage is being written to the pixel circuit Pix(i,j). Moreover, once the preceding scanning signal line Gi−1 is selected at time t2, the second initialization transistor T7 also transitions to an ON state. As a result, charge stored on parasitic capacitance of the organic EL element OL is released, so that the anode voltage Va of the organic EL element is initialized to the initialization voltage Vini (see
The period from time t2 to time t3 corresponds to a reset period for the i'th row pixel circuits Pix(i,1) to Pix(i,m), and in the pixel circuit Pix(i,j), the first initialization transistor T4 is in the ON state during the reset period, as described earlier. (A) of
At time t3, the voltage on the preceding scanning signal line Gi−1 is changed to H level, with the result that the preceding scanning signal line Gi−1 is deselected. Accordingly, the first initialization transistor T4 transitions to an OFF state. During the period from time t3 to the start of the i'th scanning selection period at time t4, the data-side drive circuit 30 starts applying a data signal D(j) to the data signal line Dj as a data voltage for the i'th-row, j'th-column pixel, and the data signal D(j) continues to be applied at least until the end of the i'th scanning selection period at time t5.
At time t4, the voltage on the corresponding scanning signal line Gi is changed from H to L level, as shown in
The period from time t4 to time t5 corresponds to the data write period for the i'th-row pixel circuits Pix(i,1) to Pix(i,m), and during the data write period, the write control transistor T2 and the threshold compensation transistor T3 are in the ON state, as described earlier. (B) of
Vg(i,j)=Vdata−|Vth| (5)
Specifically, during the data write period, the data voltage that has been subjected to threshold compensation is written to the holding capacitor Cst, with the result that the gate voltage Vg(i,j) takes a value as given by equation (5).
Thereafter, at time t6, the voltage on the emission control line Ei is changed to L level. Correspondingly, the first and second emission control transistors T5 and T6 transition to the ON state. The emission period starts and continues from time t6, and during the emission period, in the pixel circuit Pix(i,j), the first and second emission control transistors T5 and T6 are in the ON state, the write control transistor T2, the threshold compensation transistor T3, the first initialization transistor T4, and the second initialization transistor T7 are in the OFF state, as described earlier. (C) of
I1=(β/2)(ELVDD−Vg−|Vth|)2
=(β/2)(ELVDD−Vdata)2 (6)
Accordingly, after time t6, the drive current I1 corresponding to the data voltage Vdata, which is the voltage on the corresponding data signal line Dj during the i'th scanning selection period, flows through the organic EL element OL, so that the organic EL element OL emits light with an intensity corresponding to the data voltage Vdata, regardless of the threshold Vth of the drive transistor T1.
In the case of display devices which use pixel circuits configured such that data voltages are written to holding capacitors via diode-connected drive transistors after gate voltages of the drive transistors are initialized, as in the present embodiment, each pixel circuit is controlled such that the organic EL element emits no light not only during the data write period for the pixel circuit (the i'th scanning selection period shown in
<1.5 Configuration and Operation for Threshold Control>
In the present embodiment, in the pause drive mode, the threshold Vth of the drive transistor T1 in each pixel circuit Pix(i,j) is controlled by the voltage on the threshold control line TCi, i.e., the voltage Vtc(i) of the threshold control signal TC(i) (referred to below as the “threshold control voltage”), which is provided to the threshold control terminal (top gate electrode) TG of the drive transistor T1, as described above (see
In the pause drive mode, one long NRF period occurs between two adjacent RF periods, as shown in
On the other hand, in the present embodiment, for each pixel circuit Pix(i,j), the threshold control line TCi is driven such that the voltage Vtc(i), which is provided to the threshold control terminal TG of the drive transistor T1 in the pixel circuit Pix(i,j), changes as shown in
Here, since the drive transistor T1 is of a P-channel type, the positively higher the voltage Vtc(i) provided to the threshold control terminal TG becomes, the larger the absolute value |Vth| of the threshold of the drive transistor T1 becomes (i.e., less current flows). As can be appreciated from equation (1) described earlier, the increase in the absolute value |Vth| of the threshold causes the drive transistor T1 to decrease the drive current I1 of the organic EL element OL and thereby decrease the luminance of the organic EL element OL. Accordingly, by appropriately setting the rate of change in the threshold control voltage Vtc(i) during the emission period in accordance with the characteristics of the drive transistor T1, it is rendered possible to reduce the change in the luminance L(i,j) of the organic EL element OL in the pixel circuit Pix(i,j), as indicated by the solid line in
Described below is a specific method for setting the threshold control voltage Vtc(i) to inhibit the occurrence of flickering as described above.
The drive current I1, which flows from the drive transistor T1 to the organic EL element OL during the emission period, is given by equation (1) described earlier. Here, for the convenience of description, assuming that Vdd=ELVDD and also that, given that the drive transistor T1 is of a P-channel type, Vdd>Vg, the drive current I1 can be expressed by the following equation:
I1=(β/2)(Vdd−Vg−|Vth|)2 (7)
Moreover, since the gate voltage Vg=Vg(i,j) changes due to a leakage current Ioff through the first initialization transistor T4 during the emission period, the gate voltage Vg is considered to be a function of time t and therefore represented by Vg(t), and assuming that the end of the data write period for the pixel circuit Pix(i,j) at time t5 is represented by t=0 (see
Vg(0)=Vdata−|Vth| (8)
The gate voltage Vg(t), which changes due to the leakage current Ioff through the first initialization transistor T4 in the OFF state during the emission period, can be expressed by the following equation, from
Vg(t)=(Vg(0)−Vini)exp(−t/(Cst·Roff))+Vini (9)
Here, Vini, Cst, and Roff respectively represent an initialization voltage, a capacitance value of the holding capacitor Cst, an OFF resistance of the first initialization transistor T4.
Given the change of the gate voltage Vg due to the leakage current Ioff through the first initialization transistor T4, the drive current I1 can be expressed by the following equation using Vg(t) as obtained by equation (8) and (9).
I1=(β/2)(Vdd−Vg(t)−|Vth|)2 (10)
Accordingly, when no threshold control is performed on the drive transistor T1 in the pause drive mode, as can be seen from equations (8) and (9), the gate voltage Vg(t) gradually falls from Vg(0) as given by equation (8) during the emission period following the data write period for the pixel circuit Pix(i,j) and then rises to Vg(0) as given by equation (8) by virtue of data voltage writing during the next RF period. Specifically, the gate voltage Vg changes periodically in the refresh cycle Tref-PD in the pause drive mode, as shown in
I1=(β/2)(Vdd−Vg(0)−|Vth|)2
=(β/2)(Vdd−Vdata)2,
and by virtue of data voltage writing during the next RF period, the drive current I1 decreases to the value given by the following:
I1=(β/2)(Vdd−Vdata)2
Correspondingly, the luminance L(i,j) of the current-driven organic EL element OL changes periodically in the refresh cycle Tref-PD in the pause drive mode, as shown in
On the other hand, in the present embodiment, in the pause drive mode, the threshold Vth of the drive transistor T1 is controlled by providing the threshold control voltage Vtc(i) to the threshold control terminal (top gate electrode) TG of the drive transistor T1 in each pixel circuit Pix(i,j) via the threshold control line TCi. To enable this to inhibit the drive current I1 from changing due to changes of the gate voltage Vg, the threshold is considered to be a function Vth(t) of time t and ideally controlled such that:
Vg(t)+|Vth(t)|=Vg(0)+|Vth(0)| (11)
This renders it possible to keep the drive current I1 from changing and maintain the drive current I1 at a value given by the following equation based on equation (10):
I1=(β/2)(Vdd−Vg(0)−|Vth(0)|)2 (12)
Here, Vg(t) as given by equation (9) is approximated by the following equation, considering the value t/(Cst·Roff) to be sufficiently low:
Vg(t)=(Vg(0)−Vini)(1−t/(Cst·Roff))+Vini (13)
Equations (11) and (13) yield the following:
|Vth(t)|=|Vth(0)|+(Vg(0)−Vini)t/(Cst·Roff) (14)
Meanwhile, as in the present embodiment, when the top gate electrode TG of the drive transistor T1 serves as the threshold control terminal, the absolute value |Vth| of the threshold can be expressed by the following linear expression for the voltage Vtg on the top gate electrode TG.
|Vth|=a·Vtg+b
In the present embodiment, the threshold control voltage Vtc(i) is provided to the top gate electrode TG as Vtg, and therefore the above equation can be rewritten as follows:
|Vth|=a·Vtc(i)+b (15)
In equation (15), a is a constant equal to the gate insulating film capacitance ratio Ct/Cb between the top gate electrode TG and the bottom gate electrode BG (i.e., a=Ct/Cb). In the present embodiment, in the pause drive mode, the threshold Vth is changed by changing the threshold control voltage Vtc(i) provided to the top gate electrode TG as Vtg, and therefore when these two values are considered as functions Vth(t) and Vtc(i,t) of time t and the threshold control voltage is assumed to be such that Vtc(i,0)=VtcI where t=0, equation (15) yields the following:
b=|Vth(0)|−a·VtcI
This equation and equation (15) yield the following equation:
Vtc(i,t)={|Vth(t)|−b}/a
={|Vth(t)|−|Vth(0)|+a·VtcI}/a (16)
By substituting equation (14) into equation (16), the following can be obtained:
Vtc(i,t)=VtcI+(Vg(0)−Vini)t/{(Cst·Roff)·a}
=VtcI+(Vg(0)−Vini)t/{(Cst·Roff)(Ct/Cb)} (17)
Accordingly, in the present embodiment, in the pause drive mode, the threshold control circuit 22 generates and applies threshold control signals TC(1) to TC(n) to the threshold control lines TC1 to TCn, respectively, during the period (corresponding to one refresh cycle Tref-PD) that lasts from data voltage writing at time t=0 until data voltage writing during the next RF period following the emission period (including the NRF period), such that the threshold control voltage Vtc(i), which changes in accordance with equation (17), is provided to the threshold control terminal (top gate electrode) TG of the drive transistor T1 in each pixel circuit Pix(i,j) (where i=1 to n, and j=1 to m) via the threshold control line TCi (see
It should be noted that Vg(0) in equation (17) is given by equation (5) described earlier such that:
Vg(0)=Vdata−|Vth(0)|,
and therefore the threshold control voltage Vtc(i,t) as given by equation (17) depends on the data voltage Vdata that is to be written to the pixel circuit Pix(i,j), i.e., the voltage on the corresponding data signal line Dj. However, given this dependence, the threshold control voltage Vtc(i,t) may be generated in accordance with equation (17) using a gate voltage Vg(0)=Vdrp−|Vth(0)| corresponding to a representative data voltage value Vdrp, which is determined as either an average of the m data voltages Vdata that are to be written to the pixel circuits Pix(i,1) to Pix(i,m) connected to the corresponding threshold control line TCi or the data voltage that corresponds to the lowest luminance among the m data voltages Vdata. Specifically, for each threshold control line TCi (where i=1 to n), the representative data voltage value Vdrp is be determined for the data voltages to be written to the pixel circuits Pix(i,1) to Pix(i,m) that correspond to the threshold control line TCi, and the threshold control voltage Vtc(i) to be provided to the threshold control terminals TG of the drive transistors T1 in the corresponding circuits Pix(i,1) to Pix(i,m) is generated as expressed by a function Vtc(i,t) of time t given by the following equation using the determined representative data voltage value Vdrp.
Vtc(i,t)=VtcI+(Vdrp−|Vth(0)|−Vini)t/{(Cst·Roff)(Ct/Cb)} (18)
As can be seen from equation (18), when Ct>Cb, i.e., the gate insulating film capacitance Ct at the threshold control terminal is greater than the gate insulating film capacitance Cb at the main control terminal, decreasing the change amount (top/bottom range) of the threshold control voltage Vtc(i,t) still renders it possible to inhibit the fluctuation of the drive current I1 due to changes of the gate voltage Vg of the drive transistor T1.
Furthermore, the above representative data voltage value Vdrp may be replaced by a representative data voltage value Vdrp, which is determined as either an average of the n×m data voltages that are to be written to the n×m pixel circuits Pix(i,j) of the display portion 11b for each frame period or the data voltage that corresponds to the lowest luminance among the n×m data voltages Vdata. Alternatively, the representative data voltage value Vdrp for the n×m data voltage Vdata may be a predetermined value based on various display images. In either case, the same representative data voltage value Vdrp is determined for each threshold control line TCi, and therefore the display control circuit 20 provides the threshold control terminals TG of the drive transistors T1 in all pixel circuits Pix(1,1) to Pix(n,m) with threshold control voltages as given by the function Vtc(i,t) of time t defined by equation (18) using the same representative data voltage value Vdrp, i.e., the provided threshold control voltages are given by the same time function Vtc(i,t)=Vtc(t).
It should be noted that in the case where the threshold control voltages as given by the same time function Vtc(t) are provided to all pixel circuits Pix(1,1) to Pix(n,m), as described above, the n threshold control lines TC1 to TCn provided along the scanning signal lines G1 to Gn, as shown in
<1.6 Effects>
In the present embodiment as described above, in the pause drive mode, the threshold control voltage Vtc(i) is increased, thereby compensating for the decrease in the voltage that is being held by the holding capacitor Cst (or the change in the amount of stored charge) in each pixel circuit Pix(i,j), i.e., the decrease in the gate voltage Vg, which is caused due to a leakage current through the first initialization transistor T4 during the emission period (
<2.1 Overall Configuration and Overall Operation>
As in the first embodiment, the display device 10b according to the present embodiment operates in two modes: normal drive mode and pause drive mode. Moreover, as in the first embodiment, in the normal drive mode, the refresh period (RF period) is repeated, as shown in
<2.2 Configuration of the Pixel Circuit>
Next, the configuration of the pixel circuit 15 in the present embodiment will be described with reference to
It should be noted that in the pixel circuit 15b, the transistors T2 to T8, i.e., all the transistors excluding the drive transistor T1, function as switching elements. Moreover, as in the first embodiment, the drive transistor T1 is a double-gate P-channel transistor with a top gate electrode TG and a bottom gate electrode BG (see
The pixel circuit 15b is connected to a corresponding scanning signal line Gi, which is a scanning signal line corresponding thereto, a preceding scanning signal line Gi−1, which is a scanning signal line immediately preceding the corresponding scanning signal line Gi, a corresponding emission control line Ei, which is an emission control line corresponding to the pixel circuit 15b, a corresponding data signal line Dj, which is a data signal line corresponding to the pixel circuit 15b, an initialization voltage supply line Vini, a high-level power supply line ELVDD, and a low-level power supply line ELVSS. The pixel circuit 15b is the same as the pixel circuit 15 in the first embodiment in terms of the form of connections between the lines, including the above signal and power supply lines, and all elements excluding the threshold control transistor T8, the threshold control capacitor Ctc, and the threshold control resistance element Rtc (i.e., the organic EL element OL, the drive transistor T1, the write control transistor T2, the threshold compensation transistor T3, the first initialization transistor T4, the first emission control transistor T5, the second emission control transistor T6, the second initialization transistor T7, and the holding capacitor Cst), and also the form of connections between all the elements excluding the threshold control transistor T8, the threshold control capacitor Ctc, and the threshold control resistance element (see
In the present embodiment, unlike in the first embodiment, the pixel circuit 15b includes the threshold control transistor T8, the threshold control capacitor Ctc, and the threshold control resistance element Rtc, the threshold control terminal (top gate electrode) TG of the drive transistor T1 is connected to the high-level power supply line ELVDD via the threshold control capacitor Ctc, to the initialization voltage supply line Vini via the threshold control transistor T8, and to the high-level power supply line ELVDD via the threshold control resistance element Rtc, as shown in
<2.3 Operation of the Pixel Circuit>
As can be appreciated by comparing the signal waveform diagram shown in
<2.4 Configuration and Operation for Threshold Control>
In the present embodiment, the voltage Vtc (referred to below as the “threshold control voltage”) on the threshold control terminal TG of the drive transistor T1 in each pixel circuit Pix(i,j) changes as shown in
When the threshold control transistor T8 is in an ON state, the threshold control capacitor Ctc is charged by the high-level power supply line ELVDD and the initialization voltage supply line Vini so as to hold a voltage Vdd-Vini. Thereafter, the threshold control transistor T8 transitions to an OFF state at the end of the data write period at time t5, and thereafter while the threshold control transistor T8 is in the OFF state, charge stored on the threshold control capacitor Ctc is released via the threshold control resistance element Rtc. Accordingly, the threshold control voltage Vtc(t) at this time can be expressed by the following equation.
Vtc(t)=(Vini−Vdd)exp(−t/(Ctc·Rtc))+Vdd (19)
Here, assuming that t/(Ctc·Rtc) is sufficiently low, Vtc(t) as given by equation (19) is approximated by the following equation.
Vtc(t)=(Vini−Vdd){1−t/(Ctc·Rtc)}+Vdd
=Vini+(Vdd−Vini)t/(Ctc·Rtc) (20)
In the present embodiment, as in the first embodiment, the threshold control voltage Vtc is changed so as to inhibit the drive current I1 from increasing due to a decrease in the gate voltage Vg caused by a leakage current through the first initialization transistor T4 during the emission period. To this end, as can be appreciated by comparing equations (17) and (20) described earlier, in the present embodiment, given that Vtc(0)=Vini, the capacitance value of the threshold control capacitor Ctc (the capacitance value will also be denoted by the symbol “Ctc”) and the resistance value of the threshold control resistance element Rtc (the resistance value will also be denoted by the symbol “Rtc”) are set so as to satisfy the following equations:
(Vdd−Vini)/(Ctc·Rtc)=(Vg(0)−Vini)/{(Cst·Roff)·Ct/Cb}
Ctc·Rtc=(Vdd−Vini)(Cst·Roff)(Ct/Cb)/(Vg(0)−Vini) (21)
It should be noted that Vg(0) in equations (21) is given by equation (5) described earlier such that:
Vg(0)=Vdata−|Vth(0)|,
and therefore, when equations (21) are satisfied, the capacitance value Ctc and the resistance value Rtc depend on the data voltage Vdata that is to be written to the pixel circuit Pix(i,j). However, given this dependence, a representative data voltage value Vdrp may be determined in the same manner as in the first embodiment, and the capacitance value Ctc of the threshold control capacitor and the resistance value Rtc of the threshold control resistance element may be set in accordance with equation (21) using a gate voltage Vg(0)=Vdrp−|Vth(0)|, which corresponds to the determined representative data voltage value Vdrp. Note that the capacitance value Ctc and the resistance value Rtc are circuit constants, and therefore the representative data voltage value Vdrp determined in the present embodiment is a fixed value.
Furthermore, as can be appreciated from equations (21), when Ct<Cb, i.e., the gate insulating film capacitance Ct at the threshold control terminal is less than the gate insulating film capacitance Cb at the main control terminal, setting Ctc·Rtc lower than Cst·Roff still renders it possible to achieve the desired effect of inhibiting the fluctuation of the drive current I1 due to changes of the gate voltage Vg of the drive transistor T1.
<2.5 Effects>
In the present embodiment as described above, in each pixel circuit Pix(i,j), the threshold control capacitor Ctc, the threshold control transistor T8, and the threshold control resistance element Rtc constitute a threshold control circuit 24 for generating the threshold control voltage Vtc (see
The disclosure is not limited to the embodiments, and various modifications can also be made without departing from the scope of the disclosure.
For example, in the first embodiment, in the normal drive mode, the threshold control voltage Vtc(i) is fixed to VtcI but may be changed as in the pause drive mode (see
Furthermore, in the first embodiment, in the pause drive mode, for each row of pixel circuits Pix(i,1) to P(i,m), the threshold control voltage Vtc(i), which is changed at times suitable for the row, is provided to the threshold control terminals TG of the drive transistors T1 in the pixel circuits Pix(i,1) to P(i,m) via the threshold control lines TC1 to TCn (see
In the first and second embodiments, the top gate electrode TG of the drive transistor T1 is used as the threshold control terminal, and the bottom gate electrode BG is used as the main gate terminal (i.e., the control terminal for controlling the current flowing through the drive transistor T1) (
In the pause drive mode of the first embodiment and the second embodiment, the threshold control voltage Vtc(i) or Vtc provided to the threshold control terminal TG of the drive transistor T1 in each pixel circuit Pix(i,j) changes periodically in the refresh cycle that corresponds to intervals of data voltage writing to the pixel circuit Pix(i,j). Specifically, as shown in figures such as
The first and second embodiments use the pixel circuits 15 and 15b for internal compensation, as shown in
In the first and second embodiment, the equation for the decrease in the gate voltage Vg (i.e., the voltage that is being held by the holding capacitor Cst), which causes flickering in a display image, is formulated considering only the leakage current through the first initialization transistor T4 as the cause of the decrease, and the equation for the threshold control voltage Vtc for compensating for the decrease is derived from the formulated equation. In the case where some leakage current in another path (e.g., a leakage current in a path from the main gate terminal of the drive transistor T1 through the threshold compensation transistor T3, the emission control transistor T6, and the organic EL element OL to the low-level power supply line ELVSS) is not negligible as a cause of the decrease in the gate voltage Vg, the equation for the threshold control voltage Vtc for compensating for the decrease can also be derived by formulating the equation for the decrease in the gate voltage Vg in accordance with a similar approach to the above.
While the embodiments and the variants thereof have been described above taking as an example the organic EL display device, the disclosure is not limited to the organic EL display device and can be applied to any display devices, so long as the display devices use current-driven display elements. Display elements that can be used are those for which luminance, transmittance, etc., are controlled by currents, and in addition to organic EL elements, that is, organic light-emitting diodes (OLEDs), examples of the display elements include inorganic light-emitting diodes and quantum-dot light-emitting diodes (QLEDs).
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2018/036597 | 9/28/2018 | WO |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2020/066024 | 4/2/2020 | WO | A |
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| 20040036669 | Yanagi | Feb 2004 | A1 |
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| Number | Date | Country |
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| 2004-078124 | Mar 2004 | JP |
| 2013-003569 | Jan 2013 | JP |
| 2017-083813 | May 2017 | JP |
| Number | Date | Country | |
|---|---|---|---|
| 20210343238 A1 | Nov 2021 | US |
