Patent Application
20210125575
The present disclosure relates to a display device including an active matrix substrate, and more particularly, to a display device including a demultiplexer for time-divisionally applying data signals output from a data drive circuit to two or more data signal lines in a corresponding active matrix substrate and a drive method thereof.
Display devices such as an active matrix liquid crystal display device use an active matrix substrate in which a plurality of data signal lines (also referred to as “source bus lines”), a plurality of scanning signal lines (also referred to as “gate bus lines”) intersecting the plurality of data signal lines, and a plurality of pixel forming units arranged in a matrix along the plurality of data signal lines and the plurality of scanning signal lines are formed. In some of the display devices, a method is employed in which a plurality of data signal lines in the active matrix substrate are divided into a plurality of sets of data signal line groups with two or more data signal lines making up one set, and data signals are time-divisionally applied to two or more data signal lines in each set (hereinafter referred to as a “source shared driving (SSD) method”).
In the SSD method, a plurality of demultiplexers are used corresponding to the plurality of sets, and a data drive circuit outputs a plurality of data signals to the plurality of demultiplexers, respectively. Each demultiplexer includes two or more switching elements that are respectively connected to two or more data signal lines of the corresponding set. As a data signal from the data drive circuit, an analog voltage is applied to one of the two or more data signal lines via an on-state switching element of the two or more switching elements in the demultiplexer, and the switching elements in each demultiplexer are sequentially switched to the on-state. When the switching element connected to each data signal line is in the on-state in the demultiplexer, a data signal is applied to the data signal line the via the switching element, and then, when the switching element changes to the off-state, the analog voltage as the data signal is held in a wiring capacitor thereof. When one of the plurality of scanning signal lines is activated (selected) in a state where the analog voltage as the data signal is applied to or held in each data signal line as described above, the voltage of the data signal line is written as pixel data in the pixel forming unit connected to the activated scanning signal line.
In the active matrix display device employing the SSD method, when after the analog voltage is applied to each data signal line via the switching element that is in the on-state, the switching element changes to the off-state by changing the level of a control signal of the switching element, the voltage held in the data signal line becomes lower or higher than the original voltage as the data signal, due to parasitic capacitance (this phenomenon is referred to as a “field-through phenomenon” or a “feed-through phenomenon”). For example, when the switching element is an N-channel transistor and the voltage applied to a gate terminal as a control terminal (hereinafter referred to as a “gate voltage”) is changed from a high level (H level) to a low level (L level) to put the switching element to the off-state, the voltage held in the corresponding data signal line becomes lower than the original voltage as the data signal, due to the influence of the change in the gate voltage via the parasitic capacitance. On the other hand, when the switching element is a P-channel transistor and the voltage applied to a gate terminal as the control terminal (gate voltage) is changed from the L level to the H level to put the switching element to the off-state, the voltage held in the corresponding data signal line becomes higher than the original voltage as the data signal, due to the influence of the change in the gate voltage via the parasitic capacitance.
Incidentally, in the display device including the active matrix substrate using the SSD method, it is normal that each switching element in the demultiplexer changes from the off-state to the on-state and then changes from the on-state to the off-state in each horizontal period. That is, the number of toggles of each switching element in the demultiplexer is twice per horizontal period. With regard to such a display device using the SSD method, a configuration of reducing the number of toggles to reduce power consumption (hereinafter referred to as a “toggle-number reducing configuration”) has been proposed (for example, International Publication No. 2018/190245, paragraphs [0170] to [0173]).
When the toggle-number reducing configuration is employed, each demultiplexer includes a switching element that changes from the on-state to the off-state and a switching element that does not change from the on-state to the off-state, in each horizontal period. Therefore, one set of data signal line groups connected to each demultiplexer includes a data signal line in which the feed-through phenomenon occurs and a data signal line in which the feed-through phenomenon does not occur in each horizontal period, resulting in deterioration of display quality. In particular, when a large-sized transistor is used as a switching element in each demultiplexer, a significant difference occurs in the voltage held between the data signal line in which the feed-through phenomenon occurs and the data signal line in which the feed-through phenomenon does not occur, which causes a significant deterioration of display quality.
Therefore, in the display device including the active matrix substrate using the SSD method, it is desirable to suppress deterioration of the display quality due to the feed-through phenomenon of the data signal line while reducing power consumption.
According to an aspect of the disclosure, there is provided a display device including an active matrix substrate provided with a plurality of data signal lines, a plurality of scanning signal lines intersecting the plurality of data signal lines, and a plurality of pixel forming units arranged along the plurality of data signal lines and the plurality of scanning signal lines. The display device includes a demultiplexing circuit that includes a plurality of demultiplexers respectively corresponding to a plurality of sets of data signal line groups obtained by dividing the plurality of data signal lines into groups with two or more data signal lines making up one set, and a plurality of input terminals respectively corresponding to the plurality of demultiplexers, a data drive circuit that applies, to each of the plurality of input terminals, a signal into which two or more data signals are time-division multiplexed as a multiplexed data signal, the two or more data signals being respectively applied to the two or more data signal lines in the set corresponding to the input terminal, among a plurality of data signals representing an image to be displayed, and a demultiplexing control circuit that generates a demultiplexing control signal for controlling the demultiplexing circuit such that the plurality of data signals are respectively applied to the plurality of data signal lines. Each of the plurality of demultiplexers includes two or more main switching elements respectively corresponding to the two or more data signal lines in the corresponding set, the main switching elements each having a first conduction terminal connected to the corresponding data signal line, a second conduction terminal connected to the input terminal corresponding to the demultiplexer, and a control terminal for receiving a connection control signal for switching between an on-state and an off-state based on the demultiplexing control signal, and two or more sub-switching elements respectively corresponding to the two or more main switching elements, the sub-switching elements each having first and second conduction terminals respectively connected to the first and second conduction terminals of the corresponding main switching element, and a control terminal for receiving a connection control signal for switching between the on-state and the off-state based on the demultiplexing control signal, and the demultiplexing control circuit generates the demultiplexing control signal such that each of the two or more sub-switching elements included in each of the plurality of demultiplexers is turned off at a point in time later than a point in time when the corresponding main switching element is turned off.
According to another aspect of the disclosure, there is provided a drive method of a display device that includes an active matrix substrate provided with a plurality of data signal lines, a plurality of scanning signal lines intersecting the plurality of data signal lines, and a plurality of pixel forming units arranged along the plurality of data signal lines and the plurality of scanning signal lines. The display device includes a demultiplexing circuit that includes a plurality of demultiplexers respectively corresponding to a plurality of sets of data signal line groups obtained by dividing the plurality of data signal lines into groups with two or more data signal lines making up one set, and a plurality of input terminals respectively corresponding to the plurality of demultiplexers. Each of the plurality of demultiplexers includes two or more main switching elements respectively corresponding to the two or more data signal lines in the corresponding set, the main switching elements each having a first conduction terminal connected to the corresponding data signal line, a second conduction terminal connected to the input terminal corresponding to the demultiplexer, and a control terminal for receiving a connection control signal for switching between an on-state and an off-state, and two or more sub-switching elements respectively corresponding to the two or more main switching elements, the sub-switching elements each having first and second conduction terminals respectively connected to the first and second conduction terminals of the corresponding main switching element, and a control terminal for receiving a connection control signal for switching between the on-state and the off-state. The drive method includes applying, to each of the plurality of input terminals, a signal into which two or more data signals are time-division multiplexed, the two or more data signals being respectively applied to the two or more data signal lines in the set corresponding to the input terminal, among a plurality of data signals representing an image to be displayed, and controlling the main switching elements and the sub-switching elements in the demultiplexing circuit such that the plurality of data signals are respectively applied to the plurality of data signal lines. In the controlling, the two or more main switching elements and the two or more sub-switching elements are controlled such that each of the two or more sub-switching elements included in each of the plurality of demultiplexers is turned off at a point in time later than a point in time when the corresponding main switching element is turned off.
These and other objects, features, aspects and effects of the present invention will become more apparent from the following detailed description of the present invention with reference to the accompanying drawings.
Hereinafter, embodiments will be described with reference to the accompanying drawings. Note that, in each transistor described below, a gate terminal corresponds to a control terminal, one of a drain terminal and a source terminal corresponds to a first conduction terminal, and the other corresponds to a second conduction terminal. Further, it is assumed that the transistors in each of the following embodiments are all N-channel thin film transistors, but the present disclosure is not limited thereto. The present disclosure can be applied when a field effect transistor is used in a demultiplexing circuit described below regardless of whether it is an N-channel type or a P-channel type. Further, the term “connection” in the present specification means “electrical connection” unless otherwise specified, and as long as it does not depart from the gist of the present disclosure, not only the case where it means a direct connection but also the case where it means an indirect connection via another element is included.
Each pixel forming unit 10 corresponds to any one of the source bus lines SL1 to SL2m, and corresponds to any one of the gate bus lines GL1 to GLn, and each pixel forming unit is connected to the corresponding gate bus line GLi and source bus line SLj (1≤i≤n, 1≤j≤2m).
As shown in
As the TFT 11 in the pixel forming unit 10, a thin film transistor using amorphous silicon for a channel layer, a thin film transistor using low temperature polysilicon for the channel layer (LTPS-TFT), a thin film transistor using an oxide semiconductor for the channel layer (hereinafter referred to as an “oxide TFT”), and the like can be employed. As the oxide TFT, for example, a thin film transistor having an oxide semiconductor layer containing an In—Ga—Zn—O-based semiconductor (for example, indium gallium zinc oxide) can be employed. In the present embodiment, it is assumed that an oxide TFT is used as the TFT 11 in the pixel forming unit 10. The gate driver 50 and the demultiplexing circuit 40 are integrally formed with the pixel forming unit 10 on the active matrix substrate 100, and it is assumed that the oxide TFT is also used for the TFT in the demultiplexing circuit 40.
The display control circuit 20 receives the input signal Sin from the outside, and generates and outputs a data control signal Scd, a scanning side control signal Scs, a demultiplexing control signal Ssw, and a common voltage Vcom (not shown) based on the input signal Sin. The data control signal Scd is applied to the source driver 30 as a data drive circuit, the scanning side control signal Scs is applied to the gate driver 50 as a scanning signal line drive circuit, and the demultiplexing control signal Ssw is applied to the demultiplexing circuit 40, respectively. Thereby, the display control circuit 20 controls the source driver 30 and the gate driver 50, and also controls the demultiplexing circuit 40. As described above, in the present embodiment, the circuit for controlling the demultiplexing circuit 40, that is, the demultiplexing control circuit is included in the display control circuit 20, but it may be separated from the display control circuit 20 or may be provided in the source driver 30 or the gate driver 50.
The gate driver 50 generates scanning signals G1, G2, . . . , Gn for sequentially selecting n gate bus lines GL1, GL2, . . . , GLn based on the scanning side control signal Scs to apply them to the n gate bus lines GL1, GL2, . . . , GLn, respectively. By driving the gate bus lines GL1 to GLn by the gate driver 50 as described above, the n gate bus lines GL1 to GLn are sequentially selected for one horizontal period, and such sequential selection of the n gate bus lines GL1 to GLn is repeated with one frame period as a cycle. Here, the “horizontal period” refers to a period of a portion corresponding to one line of a display image in a video signal based on horizontal scanning and vertical scanning. Note that the gate bus lines GL1 to GLn may be sequentially selected for each of a plurality of horizontal periods (for example, two horizontal periods).
The data control signal Scd applied to the source driver 30 includes an image signal Sv representing an image to be displayed and a data timing control signal Sct (for example, a start pulse signal or a clock signal). The source driver 30 drives the source bus lines SL1 to SL2m via the demultiplexing circuit 40 by generating and outputting data output signals Do1 to Dom, at a timing corresponding to the driving of the gate bus lines GL1 to GLn by applying the scanning signals G1 to Gn, based on such a data control signal Scd (details will be described below). Generally, in the display device using the SSD method, the source bus lines in the active matrix substrate are divided into a plurality of sets of source bus line groups with two or more source bus lines making up one set, and the source driver includes a plurality of output terminals respectively corresponding to the plurality of sets as output terminals for driving the source bus lines. As shown in
The demultiplexing circuit 40 is integrally formed with the n×2m pixel forming units 10 of the display unit 101 on the active matrix substrate 100, receives multiplexed data signals Do1 to Dom from the source driver 30, and demultiplexes these multiplexed data signals Do1 to Dom based on the demultiplexing control signal Ssw to apply them as 2m data signals D1 to D2m to the source bus lines SL1 to SL2m, respectively.
As described above, the data signals D1 to D2m are applied to the source bus lines SL1 to SL2m, and the scanning signals G1 to Gn are applied to the gate bus lines GL1 to GLn. Further, the common voltage Vcom is supplied from the display control circuit 20 to the common electrode Ec. By driving the source bus lines SL1 to SL2m and the gate bus lines GL1 to GLn in the display unit 101 as described above, pixel data is written in each pixel forming unit 10 based on the image signal Sv in the input signal Sin, and the back surface of the display unit 101 is irradiated with light from a backlight (not shown), so that the image represented by the image signal Sv is displayed on the display unit 101.
As shown in
Further, as shown in
Further, in each demultiplexer 41k (k=1 to m), two main connection control transistors Ma1 and Mb1 are connected in parallel with two sub-connection control transistors Ma0 and Mb0 as sub-switching elements, respectively. That is, the two main connection control transistors Ma1 and Mb1 correspond to the two sub-connection control transistors Ma0 and Mb0, respectively, and the source terminal and the drain terminal of each of the two main connection control transistors Ma1 and Mb1 are respectively connected to the source terminal and the drain terminal of the corresponding sub-connection control transistor. Therefore, the input terminal Tdk corresponding to each demultiplexer 41k is connected to the 2k−1-th source bus line SL2k−1 via one main connection control transistor Ma1 and is also connected to the 2k−1-th source bus line SL2k−1 via one sub-connection control transistor Ma0, or is connected to the 2k-th source bus line SL2k via the other main connection control transistor Mb1 and is also connected to the 2k-th source bus line SL2k via the other sub-connection control transistor Mb0. In the present embodiment, the respective sizes (correctly, channel widths) of the sub-connection control transistors Ma0 and Mb0 are smaller than the respective sizes (correctly, channel widths) of the main connection control transistors Ma1 and Mb1, but they may be the same. Note that, hereinafter, for convenience, the conduction terminal, which is connected to the source bus line, of the two conduction terminals in each of the main connection control transistors Ma1 and Mb1 will be referred to as the drain terminal. The same applies to the sub-connection control transistors Ma0 and Mb0.
As shown in
The demultiplexing control signal Ssw applied to the demultiplexing circuit 40 includes an A main control signal ASW1, a B main control signal BSW1, an A sub-control signal ASW0, and a B sub-control signal BSW0 as shown in
The demultiplexing circuit 40 configured as described above operates as follows based on the demultiplexing control signal Ssw (the A main control signal ASW1, the B main control signal BSW1, the A sub-control signal ASW0, and the B sub-control signal BSW0) from the display control circuit 20, thereby demultiplexing the multiplexed data signals Do1 to Dom output from the source driver 30 and applying them as 2m data signals D1 to D2m to the source bus lines SL1 to SL2m, respectively. Hereinafter, referring to
As shown in
After that, at time t2, the A main control signal ASW1 changes from the H level to the L level, and the A main control transistor Ma1 enters the off-state. At this time, the voltage change of the A main control signal ASW1 from the H level to the L level affects the voltage of the 2k−1-th source bus line SL2k−1 via the parasitic capacitance Cpa1 of the A main control transistor Ma1 and reduces the voltage (hereinafter, the amount of voltage drop at this time is referred to as a “feed-through voltage due to turn-off of the A main control transistor Ma1”). However, at time t2, since the A sub-control transistor Ma0 is maintained in the on-state, the voltage of the source bus line SL2k−1 changes from the reduced voltage to the original voltage (see
After that, at time t3, the A sub-control signal ASW0 changes from the H level to the L level, and the A sub-control transistor Ma0 enters the off-state. At this time, the voltage change of the A sub-control signal ASW0 from the H level to the L level affects the voltage of the 2k−1-th source bus line SL2k−1 via the parasitic capacitance Cpa0 of the A sub-control transistor Ma0 and reduces the voltage (hereinafter, the amount of voltage drop at this time is referred to as a “feed-through voltage due to turn-off of the A sub-control transistor”) again, and the voltage after the reduction is held in the source bus line SL2k−1. However, as described above, since the size of the A sub-control transistor Ma0 is smaller than the size of the A main control transistor Ma1, a capacitance value of the parasitic capacitance Cpa0 of the A sub-control transistor Ma0 is smaller than a capacitance value of the parasitic capacitance Cpa1 of the A main control transistor Ma1. Therefore, the feed-through voltage (absolute value) due to turn-off of the A sub-control transistor Ma0 at this time is smaller than the feed-through voltage (absolute value) due to turn-off of the A main control transistor Ma1. Note that, even if the capacitance values of both parasitic capacitances Cpa0 and Cpa1 are the same, the feed-through voltages (absolute values) of them are smaller than in the case of the related art. This is because the capacitance value of each of the parasitic capacitances Cpa0 and Cpa1 is smaller than a capacitance value of a parasitic capacitance of each transistor as a switching element in the demultiplexer of the related art as described below.
After that, at time t4, both the B main control signal BSW1 and the B sub-control signal BSW0 change from the L level to the H level, and the B main control transistor Mb1 and the B sub-control transistor Mb0 enter the on-state. At this time, the voltage of the multiplexed data signal Dok input to the demultiplexer 41k changes to the voltage of the data signal D2k to be written in the pixel forming unit 10 corresponding to the i-th gate bus line GLi and the 2k-th source bus line SL2k (data voltage to be written in the pixel forming unit 10 in the i-th row and the 2k-th column). Therefore, after time t4, the voltage of the multiplexed data signal Dok is applied to the 2k-th source bus line SL2k via the B main control transistor Mb1 as the voltage of such a data signal D2k, and is also applied to the 2k-th source bus line SL2k via the B sub-control transistor Mb0.
After that, at time t5, the i-th scanning signal Gi changes from the H level to the L level, and the i-th gate bus line GLi enters a non-selected state. Thereby, the writing of the voltage held in the 2k-th source bus line SL2k to the pixel forming unit 10 corresponding to the i-th gate bus line GLi and the 2k-th source bus line SL2k is ended.
After that, at time t6, the i-th 1H period ends and the i+1-th 1H period starts. At time t6, the voltage of the multiplexed data signal Dok input to the demultiplexer 41k changes to the voltage of the data signal D2k to be written in the pixel forming unit 10 corresponding to the i+1-th gate bus line GLi+1 and the 2k-th source bus line SL2k (data voltage to be written in the pixel forming unit 10 in the i+1-th row and the 2k-th column). Therefore, after time t6, the voltage of the multiplexed data signal Dok is applied to the 2k-th source bus line SL2k via the B main control transistor Mb1 as the voltage of the data signal D2k corresponding to the i+1-th display line, and is also applied to the 2k-th source bus line SL2k via the B sub-control transistor Mb0.
After that, at time t7, the B main control signal BSW1 changes from the H level to the L level, and the B main control transistor Mb1 enters the off-state. At this time, the voltage change of the B main control signal BSW1 from the H level to the L level affects the voltage of the 2k-th source bus line SL2k via the parasitic capacitance Cpa1 of the B main control transistor Mb1 and reduces the voltage (hereinafter, the amount of voltage drop at this time is referred to as a “feed-through voltage due to turn-off of the B main control transistor Mb1”). However, at time t7, since the B sub-control transistor Mb0 is maintained in the on-state, the voltage of the source bus line SL2k changes from the reduced voltage to the original voltage (see
After that, at time t8, the B sub-control signal BSW0 changes from the H level to the L level, and the B sub-control transistor Mb0 enters the off-state. At this time, the voltage change of the B sub-control signal BSW0 from the H level to the L level affects the voltage of the 2k-th source bus line SL2k via the parasitic capacitance Cpa0 of the B sub-control transistor Mb0 and reduces the voltage (hereinafter, the amount of voltage drop at this time is referred to as a “feed-through voltage due to turn-off of the B sub-control transistor”) again. However, as described above, since the size of the B sub-control transistor Mb0 is smaller than the size of the B main control transistor Mb1, a capacitance value of the parasitic capacitance Cpa0 of the B sub-control transistor Mb0 is smaller than a capacitance value of the parasitic capacitance Cpa1 of the B main control transistor Mb1. Therefore, the feed-through voltage (absolute value) due to turn-off of the B sub-control transistor Mb0 at this time is smaller than the feed-through voltage (absolute value) due to turn-off of the B main control transistor Mb1. Note that, similar to the above, even if the capacitance values of both parasitic capacitances Cpa0 and Cpa1 are the same, the feed-through voltages (absolute values) of them are smaller than in the case of the related art.
After that, at time t9, both the A main control signal ASW1 and the A sub-control signal ASW0 change from the L level to the H level, and the A main control transistor Ma1 and the A sub-control transistor Ma0 enter the on-state. At this time, the voltage of the multiplexed data signal Dok input to the demultiplexer 41k changes to the voltage of the data signal D2k−1 to be written in the pixel forming unit 10 corresponding to the i+1-th gate bus line GLi+1 and the 2k−1-th source bus line SL2k−1 (data voltage to be written in the pixel forming unit 10 in the i+1-th row and the 2k−1-th column). Therefore, after time t9, the voltage of the multiplexed data signal Dok is applied to the 2k−1-th source bus line SL2k−1 via the A main control transistor Ma1 as the voltage of such a data signal D2k−1, and is also applied to the 2k−1-th source bus line SL2k−1 via the A sub-control transistor Ma0.
After that, at time t10, the i+1-th scanning signal Gill changes from the H level to the L level, and the i+1-th gate bus line GLi+1 enters the non-selected state. Thereby, the writing of the voltage held in the 2k−1-th source bus line SL2k−1 to the pixel forming unit 10 corresponding to the i+1-th gate bus line GLi+1 and the 2k−1-th source bus line SL2k−1 is ended.
As described above, for each 1H period, the voltages of the multiplexed data signals Do1 to Dom output from the source driver 30 are demultiplexed and respectively applied to and held by the source bus lines SL1 to SL2m as the voltages of the data signals D1 to D2m. The voltages applied to and held by the source bus lines SL1 to SL2m are line-sequentially written as data voltages in the n×2m pixel forming units 10 of the display unit 101 in accordance with the scanning of the gate bus lines GL1 to GLn.
Note that in the present embodiment, the toggle-number reducing configuration is employed, and as can be seen from
Next, driving of the source bus line via a demultiplexing circuit (hereinafter referred to as a “demultiplexing circuit in the example of the related art”) 40a in the active matrix substrate shown in
As shown in (A) of
As can be seen from (B) of
Also in the simulation for obtaining the result of
In the present embodiment as described above, in each demultiplexer 41k, the A main control transistor Ma1 and the A sub-control transistor Ma0 change to the on-state at the same time, but the point in time to change to the off-state is slightly different, and the A sub-control transistor Ma0 changes to the off-state after the A main control transistor Ma1 changes to the off-state (see
A feed-through voltage ΔV0 at the sub-connection off point in time T0off which is the end point in time of charging of the source bus line, which is connected to the main selection transistor Ms1 and the sub-selection transistor Ms0, of the source bus lines SL2k−1 and SL2k, that is, the amount ΔV0 of voltage drop in the output waveform due to the field-through phenomenon becomes smaller as the size (channel width W0) of the sub-selection transistor Ms0 (Ma0, Mb0) is reduced. However, as shown in
In the simulation results shown in
When the connection off time difference ΔToff=T0off−T1off is “0”, the main selection transistor Ms1 and the sub-selection transistor Ms0 change to the off-state at the same time, and the feed-through voltage in the output waveform is maximized. As the connection off time difference ΔToff is increased, the time that can be secured for charging the source bus line via the sub-selection transistor Ms0 becomes long, so that the substantial feed-through voltage ΔVs can be reduced. However, as shown in
According to the above-described simulation results shown in
In (A) and (B) of
In the above-described comparative example, the feed-through voltage in the charging operation of the source bus line (the amount of voltage drop due to the field-through phenomenon at the connection off point in time Tcoff) is minimized when the channel width W of the connection control transistor is 50 μm, and the feed-through voltage at this time is about 60 mV (see (B) in
According to the present embodiment, since the feed-through voltage in the charging operation of the source bus line as the data signal line is significantly reduced in this way, even when the toggle-number reducing configuration is employed (see
Note that, in above the first embodiment, the total W1+W0 of the channel width W1 of the main connection control transistors Ma1 and Mb1 and the channel width W0 of the sub-connection control transistors Ma0 and Mb0 is 50 μm, which is fixed (see
Further, in the first embodiment, voltage amplitudes of the main control signals ASW1 and BSW1 (5 V in the above case) and voltage amplitudes of the sub-control signals ASW0 and BSW0 are the same, but they do not necessarily have to be the same. For example, from the viewpoint of suppressing the feed-through voltage related to the source bus line when the sub-connection control transistors Ma0 and Mb0 change to the off-state (sub-connection off point in time T0off), the voltage amplitudes of the sub-control signals ASW0 and BSW0 may be smaller than the voltage amplitudes of the main control signals ASW1 and BSW1.
Further, in the first embodiment, the point in time when the A main control transistor Ma1 and the B main control transistor Mb1 are turned on (the point in time when the main control signals ASW1 and BSW1 change to the H level) and the point in time when the A sub-control transistor Ma0 and the B sub-control transistor Mb0 are turned on (the point in time when the sub-control signals ASW0 and BSW0 change to the H level) coincide with each other (see
Next, a liquid crystal display device including an active matrix substrate using a monolithic SSD method according to a second embodiment will be described.
As shown in
In the present embodiment, as shown in
Therefore, according to the present embodiment, the demultiplexing circuit 40b operates similarly to the demultiplexing circuit 40 in the first embodiment (see
Note that, in the second embodiment, although four control signal lines are provided to control the main connection control transistors Ma1 and Mb1, and only two control signal lines are provided to control the sub-connection control transistors Ma0 and Mb0, the number of control signal lines to be provided in the demultiplexing circuit 40b is not limited thereto. More generally, the main connection control transistors to which the same main connection control signal is to be applied (m A main control transistors Ma1 or m B main control transistors Mb1) among 2m main connection control transistors Ma1 and Mb1 included in m demultiplexers 411 to 41m may be divided into two or more main connection control transistor groups, and two or more control signal lines may be provided to transmit the same main connection control signal to each of the two or more main connection control transistor groups. Further, for not only the main connection control transistors Ma1 and Mb1 but also the sub-connection control transistors Ma0 and Mb0, the number of control signal lines to be provided in the demultiplexing circuit 40b may be determined in consideration of the necessity of load distribution based on the sizes and the like. For example, when there is the necessity of load distribution for controlling the sub-connection control transistors Ma0 and Mb0, four control signal lines may be provided to control the sub-connection control transistors Ma0 and Mb0.
Next, a liquid crystal display device including an active matrix substrate using a monolithic SSD method according to a third embodiment will be described.
As shown in
In the present embodiment, the demultiplexing control signal Ssw applied to the demultiplexing circuit 40c includes two types of main control signals DG1 and DG2 and two sub-connection control signals ASW0 and BSW0 (A sub-control signal ASW0 and B sub-control signal BSW0), as shown in
As shown in
As shown in
As can be seen from
The demultiplexing circuit 40c including the boost circuits 421 to 42(2m) configured as described above operates as follows based on the demultiplexing control signal Ssw from the display control circuit 20, that is, the first to third A b boost control signals DL1A to DL3A, the first to third B boost control signals DL1B to DL3B, the A sub-control signal ASW0, and the B sub-control signal BSW0 as shown in
The A main control transistor Ma1 to which the A main control signal SW1 generated by the A boost circuit 421 is applied and the B main control transistor Mb1 to which the B main control signal SW2 generated by the B boost circuit 422 is applied constitutes the first demultiplexer 411, and a signal obtained by time-division multiplexing the data signals D1 and D2 to be respectively applied to the two source bus lines SL1 and SL2 is applied as the multiplexed data signal Do1 via a data output line VL1 to the input terminal of the demultiplexer 411. More specifically, for the first demultiplexer 411, in one of the first half and the second half of each horizontal period (1H period), the voltage of the data signal D1 is applied to the demultiplexer 411 via the data output line VL1, and in the other period, the voltage of the data signal D2 is applied to the demultiplexer 411 via the data output line VL1. The same applies to the other demultiplexers 412 to 41m.
As shown in
After that, at time t2, the third A boost control signal DL3A in the demultiplexing control signal Ssw changes from the H level to the L level, and at the time t3, the first A boost control signal DL1A changes from the H level to the L level and the second A boost control signal DL2A changes from the L level to the H level. In response to this, the voltage of the internal node N1A of the A boost circuit 421 is reduced and becomes the L level at time t3. Thereby, the A main control transistor Ma1 enters the off-state. After that, at time t4, the A sub-control signal ASW0 changes from the H level to the L level, whereby the A sub-control transistor Ma0 also enters the off-state. Note that, the time from time t3 to time t4 corresponds to the connection off time difference ΔToff=T0off−T1off in the first embodiment (see
After that, at time t5, the third B boost control signal DL3B in the demultiplexing control signal Ssw changes from the L level to the H level, whereby the voltage of the internal node N1B of the B boost circuit 422 is boosted via the boost capacitor Cbst (see
At a predetermined point in time from time t4 to time t5, the voltage applied from the source driver 30 to the data output line VL1 changes from the voltage of the data signal D1 to be applied to the source bus line SL1 to the voltage of the data signal D2 to be applied to the source bus line SL2. Therefore, after time t5, the voltage of the data signal D2 is applied to the source bus line SL2 by two paths of a path via the B main control transistor Mb1 that is in the on-state by the voltage of the boost H level at the internal node N1B and a path via the B sub-control transistor Mb0 in the on-state.
After that, at time t6, the i-th scanning signal Gi changes from the H level to the L level, and the i-th gate bus line GLi enters the non-selected state. Thereby, the writing of the voltage held in the second source bus line SL2 to the pixel forming unit 10 corresponding to the i-th gate bus line GLi and the first source bus line SL1 is ended.
At time t7 when the 1H period ends and the next 1H period (hereinafter referred to as a “second 1H period”) starts, the voltage applied from the source driver 30 to the data output line VL1 changes to the voltage of the data signal D2 of the next display line to be applied to the source bus line SL2. At this time, since the B main control transistor Mb1 and the B sub-control transistor Mb0 are maintained in the on-state, the voltage of the data signal D2 is applied to the source bus line SL2 after time t7.
Further, at time t7, the first A boost control signal DL1A in the demultiplexing control signal Ssw changes from the L level to the H level. Thereby, the internal node N1A of the A boost circuit 421 is precharged via a diode-connected transistor T1A (see
After that, at time t8, the third B boost control signal DL3B in the demultiplexing control signal Ssw changes from the H level to the L level, and at the time t9, the first B boost control signal DL1B changes from the H level to the L level and the second B boost control signal DL2B changes from the L level to the H level. In response to this, the voltage of the internal node N1B of the B boost circuit 422 is reduced and becomes the L level at time t9. Thereby, the B main control transistor Mb1 enters the off-state. After that, at time t10, the B sub-control signal BSW0 changes from the H level to the L level, whereby the B sub-control transistor Mb0 also enters the off-state. Note that, the time from time t9 to time t10 corresponds to the connection off time difference ΔToff=T0off−T1off in the first embodiment (see
After that, at time t11, the third A boost control signal DL3A in the demultiplexing control signal Ssw changes from the L level to the H level, whereby the voltage of the internal node N1A of the A boost circuit 421 is boosted via the boost capacitor Cbst (see
At a predetermined point in time from time t10 to time t11, the voltage applied from the source driver 30 to the data output line VL1 changes from the voltage of the data signal D2 to be applied to the source bus line SL2 to the voltage of the data signal D1 to be applied to the source bus line SL1. Therefore, after time t11, the voltage of the data signal D1 is applied to the source bus line SL1 by two paths of a path via the A main control transistor Ma1 that is in the on-state by the voltage of the boost H level at the internal node N1A and a path via the A sub-control transistor Ma0 in the on-state.
After that, at time t12, the i+1-th scanning signal Gill changes from the H level to the L level, and the i+1-th gate bus line GLi+1 enters the non-selected state. Thereby, the writing of the voltage held in the first source bus line SL1 to the pixel forming unit 10 corresponding to the i+1-th gate bus line GLi+1 and the first source bus line SL1 is ended.
The other demultiplexers 412 to 41m in the demultiplexing circuit 40c also operate in the same manner as above. As described above, for each 1H period, the voltages of the multiplexed data signals Do1 to Dom output from the source driver 30 are demultiplexed and respectively applied to and held by the source bus lines SL1 to SL2m as the voltages of the data signals D1 to D2m. In such a demultiplexing operation, in the transistor Ms1 to be in the on-state of the main connection control transistors Ma1 and Mb1 of the present embodiment, the voltage of the boost H level generated by the boost circuit 42j is applied to the gate terminal of the transistor Ms1. In this way, the voltages respectively applied to and held by the source bus lines SL1 to SL2m are line-sequentially written as data voltages in the n×2m pixel forming units 10 of the display unit 101 in accordance with the scanning of the gate bus lines GL1 to GLn.
According to the present embodiment as described above, each demultiplexer 41k includes sub-connection control transistors Ma0 and Mb0 in addition to the main connection control transistors Ma1 and Mb1 as in the first embodiment, by configuring the size and the control of the main connection control transistors Ma1 and Mb1 and the sub-connection control transistors Ma0 and Mb0 such that the feed-through voltage related to the source bus line is minimized by the operation of the demultiplexer 41k, the same effect as in the first embodiment can be obtained. In addition to this, according to the present embodiment, in each demultiplexer 41k, the voltage of the boost H level generated by the boost circuit 42j is applied to the gate terminal of the transistor Ms1 to be in the on-state of the main connection control transistors Ma1 and Mb1. Therefore, it is possible to realize an active matrix substrate compatible with the monolithic SSD method while reducing the size of the TFT as a switching element that constitutes each demultiplexer 41k from the one in the related art.
Therefore, in a display device, which is driven by a monolithic SSD method, using a TFT in which a channel layer is formed of a material having a relatively low mobility, such as an oxide semiconductor, power consumption can be reduced while suppressing an increase in frame size.
Note that, the sub-connection control transistors Ma0 and Mb0 are provided to suppress the feed-through voltage and do not need to have a large charging capacity. Therefore, it is not necessary to provide a circuit for boosting the sub-control signals ASW0 and BSW0 to be applied to the gate terminals of the sub-connection control transistors Ma0 and Mb0, and from the viewpoint of reducing the feed-through voltage related to the source bus line, it is preferable that the voltage amplitudes of the sub-control signals ASW0 and BSW0 are small. Here, when it is necessary to provide a circuit due to the characteristics of the transistors used as sub-connection control transistors Ma0 and Mb0, a circuit for boosting the sub-control signals ASW0 and BSW0 to be applied to the gate terminals of the sub-connection control transistors Ma0 and Mb0 may be provided.
Further, the configuration of the demultiplexing circuit using the boost circuit is not limited to the configuration shown in
Although the present disclosure has been described in detail above, the above description is illustrative in all aspects and not restrictive. It is understood that numerous other modifications and variations can be devised without departing from the scope of the present disclosure.
For example, in the active matrix substrate according to each of the above embodiments, the demultiplexing circuit is realized using only N-channel TFTs, but the present disclosure is not limited thereto. For example, a circuit such as the demultiplexing circuit in the active matrix substrate according to each of the above embodiments may be realized using only P-channel TFTs. In this case, the configuration related to the polarity of the voltage is different from that of each of the above embodiments, but since the specific configuration is apparent to those skilled in the art, the details will be omitted.
Further, the demultiplexing circuit usable in the present disclosure is not limited to the one configured and controlled as shown in
Note that, the display devices according to various modification examples can be configured by optionally combining the features of the display devices according to the above-described embodiments and the modification examples thereof, as long as the characteristics thereof are not violated.
Hereinabove, the liquid crystal display device, which is driven by an SSD method, using the active matrix substrate has been described as an example. However, the present disclosure is not limited thereto, and is also applicable to a display device other than the liquid crystal display device, for example, an organic electroluminescence (EL) display device as long as it is a display device driven by an SSD method.
The present disclosure contains subject matter related to that disclosed in US Provisional Patent Application No. 62-925792 filed in the US Patent Office on Oct. 25, 2019, the entire contents of which are hereby incorporated by reference.
It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and alterations may occur depending on design requirements and other factors insofar as they are within the scope of the appended claims or the equivalents thereof.
| Number | Date | Country | |
|---|---|---|---|
| 62925792 | Oct 2019 | US |
