Patent Grant
7812807
This Nonprovisional application claims priority under 35 U.S.C. §119(a) on Patent Application No. 2004/99939 filed in Japan on Mar. 30, 2004, the entire contents of which are hereby incorporated by reference.
The present invention relates to a driving device of a display device such as a liquid crystal display device, and particularly to a driving device of a display device such as an active matrix liquid crystal display device, and the display device.
One example of liquid crystal display devices is disclosed in Japanese Patent No. 2,837,027 (published on Dec. 14, 1998, corresponding U.S. Pat. No. 5,402,255).
The TCP includes (i) a driver chip 57 substantially at the center, (ii) the liquid crystal drive output external connection terminal section 55 at the upper side, (iii) the input/output signal external connection terminal section 51 (commonly used by a plurality of driver ICs) at the lower side and (iv) terminals S1 to S7 which come out from the lower side.
The chip portion is covered with a resin so as to be protected electrically and physically. Generally, the liquid crystal drive output external connection terminal section 55 is connected to the liquid crystal panel via an anisotropic conductive sheet. On the input/output signal external connection terminal section 51, slits are formed by cutting out the TCP. Then, by connecting the input/output signal external connection terminal section 51 with PWB, it becomes possible to commonly supply a signal to a plurality of driver ICs.
In this arrangement, the terminals S1 to S7 of the input/output signal external connection terminal section 51 are provided so that one terminal corresponds to one signal. Naturally, one pad corresponds to one signal.
The following description explains a basic principle of how the liquid crystal is driven by the liquid crystal driving device in reference to
In addition to the above inversion driving per period, there is an inversion driving per dot of a panel as a method of applying the electric field to a liquid crystal panel.
The above cases are different from each other in ease of building a display system and in image quality. The driving method of
In the driving device adopting the dot inversion driving, a plurality of operational amplifiers 76 are provided. To an output terminal of each of the operational amplifiers 76, two switching elements 102 and 104 are connected. These two switching elements 102 and 104 are formed by the first and second MOS transistors, respectively. Drain terminals 96 of the switching elements 102 and 104 are connected to a load capacitance C2.
A gate terminal of the first switching element 102 is coupled with a SELECT signal, and a gate terminal of the second switching element 104 is coupled with a complementary SELECT signal (an inversion signal of the SELECT signal).
A source terminal of the first switching element 102 is coupled with an external memory capacitor 66, and a source terminal 65 of the second switching element 104 is coupled with an output of the operational amplifier 76. When the SELECT signal is high, the switching element 102 is turned on, and the switching element 104 is turned off. When the SELECT signal is low, the switching element 102 is turned off, and the switching element 104 is turned on.
The external memory capacitor is provided for carrying out a charge sharing. The charge sharing is one type of precharging. That is, by utilizing the electric charge remaining in the source signal lines in a certain horizontal period, the precharging of the source signal lines is carried out in the following horizontal periods. As for the precharging, before the potential of the source signal line is set to the source signal potential for the horizontal period, a voltage is applied to the source signal line in advance. An object of this voltage application is to cause the source signal line to reach a desired source signal potential as quickly as possible.
In
In the line inversion driving, voltages are not randomly applied (that is, the applied voltage is not unknown in each horizontal period), but polarities of the voltages regularly shift in the horizontal period. On this account, energy for switching a load capacitance to be high is used for switching a next load capacitance to be low. Therefore, it is possible to decrease a voltage newly applied at the beginning of the horizontal period.
Adversely, energy for switching a load capacitance to be low is used for switching a next load capacitance to be high. Therefore, it is possible to decrease a voltage newly applied at the beginning of the horizontal period.
The external memory capacitor 66 time-averages voltages applied to the source signal lines. In the line inversion driving, an average voltage charged on the external memory capacitor 66 is a bias voltage between a maximum positive voltage and a minimum negative voltage (whose absolute value is maximum) applied to the source signal line. For example, when the maximum positive voltage is 6 V and the minimum negative voltage is −6 V, the bias voltage is 0 V. Therefore, the external memory capacitor is 0 V or close to 0 V.
The external memory capacitor 66 is connected between a common line (not illustrate) and a bias voltage source which is at a ground potential in this case.
In the driving device illustrated in
Therefore, when the SELECT signal is high, a plurality of switching elements 102 are turned on at the same time, and are connected to the external memory capacitor 66 provided externally. The external memory capacitor 66 then carries out the charge sharing so that the electric power charged to the load capacitance 96 from the output of the operational amplifier 76 is collected or discharged to the external memory capacitor 66.
Liquid crystal display devices have been developed in order to meet the demand of increasing the size of the screen for use in TVs, PCs, etc. Moreover, mid-size and small-size liquid crystal display devices and liquid crystal driving devices are developed for use in mobile terminals, such as mobile phones which are rapidly expanding its market in recent years.
For the screens of the liquid crystal display devices used for the above purposes, the liquid crystal driving devices are strongly desired to be small, be light, support many outputs, be high in speed, be low in cost, be high in display quality, and be low in power consumption (including a case of battery-driven).
However, because the number of pixels and the materials are different between a newly designed liquid crystal panel and a conventional liquid crystal panel, load capacitances and the like are also different between them, and hence external memory capacitors required for adequately carrying out the charge sharing are also different between them. On this account, in order to obtain the effect equivalent to that of the charge sharing of the conventional liquid crystal display device by using the newly designed liquid crystal display device, it is necessary, in the conventional technology, to adjust the timing of the pulse width (high period) of SELECT signal outputted from a controller so that an outputted driving voltage temporarily gets close to a medium driving voltage. For this, it becomes necessary to arrange a new controller.
The present invention was made to solve the above problems, and an object of the present invention is to realize a display device and a driving device which do not require the change in the arrangement of the controller, even when a newly designed display section (liquid crystal panel, etc.), which is different in the number of pixels and materials, is used.
In order to solve the above problems, the driving device of the present invention drives a display section of a display device by applying, in each horizontal period, voltages to pixels in the display section through source signal lines charged to have source signal potentials according to display data signals supplied from an outputting circuit, the driving device precharging the source signal lines before causing the source signal lines to have the source signal potentials for the above each horizontal period, and the driving device comprises: a switching circuit which (a) separates the outputting circuit from the source signal lines and (b) short-circuits at least one source signal line whose source signal potential is positive in one horizontal period and at least one source signal line whose source signal potential is negative in the above one horizontal period, so that the short-circuited source signal lines are precharged.
According to the above arrangement, the precharging is carried out by short-circuiting (i) at least one source signal line whose source signal potential is positive and (ii) at least one source signal line whose source signal potential is negative in the same horizontal period.
In this way, the precharging is completed by short-circuiting the source signal lines with each other inside the display section. Therefore, the external memory capacitor is unnecessary, and the adjustment of the external memory capacitor is obviously unnecessary. As a result, it is unnecessary to change or adjust the timing of the pulse width (high period) of the SELECT signal outputted from the controller. Therefore, it is unnecessary to renew the arrangement of the controller.
On this account, even when a newly designed display section (liquid crystal panel, etc.), which is different in the number of pixels and materials, is used, it is possible to realize a display device and a driving device which do not require the change in the arrangement of the controller.
Additional objects, features, and strengths of the present invention will be made clear by the description below. Further, the advantages of the present invention will be evident from the following explanation in reference to the drawings.
a) and 21(b) are diagrams illustrating one example of basic methods of driving liquid crystal.
a) and 21(b) are diagrams illustrating one example of various inversion driving methods.
a) and 23(b) are diagrams illustrating one example of various inversion driving methods.
a) and 24(b) are diagrams illustrating examples of various inversion driving methods.
The following description explains one embodiment of the present invention in reference to
The present embodiment takes a liquid crystal display device as an example of a display device. That is, the present embodiment takes a liquid crystal driving device as an example of a driving device.
Here, in the same horizontal period, some source signal lines have positive source signal potentials, while other source signal lines have negative potentials (that is, a dot inversion driving is basically performed).
Here, each of the source signal lines has a load capacitance. The load capacitance is a capacitance of load relative to the source signal lines. The load capacitance includes a capacitance of the source signal line itself and a pixel capacitance of a pixel of a selected line (in a direction along gate signal lines).
A liquid crystal display device 900 includes a liquid crystal display section (display section) and a liquid crystal driving device (driving device) which drives the liquid crystal display section.
The liquid crystal display section includes a TFT liquid crystal panel 901. In the liquid crystal panel 901, liquid crystal display elements (not illustrated) and a counter electrode (common electrode) 906 are provided.
Meanwhile, the liquid crystal driving device includes source drivers 902 each of which also includes an IC (Integrated Circuit), gate drivers 903 each of which is also composed of an IC (Integrated Circuit), a controller 904 and a liquid crystal driving power source 905.
Generally, each of the source drivers 902 and the gate drivers 903 is arranged in such a manner that (i) a TCP (Tape Carrier Package), formed by mounting an IC chip on a film having wirings, is mounted and connected to an ITO (Indium Tin Oxide, Indium Tin Oxide Film) terminal of a liquid crystal panel or (ii) thermocompression bonding is carried out so that an IC chip is mounted and connected to an ITO terminal of a liquid crystal panel via ACF (Anisotropic Conductive Film).
The controller 904 outputs sets of digitalized display data (for example, the sets of data are respectively R, G, and B signals corresponding to red, green and blue, respectively) and various control signals to the source drivers 902. Moreover, the controller 904 also outputs various control signals to the gate drivers 903. The control signals outputted to the source drivers 902 are mainly a horizontal synchronization signal, a start pulse signal, a clock signal for the source drivers, etc., which are indicated by S1 in
The liquid crystal driving power source 905 supplies a voltage for the liquid crystal panel display (in the present invention, a reference voltage for generating a voltage for displaying gradations) to the source drivers 902 and the gate drivers 903.
The sets of the display data supplied from the outside are inputted as a set of display data D (digital signals) to the source drivers 902 via the controller 904.
Each of the source drivers 902 internally latches the set of the inputted digitalized display data D in a time-division manner. Then, the source driver 902 performs DA (Digital-Analog) conversion in synchronism with the horizontal synchronization signal (also referred to as “latch signal LS” (see
The following description explains the liquid crystal display panel 901.
To the source signal lines 1004, the gradation displaying voltages corresponding to brightness of pixels for displaying images are applied from the source drivers 902. To the gate signal lines 1005, scanning signals for sequentially turning on TFTs 1003 lined up in a column direction are inputted from the gate drivers 903. The voltages of the source signal lines 1004 are applied via TFTs 1003 in an ON state to the pixel electrodes 1001 connected to drains of the TFTs 1003, so that the pixel capacitances 1002 provided between the pixel electrodes 1001 and the counter electrode 1006 are charged. Thus, the optical transmittance of liquid crystal is changed, so that the displaying is carried out.
Each of
For example, in
At this moment, the above-described voltage is held because of the pixel capacitance 1002 in the pixel. This is substantially the same as the case of
The difference between
The shift register 21 carries out shifting of an inputted start pulse SP in synchronism with an inputted clock signal CK. From each stage of the shift register 21, a control signal is outputted to the sampling memory 23. Note that, the start pulse SP is a signal which is synchronized with the horizontal synchronization signal LS of the data signals D (display data DR, DG and DB). Moreover, the start pulse SP shifted by the shift register 21 is inputted as the start pulse SP to a shift register 21 of an adjacent source driver, and the start pulse SP thus inputted is shifted in the same way as above. Eventually, the start pulse SP is transferred to a shift register of the farthest source driver from the controller 4.
The input latch circuit 22 temporarily latches the sets of the display data DR, DG and DB each of which is six-bit data and is serially inputted to an input terminal corresponding to each color, and the input latch circuit 22 transfers the sets of the display data DR, DG and DB to the sampling memory 23.
By using the output signals (control signals) from the respective stages of the shift register 21, the sampling memory 23 samples the sets of the display data DR, DG and DB (each of R, G and B has 6 bits, so that the total is 18 bits) transferred from the input latch circuit 22 in a time-divisional manner. Then, the sampling memory 23 stores the sets of the display data DR, DG and DB until all the display data DR, DG and DB for one horizontal synchronization period are supplied.
The holding memory 24 latches the sets of the display data DR, DG and DB according to the hold signal LS. Then, the sets of the display data DR, DG and DB are held until the next horizontal synchronization signal LS is inputted, and are outputted to the level shifter 25.
The level shifter 25 is a circuit which converts a signal level of each of the display data DR, DG and DB by boosting, etc. so that the sets of the display data DR, DG and DB thus converted are compatible with the DA converter which processes levels of voltages applied to the liquid crystal panel 901. The level shifter 25 outputs sets of display data D′R, D′G and D′B.
The reference voltage generating circuit 27 generates 64-level analog voltages, used for displaying gradations, according to a reference voltage VR supplied from the liquid crystal driving power source 905 (see
The DA converter 26 selects one of the 64-level analog voltages according to the sets of the display data (digital) D′R, D′G and D′B (each of R, G and B has 6 bits) inputted from the level shifter 25. In this way, the DA converter 26 performs conversion into the analog voltage and outputs the voltage to the outputting circuit 28. That is, as illustrated in
By selecting the switches respectively corresponding to the sets of the 6-bit display data D′R, D′G and D′B, the DA converter 26 selects one of the 64-level analog voltages inputted from the reference voltage generating circuit 27.
The outputting circuit 28 changes the analog signal selected by the DA converter 26 into a low impedance signal, and outputs the low impedance signal to the switching circuit 30.
According to (i) a clock signal CLK generated by the 1/n frequency divider 31 from the clock signal CK inputted to the shift register 21 and (ii) the hold signal LS which is outputted from the controller 904 and inputted to the holding memory 24 and (iii) 3-bit setting signals CTR1 to CTR3, the pulse width adjusting circuit 29 (for a hold signal LS) adjust a pulse width of the hold signal LSA on a scale of one to n (on a scale of one to eight in the present embodiment). Note that, an arrangement of the pulse width adjusting circuit 29 will be described later in detail.
As illustrated in
As described above, in the same horizontal period, there are the source signal lines whose source signal potentials are positive and the source signal lines whose source signal potentials are negative (that is, a dot inversion driving is basically performed). Such source signal lines are short-circuited with each other. In this way, it is possible to assist a precharging by electric charges, whose polarities are positive and negative, on data lines of the liquid crystal panel. That is, by utilizing residual electric charge in the liquid crystal panel, it is possible to reduce electric power for driving the liquid crystal. Note that, operations of the switching circuit 30 will be described later in detail.
The following explains the details of the pulse width adjusting circuit 29 in reference to
As illustrated in
The up counter circuit 6 sequentially carries out a counting operation by a clock signal inputted to three delay T flip flops 9 whose number corresponds to the number of setting (3 bits) of the setting signals CTR1 to CTR3.
The comparator 7 includes (i) three Exclusive-OR gates (hereinafter referred to as “EX-OR circuit”) 11 whose number is equal to the number of setting (the number of bits) of the setting signals CTR1 to CTR3 and (ii) one OR circuit 12.
The R-S flip flop 8 includes NAND circuits 13.
Each of the delay T flip flops 9 includes (i) a CK terminal which receives the clock signal CLK which is obtained by dividing the clock signal CK, inputted to the shift register 21, by 1/n by the 1/n frequency divider 31, (ii) an R terminal which receives, as a reset signal, a hold signal LS which is the same as the hold signal LS inputted to the holding memory 24 and (iii) output terminals Q and Q bar.
Note that, the output terminal Q bar outputs an inversion signal of a signal outputted from the output terminal Q.
Signals Q1, Q2 and Q3 (see
To the OR circuit 10, the signals Q1, Q2 and Q3 from the delay T flip flops 9 and a signal obtained by inverting, by an inverter 5, the hold signal LS inputted to the holding memory 24 are inputted.
That is, in the up counter circuit 6 arranged as above, i) the clock signal CLK which is obtained by dividing by 1/n the clock signal CK inputted to the shift register 21 and (ii) the hold signal LS inputted to the holding memory 24 are inputted to three delay T flip flops 9, and the delay T flip flops 9 outputs the signals Q1, Q2 and Q3, whose waveforms are illustrated in
The following briefly explains the signal outputted from the terminal Q of the delay T flip flop 9 in reference to
The signal Q1 outputted from the terminal Q of the delay T flip flop 9 in the first stage is a pulsed signal whose “0” and “1” are inverted in each cycle of the pulse of the clock signal CLK. That is, the signal Q1 is “0” in the first cycle of the pulse in one horizontal period and “1” in the next cycle.
Moreover, the signal Q2 outputted from the terminal Q of the delay T flip flop 9 in the second stage is a pulsed signal whose “0” and “1” are inverted per two cycles of the pulse of the clock signal CLK. Similarly, the signal Q2 is “0” in the first cycle of the pulse in one horizontal period.
Further, the signal Q3 outputted from the terminal Q of the delay T flip flop 9 in the third stage is a pulsed signal whose “0” and “1” are inverted per four cycles of the pulse of the clock signal CLK. Similarly, the signal Q3 is “0” in the first cycle of the pulse in one horizontal period.
Moreover, a signal OR10 which is a count signal from the up counter circuit 6 is “0” in the beginning of the horizontal period, that is, in the first cycle of the pulse of the clock signal CLK. However, the signal OR10 is “1” from the second cycle of the pulse of the clock signal CLK.
To the EX-OR circuits 11, the signals Q1, Q2 and Q3 from the delay T flip flops 9 of the up counter 6 are inputted, respectively. Moreover, the setting signals CTR1 to CTR3 are also inputted to the EX-OR circuits 11, respectively.
Moreover, when two signals thus inputted to each of the EX-OR circuits 11 are the same, “0” (a low-level signal) is supplied from the Ex-OR circuit 11 to the OR circuit 12. Meanwhile, when the two signals are different, “1” (a high-level signal) is supplied from the EX-OR circuit 11 to the OR circuit 12.
The signal is inputted from the EX-OR circuits 11 to the OR circuit 12. Then, the OR circuit 12 outputs the reset signal, which is a second signal inputted to the R-S flip flop circuit 8 in the next stage.
That is, the comparator 7 compares set values of the setting signals CTR1 to CTR3 with data values from the up counter circuit 6. Then, according to the set values, the comparator 7 resets the R-S flip flop circuit 8.
As described above, to the R-S flip flop circuit 8, the signal OR10 from the up counter circuit 6 is inputted as the set signal, and the signal from the comparator 7 is inputted as the reset signal. Then, the R-S flip flop circuit 8 adjusts the pulse width of the hold signal LSA according to the set values of the setting signals CTR1 to CTR3, and outputs the hold signal LSA.
That is, the hold signal LSA is obtained by adjusting the number of pulses (here, eight pulses (0 to 7)) of the clock signal CLK according to the setting signals CTR1 to CTR3, and is outputted.
According to one example of the hold signal LSA shown in
That is, when the number of pulses adjusted is x and the values of CTR1, CTR2 and CTR3 are a, b and c, respectively,
In
In the dot inversion driving illustrated in
The above description is much the same for A and B.
Time t1 is a start time of one horizontal period. As with conventional circuit arrangements, until Time t1, the hold signal LSA is a low level, the separating switches 30b are closed (ON), and the short-circuiting switches 30a are opened (OFF). Moreover, output signals D and E outputted from the outputting circuit 28 via the separating switches 30b and the output terminals are the same as conventional output signals A and B.
Then, Time t1, which is the start time of the horizontal period, and a rise of the hold signal LSA are synchronized with each other. As a result, at Time t1, the hold signal LSA becomes a high level “H”, the separating switches 30b are turned OFF and the short-circuiting switches are turned ON. Because the separating switches 30b are turned OFF, the outputting circuit 28 and the output terminal are electrically separated. Moreover, because the short-circuiting switches 30a are turned ON, the output terminals connected to pixels of the same color (R, G or B) are electrically connected. Therefore, the electric charge moves between those output terminals. Then, at a certain time (at Time t2), potentials of the output signals D and E become the same. A time from Time t1 to Time t2 is a charging/discharging time which is determined according to the load capacitance.
From t1 to t2, the electric charge moves between the output terminals. Therefore, no electric power is consumed.
Next, at Time t3, the hold signal LSA becomes a low level “L”, the separating switches 30b are turned ON and the short-circuiting switches are turned OFF. Therefore, the state of the circuit here becomes the same as that of the circuit until Time t1. On this account, the outputting circuit 28 charges/discharges the electric charge of the load capacitance of the source signal lines, and the electric power is consumed. At a certain time (at Time t4), the potentials of the output signals D and E are desired values (source signal potentials). A time from Time t3 to Time t4 is a charging/discharging time which is determined according to the load capacitance.
As above, the process is carried out as follows:
Moreover, (c) may be carried out at the time of (b) (that is, the time for the short-circuiting is none). Further, even in the case in which a time period when the hold signal LSA is high is decreased and the short-circuiting is canceled before the potentials of the short-circuited source signal lines become the same (that is, even in the case in which, before reaching the potential (short-circuit potential) of t2 of
A time period of the short-circuiting (short-circuit time) is determined in consideration of the following factors.
Factor 1: How close should the potentials of the source signal lines be shifted to a medium potential (short-circuit potential)?
Factor 2: To what extent should the source signal lines be charged so as to apply a desired voltage (display voltage) to the liquid crystal?
Factor 3: How much time is required for the voltages to rise and fall? (the time required for the voltages to rise and fall is determined by the load capacitance, and is therefore unchangeable)
When importance is attached to Factor 1, the pulse width adjusting circuit 29 prolongs the high-period of the hold signal LSA and thereby prolongs the duration of short-circuiting. When importance is attached to Factor 2, the pulse width adjusting circuit 29 shortens the high-period of the hold signal LSA and thereby shortens the duration of short-circuiting. Thus, the values of CTR1 to CTR3 are determined so that the high-period of the hold signal LSA has a desired length. Note that, if it is necessary to carry out the adjustment more precisely, the pulse width adjusting circuit 29 may use four CTRs. In this case, the values of CTR1 to CTR4 are determined on a scale of one to sixteen. If it is necessary to carry out the adjustment much more precisely, the pulse width adjusting circuit 29 may use five CTRs, and so forth.
In this way, without adjusting the timing of the pulse width (high period) of a SELECT signal by the controller, a driving voltage is easily changed to a medium driving voltage by the charge sharing. After that, it is possible to change smoothly to the voltage applied to liquid crystal panel (display voltage).
As illustrated in
As described above, the adjusting circuit, which is capable of changing the pulse width of the hold signal easily, is provided within the source driver. Therefore, the control signal for charge sharing can be changed easily without requiring to change the controller LSI, even though the load capacitance and the like are subject to change depending on the material of the liquid crystal panel and the number of pixels provided on the liquid crystal panel. Therefore, it is possible to realize the improvement of reliability and the high efficiency of designing.
Note that, explained above is one example in which the adjustment is carried out by the output signal from the pulse width adjusting circuit provided in the source driver. Needless to say, it is possible to easily change the arrangement by containing a similar circuit means in the controller. In this case, as illustrated in
In this case, the controller includes (i) a basic control section whose functions are the same as those of the controller of
Output terminals X1 to X128, Y1 to Y128 and Z1 to Z128 correspond to the display data DR, DG and DB, respectively. The number of each of the output terminals X, Y and Z is 128. Thus, according to the sets of the display data DR, DG and DB, source drivers for displaying 64 gradations output, to a liquid crystal panel, analog signals corresponding to gradation levels. As a result, 64-gradation displaying is carried out.
Moreover, the short-circuiting is carried out between the source signal lines connected to pixels of the same color (R, G or B). However, as long as polarities are different between the electric charges of the source signal lines, the short-circuiting can be carried out between the source signal lines connected to pixels (R, G or B) whose colors are different from each other (such as R and G, G and B, etc.).
Moreover, the present invention is applicable not only to the case of color display, but also to the case of monochrome display or binary image display.
Moreover, in
A liquid crystal driving circuit of the present invention is a liquid crystal driving circuit which drives a liquid crystal display device according to display data signals, and includes (i) a transferring circuit (shift register) which transfers a start pulse signal based on a clock signal, (ii) a latch circuit (input latch circuit) which fetches a display data signal in synchronism with the clock signal and outputs the display data signal as a set of synchronous data, (iii) a sampling circuit (sampling memory) which samples and outputs the set of the synchronous data according to the start pulse signal, (iv) a DA converter which carries out the DA conversion (Digital-Analog conversion) according to the data from the sampling circuit and (v) an outputting circuit which outputs, from a liquid crystal driving voltage output terminal, a voltage which is applied to the liquid crystal and is obtained from a gradation displaying analog voltage (for displaying gradations) obtained by the DA converter, and the liquid crystal driving circuit further includes a switching circuit which includes (i) a short-circuiting switching circuit which short-circuits the output terminals with each other, which are connected to pixels of the same color (R, G or B), before the outputting circuit outputs the voltage applied to the liquid crystal and (ii) a separating switch means which separates the output terminal from an outputting means so that the output terminal is in the state of floating.
Moreover, in addition to the above arrangement, the switching circuit of the liquid crystal driving circuit of the present invention may be arranged so that the charge sharing is carried out according to a control signal (LSA) temporarily stored in the source driver.
Moreover, in addition to the above arrangement, the switching circuit of the liquid crystal driving circuit of the present invention may be arranged so that a pulse width is adjusted according to binary setting signals (CTR1, CTR2 and CTR3) inputted from setting terminals.
Moreover, in addition to the above arrangement, the switching circuit of the liquid crystal driving circuit of the present invention may be arranged so that the charge sharing is carried out according to a control signal (LS) from the controller and can adjust a pulse width according to binary setting signals (CTR1, CTR2 and CTR3) inputted from setting terminals.
Moreover, according to the present invention, it is possible to realize a liquid crystal display device containing the liquid crystal driving circuit arranged as above.
The following explains another embodiment of the present invention in reference to
Depending on user requests, a new device may be produced by increasing or decreasing the number of output terminals of the existing source driver 902 illustrated in
Therefore, those six output terminals 910 are not connected to pixels R, G and B.
Therefore, the charge sharing is not carried out through the short-circuiting switches (short-circuiting means) 30a connected to two sets of three output terminals sandwiching the logic circuit 902 provided at the center of the source driver. In the description here, six output terminals connected to pixel groups A68 and A69 each composed of the pixels R, G and B are relevant to those two sets of three output terminals, and the charge sharing is not carried out for those six output terminals. Meanwhile, as for the output terminals connected to the pixel groups A67 and A70, the charge sharing is carried out between the output terminals which are adjacent with each other and are of the same color. Therefore, it is possible to reduce electric power consumption.
Here,
When comparing those waveforms, the waveform of the transient voltage outputted from each of the output terminals, between which the charge sharing is carried out, connected to the pixel group A67 composed of the pixels R, G and B or the pixel group A70 composed of the pixels R, G and B reaches (½) VLS faster than the waveform of the transient voltage outputted from each of the output terminals, between which the charge sharing is not carried out, connected to the pixel group A68 composed of the pixels R, G and B or the pixel group A69 composed of the pixels R, G and B. Note that, VLS is a maximum value of an output amplitude level, and VSS is a minimum value of the output amplitude level. As a result, depending on whether or not the charge sharing is carried out, the difference is given between the waveforms of the transient voltages outputted from the output terminals of the driver. Therefore, as illustrated in
Here, the present embodiment is so arranged that the charge sharing is carried out between the output terminals connected to pixels of the same color (R, G or B), without being influenced by the change in the number of output terminals according to user requests. In this way, the difference between the waveforms of the transient voltages is eliminated, and the reduction of the electric power consumption is realized.
As illustrated in
Especially, in order to carry out the charge sharing between the output terminals 910 connected to pixels of the same color (R, G or B), one end of the short-circuiting switch (short-circuiting means) 30a is connected to one of common bus lines RCS, GCS and BCS. As a result, without being influenced by the change in the number of output terminals, the charge sharing can be carried out between the output terminals 910 connected to pixels of the same color (R, G or B), via one of the common bus lines RCS, GCS and BCS.
Thus, in the present embodiment, each image is displayed by the pixel group composed of one or more pixels. Here, “each image” does not mean an image displayed by the entire screen but means an image displayed by pixel(s) by which users can recognize one color, that is, an image displayed by the pixels R, G and B (here, these three pixels are collectively referred to as “pixel group”). In the case of a monochrome display, one pixel group may be composed of only one pixel.
Moreover, via the short-circuiting switches 30a provided between the pixels, each pixel in each pixel group is connected to at least one pixels in all the other pixel groups. Then, in the precharging, the short-circuiting switches simultaneously turn ON/OFF.
With the above arrangement, each of the pixels in the pixel groups is connected to at least one pixel in the other pixel group so that the short-circuiting can be carried out. For example, when focusing on a pixel R in a certain pixel group, the pixel R is connected to at least one of pixels R, G and B in all of the pixel groups except in the pixel group including the pixel R in the certain pixel group. In
In addition to the arrangement illustrated in
Thus, even when a certain pixel group is separated from the source signal lines, the other pixel groups do not lose their partner for the short-circuiting. Therefore, the short-circuiting is carried out without fail. As a result, even when the pixel groups are decreased from the existing source driver, it is possible to suppress generating display troubles, such as vertical lines, etc.
Especially, in the present arrangement, the switching circuit 30 includes the short-circuiting switches 30a and the separating switches 30b. Each short-circuiting switch 30a carries out the short-circuiting between the source signals lines 1004 (S1, S2, . . . ) connected to pixels of the same color (R, G or B). One end of the short-circuiting switch 30a is connected to the source signal line, and another end of the short-circuiting switch 30a is connected to one of the bus lines RCS, GCS and BCS which are respectively common to the pixels R, G and B. Each separating switch 30b separates the outputting circuit from a source signal line, so that the outputting circuit is in the state of floating. Then, in the precharging, the short-circuiting is carried out between the source signal lines connected to pixels of the same color (R, G or B). In this way, the precharging of the source signal lines is carried out. That is, in the present embodiment, through bus lines and the short-circuiting switches between the pixels and the bus line, each pixel in each pixel group is connected to at least one pixel in all the other pixel groups. In the present embodiment, furthermore, only the pixels of the same color are connected with each other via the short-circuiting switches.
Note that, in addition to an arrangement in which the bus lines are provided respectively for the pixels R, G and, B, an arrangement in which the pixels of different colors exist in one group, such as
Moreover, (in the monochrome display or a color display,) it is possible to obtain the effect of the charge sharing by (i) an arrangement in which all the pixels are connected by one bus line, or (ii) an arrangement in which all the pixels R and G are connected by one bus line and all the pixels B are connected by another bus line.
Next,
Thus, it is possible to simplify the system by providing the short-circuiting switches 30a on the liquid crystal panel which is a display section of a display device.
Note that, in the arrangement of
Thus, the present embodiment is so arranged that the charge sharing is carried out between the source signal lines connected to pixels of the same color (R, G or B), without being influenced by the change in the number of output terminals. In this way, the difference between the waveforms of the transient voltages is eliminated. As a result, it is possible to further improve the reliability and realize the reduction of the electric power consumption.
That is, in one pixel group composed of pixels R, G and B, the polarities may be different from each other in the same horizontal period. For example, the pixels R and G in the first pixel group have positive polarities in a certain horizontal period, but the pixel B in the first pixel group has a negative polarity in the above horizontal period. For another example, the pixel R in the second pixel group has a negative polarity in a certain horizontal period, but the pixels G and B in the second pixel group have positive polarities in the above horizontal period. This can be realized easily by appropriately dephasing voltages applied to the source signal lines and the common electrode which are driven by alternating currents.
According to the arrangement illustrated in
The present invention is applicable to the liquid crystal display device and its driving device.
As described above, the driving device of the present invention drives a display section of a display device by applying, in each horizontal period, voltages to pixels in the display section through source signal lines charged to have source signal potentials according to display data signals supplied from an outputting circuit, the driving device precharging the source signal lines before causing the source signal lines to have the source signal potentials for the above each horizontal period, and the driving device comprises: a switching circuit which (a) separates the outputting circuit from the source signal lines and (b) short-circuits at least one source signal line whose source signal potential is positive in one horizontal period and at least one source signal line whose source signal potential is negative in the above one horizontal period, so that the short-circuited source signal lines are precharged.
According to the above arrangement, the precharging is carried out by short-circuiting (i) at least one source signal line whose source signal potential is positive and (ii) at least one source signal line whose source signal potential is negative in the same horizontal period.
In this way, the precharging is completed by short-circuiting the source signal lines with each other inside the display section. Therefore, the external memory capacitor is unnecessary, and the adjustment the external memory capacitor is obviously unnecessary. As a result, it is unnecessary to change or adjust the timing of the pulse width (high period) of the SELECT signal outputted from the controller. Therefore, it is unnecessary to renew the arrangement of the controller or produce the controller.
On this account, even when a newly designed display section (liquid crystal panel, etc.), which is different in the number of pixels and materials, is used, it is possible to realize a display device and a driving device which do not require the change in the arrangement of the controller.
Moreover, in addition to the above arrangement, the driving device of the present invention is so arranged that the source signal lines include R-signal lines, G-signal lines, and B-signal lines, which are connected to R-pixels, G-pixels, and B-pixels, respectively; and the switching circuit short-circuits an R-signal line with another R-signal line, a G-signal line with another G-signal line, and/or a B-signal line with another B-signal line, so that the short-circuited signal lines are precharged.
With the above arrangement, in the precharging, the short-circuiting is carried out between the source signal lines connected to pixels of the same color (R, G or B). In this way, the precharging of the source signal lines is carried out.
Therefore, in addition to the effect obtained by the above arrangement, it is also possible to carry out a desired precharging with a simple arrangement.
Moreover, in addition to the above arrangement, the driving device of the present invention includes a timing adjusting circuit which is able to adjust (i) a timing for separating the outputting circuit from the source signal lines and (ii) a timing for short-circuiting the source signal lines.
According to the above arrangement, it is possible to adjust (i) the timing of separating the outputting circuit from the source signal line and (ii) the timing of short-circuiting the source signal lines each other.
Therefore, in addition to the effect obtained by the above arrangement, it is also possible to easily adjust the timings of separating the above connection and short-circuiting, even when the design of the display section is changed.
Moreover, in addition to the above arrangement, the driving device of the present invention is so arranged that: each image is displayed by a pixel group including at least one pixel; through short-circuiting switches, each pixel in each pixel group is connected to at least one pixel in all the other pixel groups; and the short-circuiting switches are simultaneously turned on/off in the precharging.
With the above arrangement, each of the pixels in the pixel groups is connected to at least one pixel in the other pixel group so that the short-circuiting can be carried out.
Therefore, even when a certain pixel group is separated from the source signal lines, the other pixel groups do not lose their partner for the short-circuiting, and pixels in those other pixel groups are short-circuited with pixels in the other pixel groups without fail. Thus, even when the pixel groups are decreased from the existing source driver, it is possible to suppress generating display troubles, such as vertical lines, etc.
Moreover, in addition to the above arrangement, the driving device of the present invention is so arranged that pixels of the same color are connected with each other by the short-circuiting switches.
According to this arrangement, in addition to the effect obtained by the above arrangement, it is also possible to simplify the arrangement.
Moreover, in addition to the above arrangement, the driving device of the present invention is so arranged that, through bus lines and short-circuiting switches between the pixels and the bus lines, each pixel in each pixel group is connected to at least one pixel in all the other pixel groups.
According to this arrangement, in addition to the effect obtained by the above arrangement, it is also possible to simplify the arrangement.
Moreover, in addition to the above arrangement, the driving device of the present invention is so arranged that the switching circuit includes: short-circuiting switches each of which short-circuits an R-signal line with another R-signal line, a G-signal line with another G-signal line, or a B-signal line with another B-signal line, and separating switches each of which separates the outputting circuit from a source signal line so as to float the outputting circuit; each of the short-circuiting switches has one end connected to a source signal line and the other end connected to a common bus line shared by short-circuiting switches respectively connected to pixels of the same color; and precharging is performed by short-circuiting an R-signal line with another R-signal line, a G-signal line with another G-signal line, and/or a B-signal line with another B-signal line.
With the above arrangement, each of the pixels in the pixel groups is connected to at least one pixel in the other pixel group so that the short-circuiting can be carried out.
Therefore, even when a certain pixel group is separated from the source signal lines, the other pixel groups do not lose their partner for the short-circuiting, and pixels in those other pixel groups are short-circuited with pixels in the other pixel groups without fail. Thus, even when the pixel groups are decreased from the existing source driver, it is possible to suppress generating display troubles, such as vertical lines, etc.
Moreover, in addition to the above arrangement, the driving device of the present invention is so arranged that the short-circuiting switches and/or the separating switches are provided in the display section of the display device.
According to this arrangement, in addition to the effect obtained by the above arrangement, it is also possible to attempt to simplify the system.
Moreover, in addition to the above arrangement, the driving device of the present invention is so arranged that: each image is displayed by a pixel group including at least two pixels; in each pixel group, a polarity of at least one of the pixels is opposite a polarity of remaining pixels of the pixels in one horizontal period; and the pixels in each pixel group are connected with each other via the short-circuiting switches; and the short-circuiting switches are simultaneously turned on/off in the precharging.
With the above arrangement, each of the pixels in the pixel groups is connected to at least one pixel in the other pixel group so that the short-circuiting can be carried out.
Therefore, even when a certain pixel group is separated from the source signal lines, the other pixel groups do not lose their partner for the short-circuiting, and pixels in those other pixel groups are short-circuited with pixels in the other pixel groups without fail. Thus, even when the pixel groups are decreased from the existing source driver, it is possible to suppress generating display troubles, such as vertical lines, etc.
Moreover, the display device in accordance with the present invention is characterized by including the above-described driving device.
According to the above arrangement, the precharging is carried out by short-circuiting (i) at least one source signal line whose source signal potential is positive and (ii) at least one source signal line whose source signal potential is negative in the same horizontal period.
In this way, the precharging is completed by short-circuiting the source signal lines with each other inside the display section. Therefore, the external memory capacitor is unnecessary, and the adjustment the external memory capacitor is obviously unnecessary. As a result, it is unnecessary to change and adjust the timing of the pulse width (high period) of the SELECT signal outputted from the controller. Therefore, it is unnecessary to renew the arrangement of the controller or produce the controller.
On this account, even when a newly designed display section (liquid crystal panel, etc.), which is different in the number of pixels and materials, is used, it is possible to realize a display device and a driving device which do not require the change in the arrangement of the controller.
As described above, the driving device in accordance with the present invention includes the switching circuit which carries out the precharging of the source signal lines (i) by separating the outputting circuit from the source signal lines and (ii) by short-circuiting (a) at least one source signal line whose source signal potential is positive and (b) at least one source signal line whose source signal potential is negative in the same horizontal period. On this account, even when a newly designed display section (liquid crystal panel, etc.), which is different in the number of pixels and materials, is used, it is possible to realize a display device and a driving device which do not require the change of the arrangement of the controller.
The present invention is not limited to the embodiments above, but may be altered within the scope of the claims. An embodiment based on a proper combination of technical means disclosed in different embodiments is encompassed in the technical scope of the present invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2004-099939 | Mar 2004 | JP | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 5402255 | Nakanishi et al. | Mar 1995 | A |
| 5903234 | Kimura | May 1999 | A |
| 5959916 | Kumar | Sep 1999 | A |
| 6232948 | Tsuchi | May 2001 | B1 |
| 6366065 | Morita | Apr 2002 | B1 |
| 6396485 | Minami | May 2002 | B1 |
| 6529180 | Ito et al. | Mar 2003 | B1 |
| 6570418 | Uehara | May 2003 | B2 |
| 6642916 | Kodama et al. | Nov 2003 | B1 |
| 20020008687 | Tazuke | Jan 2002 | A1 |
| 20020050972 | Udo et al. | May 2002 | A1 |
| 20020105492 | Kosaka | Aug 2002 | A1 |
| 20030006997 | Ogawa et al. | Jan 2003 | A1 |
| 20030107541 | Naiki | Jun 2003 | A1 |
| 20030132903 | Ueda | Jul 2003 | A1 |
| 20040041763 | Kodama et al. | Mar 2004 | A1 |
| 20040041826 | Nakagawa et al. | Mar 2004 | A1 |
| Number | Date | Country |
|---|---|---|
| 10-11032 | Jan 1989 | JP |
| 04-358197 | Dec 1992 | JP |
| 07-199866 | Apr 1995 | JP |
| 07-199866 | Aug 1995 | JP |
| 08-076083 | Mar 1996 | JP |
| 09-212137 | Aug 1997 | JP |
| 09-243998 | Sep 1997 | JP |
| 10-115839 | May 1998 | JP |
| 10-133174 | May 1998 | JP |
| 10-301537 | Nov 1998 | JP |
| 10-301539 | Nov 1998 | JP |
| 11-30975 | Feb 1999 | JP |
| 11-264965 | Sep 1999 | JP |
| 11-326863 | Nov 1999 | JP |
| 2001-22328 | Jan 2001 | JP |
| 2001-134245 | May 2001 | JP |
| 2001-166731 | Jun 2001 | JP |
| 2001-188615 | Jul 2001 | JP |
| 2002-229525 | Aug 2002 | JP |
| 2003-131634 | May 2003 | JP |
| 2003-248466 | Sep 2003 | JP |
| 2004-93691 | Mar 2004 | JP |
| 10-2004-0078258 | Sep 2004 | KR |
| 416054 | Dec 2000 | TW |
| 594645 | Jun 2004 | TW |
| WO 9606421 | Feb 1996 | WO |
| Number | Date | Country | |
|---|---|---|---|
| 20050219195 A1 | Oct 2005 | US |
