Patent Grant
12236876
This application claims the benefit of priority to Japanese Patent Application No. 2022-182886 filed on Nov. 15, 2022, the entire contents of which are incorporated herein by reference.
An embodiment of the present invention relates to a display device and a driving method of the display device.
In recent years, self-luminous display devices have been mounted on televisions, smart phones, digital signage (electronic signboards, electronic advertising boards, and the like) and are becoming popular. The self-luminous display device includes, for example, a plurality of pixels and a driver for driving the plurality of pixels. Each of the plurality of pixels includes, for example, a plurality of transistors, a capacitive element, and a light emitting element. The light emitting element is, for example, a light emitting diode (Light Emitting Diode: LED), a micro light emitting diode (micro LED), or an organic electroluminescence (Electro Luminescence: EL) element. In a self-luminous display device, a driver supplies a voltage to each of a plurality of pixels, so that a current corresponding to the supplied voltage value flows to a light emitting element included in each of the plurality of pixels. Each of the light emitting elements emits light with a luminance corresponding to a current flowing through the light emitting element, and a pixel including the light emitting element can display an image with a gradation corresponding to the luminance.
For example, U.S. Patent Application Publication No. 2016/0284276 discloses a pixel including six transistors, one capacitive element, and one light emitting element, and a self-luminous display device including the pixel. For example, the self-luminous display device described in U.S. Patent Application Publication No. 2016/0284276 can control the light emission of a pixel using four driving circuits, and display an image in a display region.
A display device according to an embodiment of the present invention includes a first transistor configured to be controlled using a second control signal obtained by shifting a first control signal and electrically connected between an image data signal line and a first node, a second transistor electrically connected between the first node and a second node, a third transistor configured to be controlled using the first control signal and electrically connected between the second node and a gate electrode of the second transistor, a fourth transistor configured to be controlled using a fourth control signal obtained by shifting a third control signal and electrically connected between a driving power supply line and the second node, a fifth transistor configured to be controlled using the third control signal and electrically connected to the first node, a sixth transistor configured to be controlled using the third control signal and electrically connected to a light emitting element and a first electrode of the fifth transistor, and the light emitting element connected to the first electrode.
A driving method of a display device according to an embodiment of the present invention is a driving method of a self-luminous display device including a first transistor electrically connected at least between an image data signal line and a first node, a second transistor electrically connected between the first node and a second node, a third transistor electrically connected between the second node and a gate electrode of the second transistor, a fourth transistor electrically connected to the second node, a fifth transistor electrically connected to the first node, a sixth transistor connected to a light emitting element and a first electrode of the fifth transistor, and the light emitting element is electrically connected to the first electrode, wherein a first control signal and a second control signal are sequentially shifted and output, a third control signal and a fourth control signal are sequentially shifted and output, and the third transistor is configured to be controlled by using the first control signal, the first transistor is configured to be controlled using the second control signal, the fifth transistor and the sixth transistor are configured to be controlled using the third control signal, and the fourth transistor is configured to be controlled using the fourth control signal.
Hereinafter, embodiments of the present invention will be described with reference to the drawings and the like. However, the present invention can be implemented in many different aspects, and should not be construed as being limited to the description of the embodiments exemplified below. Further, in order to make the description clearer, the drawings may be schematically represented with respect to the width, thickness, shape, configuration and the like of each part as compared with the actual embodiment. However, the drawings are merely examples, and do not limit the interpretation of the present invention. It should be noted that the terms “first” and “second” for each element are convenient labels used to distinguish each element, and do not have any further meaning unless otherwise described.
Also, in the present specification, the expression “a includes A, B, or C,” “a includes any of A, B or C,” “a includes one selected from the group consisting of A, B and C,” and the like does not exclude cases where a includes a plurality of combinations of A to C unless otherwise specified. Furthermore, these expressions do not exclude the case where a includes other elements.
In a display device having a large number of driving circuits, a ratio of a region (for example, a frame region) in which the driving circuits are arranged in the display device is larger than a ratio of a display region in the display device. That is, the frame region becomes large, and it is difficult to reduce a size of the display device in the display device having the large number of driving circuits.
An object of an embodiment of the present invention is to provide a self-luminous display device capable of narrowing and miniaturizing a frame, and a method of driving a self-luminous display device using the self-luminous display device capable of narrowing and miniaturizing the frame, in view of such problems.
A self-luminous display device according to an embodiment of the present disclosure is, for example, a light emitting device using an EL element as a light emitting element.
[1-1. Overview of the Self-Luminous Display Device 10]
An overview of a self-luminous display device 10 according to a first embodiment will be described with reference to
As shown in
A plurality of pixels 180 in the display region 22 are arranged in a matrix. The pixel 180 is the smallest unit constituting a part of the image to be displayed in the display region 22. For example, each of the plurality of pixels 180 may correspond to a sub-pixel R, a sub-pixel G, and a sub-pixel B. One pixel may be formed by three sub-pixels. The arrangement of the pixels 180 is not limited. For example, the arrangement of the plurality of pixels 180 is a stripe arrangement. The arrangement of the self-luminous display device 10 may be a delta arrangement, a pentile arrangement, or the like.
The sub-pixel R, the sub-pixel G, and the sub-pixel B are configured to display images of different colors. For example, each of the sub-pixel R, the sub-pixel G, and the sub-pixel B may include a light emitting element including a light emitting layer that emits three primary colors of red, green, and blue. An arbitrary voltage or current is supplied to each of the three sub-pixels, and the self-luminous display device 10 can display an image.
A source driver circuit 110, a gate driver circuit 120, and a light emission control circuit 130 are provided in the peripheral region 24. Each of the source driver circuit 110, the gate driver circuit 120 and the light emission control circuit 130 is connected to a terminal part 150 using a connection wiring 341. The peripheral region 24 may be referred to as a frame region. The connection wiring 341 may be referred to as the connection wiring 341 alone, and a bundle of a plurality of connection wirings 341 may be referred to as the connection wiring 341.
The terminal part 150 and the FPC 160 electrically connected to the terminal part 150 are provided in the terminal region 26. The terminal region 26 is a region opposed to a region in which the display region 22 is provided with respect to the peripheral region 24 in a first direction D1.
The FPC 160 is connected to an external device (not shown) on an outer side of the self-luminous display device 10. The self-luminous display device is connected to the external device via the FPC 160 and the terminal part 150 connected to FPC. A control signal and a voltage are transmitted from the external device to the self-luminous display device 10 via the FPC 160 and the terminal part 150 connected to FPC. The self-luminous display device 10 drives each pixel 180 provided in the self-luminous display device 10 by using the received control signal and voltage from the external device. As a result, the self-luminous display device 10 can display an image in the display region 22.
For example, the IC tip 170 is provided on the FPC 160. The IC chip 170 supplies signals, voltages, and the like for driving the respective pixels 180 to the source driver circuit 110, the gate driver circuit 120, the light emission control circuit 130 and the pixel 180 (a pixel circuit 181) via the FPC 160, the terminal part 150 and the connecting wire 341.
Each of the source driver circuit 110, the gate driver circuit 120, the light emission control circuit 130 and the IC chip 170 may be referred to as a control circuit alone in the first embodiment, and a circuit group including some or all of the source driver circuit 110, the gate driver circuit 120, the light emission control circuit 130 and the IC chip 170 may be referred to as a control circuit in the first embodiment.
[1-2. Configuration of Source Driver Circuit 110]
Referring to
As shown in
For example, the selection circuit 112 is a switch 118 including the input terminal 114 and an output terminal 116. For example, an on-signal supplied from the IC chip 170 to the selection signal MUXR causes the input terminal 114 and the output terminal 116 to be conductive (connected), and the input terminal 114 and the output terminal 116 are cut off (disconnected) by an off-signal supplied from the IC chip 170 to the selection signal MUXR. The on-signal is a signal including a voltage that conducts between the input terminal 114 and the output terminal 116, and the off-signal is a signal including a voltage that blocks the input terminal 114 and the output terminal 116.
The on-signal may be high level (High, HI), the off-signal may be low level (Low, LO) in the present disclosure. Further, the on-signal may be low level (Low, LO), and the off-signal may be high level (High, HI) in the present disclosure.
[1-3. Configuration of Gate Driver Circuit 120]
An overview of the gate driver circuit 120 will be described with reference to
As shown in
For example, the shift register 121 is electrically connected to the shift register 122 and the shift register 122 is electrically connected to the shift register 123. For example, the shift register 121 is electrically connected to the scanning signal line 330 and supplies the scanning signal G (n) to the scanning signal line 330. Similar to the shift register 121, for example, the shift register 122 is electrically connected to the scanning signal line 331 and supplies the scanning signal G (n+1) to the scanning signal line 331, and the shift register 123 is electrically connected to the scanning signal line 332 and supplies the scanning signal G (n+2) to the scanning signal line 332. In addition, although not shown, a shift register of a next stage electrically connected to the shift register 123 is electrically connected to the scanning signal line 333, and a shift register of a next stage electrically connected to the shift register of the next stage is electrically connected to a scanning signal line different from the scanning signal line described above. The scanning signal G (n+1) includes the same pulse width as the scanning signal G (n), and is a signal in which the scanning signal G (n) is shifted. Similar to the scanning signal G (n+1), the scanning signal G (n+2) includes the same pulse width as the scanning signal G (n+1), and is a signal in which the scanning signal G (n+1) is shifted.
[1-4. Configuration of Light Emission Control Circuit 130]
An overview of the light emission control circuit 130 will be described with reference to
As shown in
For example, the shift register 131 is electrically connected to the shift register 132 and the shift register 132 is electrically connected to the shift register 133. For example, the shift register 131 is electrically connected to a light emission control signal line 334 and supplies the light emission control signal EM (n) to the light emission control signal line 334. Similar to the shift register 131, for example, the shift register 132 is electrically connected to the light emission control signal line 335, supplies the light emission control signal EM (n+1) to the light emission control signal line 335, and the shift register 133 is electrically connected to the light emission control signal line 336, and supplies the light emission control signal EM (n+2) to the light emission control signal line 336. The light emission control signal EM (n+1) includes the same pulse width as the light emission control signal EM (n). The light emission control signal EM (n+1) is a signal in which the light emission control signal EM (n) is shifted. Similarly, the light emission control signal EM(n+2) includes the same pulse width as the light emission control signal EM (n+1), and the light emission control signal EM (n+2) is a signal in which the light emission control signal EM (n+1) is shifted.
[1-5. Configuration of Pixel 180]
Referring to
The pixel circuit 181 is a circuit for driving the pixel 180. Pixel circuits of the sub-pixel R, the sub-pixel G, and the sub-pixel B included in the pixel 180 are the same as those of the pixel circuit 181, and differ in colors emitted by light emitting elements OLED. In the following explanation, a light emitting element OLED that emits red will be mainly described.
As shown in
The initialization voltage VINI is supplied to an initialization voltage line VM, the driving voltage VDDEL is supplied to a driving power line PVDD, and the reference voltage VSSEL is supplied to a reference voltage line PVSS. For example, each of the initialization voltage line VM, the driving power supply line PVDD and the reference voltage line PVSS may be electrically connected to the different connection line 341 or may be the different connection line 341. The initialization voltage VINI, the driving voltage VDDEL and the reference voltage VSSEL may be supplied from an external circuit to the plurality of pixels 180 (the pixel circuit 181) via the FPC 160, the terminal part 150, the initialization voltage line VM, the driving power supply line PVDD, and the reference voltage line PVSS. The initialization voltage VINI, the driving voltage VDDEL and the reference voltage VSSEL may be supplied from the IC chip 170 to the plurality of pixels 180 (pixel circuits 181) via the FPC 160, the terminal part 150, the initialization voltage line VM, the driving power supply line PVDD and the reference voltage line PVSS. The initialization voltage VINI is smaller than the driving voltage VDDEL. The initialization voltage VINI may be the same as the reference voltage VSSEL. The reference voltage VSSEL is smaller than the driving voltage VDDEL.
As shown in
For example, the first transistor T1 is a selection transistor. The first transistor T1 has a function of supplying the image data signal SL (m+1) to the second transistor T2.
For example, the second transistor T2 is a driving transistor. The second transistor T2 has a function for causing the light emitting element OLED to emit light by supplying a current to the light emitting element OLED using the inputted image data signal SL (m+1).
The third transistor T3 has a function of conducting a second node N2 and a gate electrode 622 of the second transistor T2 (and a second electrode 694 of the capacitor CS), supplying the driving voltage VDDEL to the gate electrode 622 of the second transistor T2, and resetting the gate electrode 622 of the second transistor T2. The driving voltage VDDEL is a voltage for driving the pixel and is also a reset voltage for resetting the pixel. The third transistor T3 has a function of accumulating charges corresponding to a threshold voltage Vth of the second transistor T2 in the gate electrode 622 of the second transistor T2 and the second electrode 694 of the capacitor CS.
The fourth transistor T4 controls connection and disconnection between the driving power supply line PVDD and the second transistor T2. That is, the fourth transistor T4 has a function of supplying the driving voltage VDDEL to the second transistor T2.
The fifth transistor T5 controls connection and disconnection between the second transistor T2 and the light emitting element OLED. In other words, the fifth transistor T5 has a function of controlling connection and disconnection between the second transistor T2 and the light emitting element OLED, and supplying a current to the light emitting element OLED to control light emission and non-light emission of the light emitting element OLED.
The sixth transistor T6 has a function for supplying a first electrode 654 of the fifth transistor T5, a second electrode 684 of the light emitting element OLED, and a first electrode 692 of the capacitor CS with an initialization voltage VINI, and initializing the first electrode 654 of the fifth transistor T5, the second electrode 684 of the light emitting element OLED, and the first electrode 692 of the capacitor CS.
For example, the capacitor CS has a function for holding a charge (first charge) corresponding to the threshold voltage Vth of the second transistor T2. The capacitor CS has a function for holding charges (second charges) corresponding to data voltages (for example, RDATA (n) (see
The light emitting element OLED has a diode characteristic and has a function for emitting light based on a current flowing through the light emitting element OLED (that is, a drain current of the second transistor T2).
The first transistor T1 includes a gate electrode 612, a first electrode 614, and a second electrode 616. The gate electrode 612 is electrically connected to the scanning signal line 331. The first electrode 614 is electrically connected to the image data signal line 321. The second electrode 616 is electrically connected to a first node N1, a first electrode 624 of the second transistor T2, and the second electrode 656 of the fifth transistor T5. The scanning signal G (n+1) is supplied to the scanning signal line 331. A conduction-state (on-state) and a non-conduction-state (off-state) are controlled by the scanning signal G (n+1) in the first transistor T1. The first transistor T1 becomes non-conductive in the case where the signal supplied to the scanning signal G (n+1) is low level (LO). The first transistor T1 becomes conductive in the case where the signal supplied to the scanning signal G (n+1) is high level (HI).
The second transistor T2 includes the gate electrode 622, the first electrode 624, and a second electrode 626. The gate electrode 622 is electrically connected to a first electrode 634 of the third transistor T3 and the first electrode 694 of the capacitor CS. The second electrode 626 is electrically connected to the second node N2, a second electrode 636 of the third transistor T3, and a first electrode 644 of the fourth transistor T4.
The third transistor T3 includes a gate electrode 632, the first electrode 634, and the second electrode 636. The gate electrode 632 is electrically connected to the scanning signal line 330. The scanning signal G (n) is supplied to the scanning signal line 330. The conduction-state (on-state) and the non-conduction-state (off-state) are controlled by the scanning signal G (n) in the third transistor T3. The third transistor T3 becomes non-conductive in the case where the signal supplied to the scanning signal G (n) is low level (LO). The third transistor T3 becomes conductive in the case where the signal supplied to the scanning signal G (n) is high level (HI).
The fourth transistor T4 includes a gate electrode 642, the first electrode 644, and a second electrode 646. The gate electrode 642 is electrically connected to the light emission control signal line 335. The second electrode 646 is electrically connected to the driving power supply line PVDD. The driving power supply line PVDD is supplied with a drive voltage VDDEL. The light emission control signal EM (n+1) is supplied to the light emission control signal line 335. The conduction-state (on-state) and the non-conduction-state (off-state) are controlled by the light emission control signal EM (n+1) in the fourth transistor T4. The fourth transistor T4 becomes non-conductive in the case where the signal supplied to the light emission control signal EM (n+1) is low level (LO) in the first embodiment, and the fourth transistor T4 becomes conductive in the case where the signal supplied to the light emission control signal EM (n+1) is high level (HI) in the first embodiment.
The fifth transistor T5 includes a gate electrode 652, the first electrode 654, and a second electrode 656. The gate electrode 652 is electrically connected to the light emission control signal line 334. The first electrode 654 is electrically connected to a second electrode 666 of the sixth transistor T6, the first electrode 692 of the capacitor CS, and the second electrode 684 of the light emitting element OLED. The light emission control signal EM (n) is supplied to the light emission control signal line 334. The conduction-state (on-state) and the non-conduction-state (off-state) are controlled by the light emission control signal EM (n) in the fifth transistor T5. The fifth transistor T5 becomes non-conductive in the case where the signal supplied to the light emission control signal EM (n) is low level (LO) in the first embodiment, and the fifth transistor T5 becomes conductive in the case where the signal supplied to the light emission control signal EM (n) is high level (HI) in the first embodiment.
The sixth transistor T6 includes a gate electrode 662, a first electrode 664, and the second electrode 666. The gate electrode 662 is electrically connected to the light emission control signal line 334. The first electrode 664 is electrically connected to the initialization voltage line VM. As described above, the light emission control signal EM (n) is supplied to the light emission control signal line 334, and the initialization voltage VINI is supplied to the initialization voltage line VM. Similar to the fifth transistor T5, in the sixth transistor T6, the conductive state (on-state) and the non-conductive state (off-state) are controlled by the light emission control signal EM (n). The sixth transistor T6 becomes conductive in the case where the signal supplied to the light emission control signal EM (n) is low level (LO) in the first embodiment, and the sixth transistor T6 becomes non-conductive in the case where the signal supplied to the light emission control signal EM (n) is high level (HI) in the first embodiment.
A first electrode 682 of the light emitting element OLED is electrically connected to the reference voltage line PVSS. As described above, the reference voltage line PVSS is supplied with the reference voltage VSSEL. For example, the first electrode 682 of the light emitting element OLED is a cathode electrode, and the second electrode 684 of the light emitting element OLED is, for example, an anode electrode.
For example, the conduction-state of the transistor in the self-luminous display device 10 is assumed to indicate a state in which the source electrode and the drain electrode of the transistor are conductive and the transistor is in an on-state (ON), and the non-conduction-state of the transistor in the self-luminous display device 10 is assumed to indicate a state in which the source electrode and the drain electrode of the transistor are non-conductive and the transistor is in an off-state (OFF). Note that in each transistor, the source electrode and the drain electrode may be interchanged depending on a voltage or a potential supplied to each electrode. In addition, it can be easily understood by people skilled in the art that even if the transistor is in the off-state, a small amount of current flows, such as a leakage current.
Each transistor shown in
[1-6. Driving Method of Self-Emitting Display Device 10]
Referring to
The driving methods of the self-luminous display device 10 include at least a reset period PRS, a sampling period PWR, and a light emission period PEM in one frame as shown in
Referring to
First, the data signal VDATA, the selection signal MUXR, the selection signal MUXG, and the selection signal MUXB will be described. The image data signal SL (m+1) including the data signal VDATA is input to each pixel 180 (pixel circuit 181) in accordance with each horizontal period. For example, the data signal VDATA is analog data including a voltage between a voltage VDH and a voltage VDL that is lower than the voltage VDH. A voltage VDM is the voltage between the voltage VDH and the voltage VDL that is lower than the voltage VDH. For example in the respective horizontal periods, the voltage RDATA is selected and supplied to the image data signal line using the selection signal MUXR, the voltage GDATA is selected, and supplied to the image data signal line using the selection signal MUXG, and the voltage BDATA is selected and supplied to the image data signal line using the selection signal MUXB. For example, the data signal VDATA is kept at the voltage VDM during periods in which no data is selected using the select signal MUXG.
Next, referring to
The gate electrode 622 of the second transistor T2 is supplied with the voltage RDATA (n−1). The scanning signal G (n) and the scanning signal G (n+1) are supplied with a low level (LO), and the first transistor T1 and the third transistor T3 are in an off-state. Further, the fourth transistor T4 is supplied with a high level (HI) from the light emission control signal EM (n+1), the fifth transistor T5 and the sixth transistor T6 are supplied with a high level (HI) from the light emission control signal EM (n), the fourth transistor T4 and the fifth transistor T5 are in an on-state, and the sixth transistor T6 is in an off-state.
The second transistor T2 is in an on-state based on the voltage RDATA (n−1). Consequently, the second transistor T2 can conduct a current IEL based on a gate/source voltage Vgs and a source/drain voltage Vds according to the voltage RDATA (n−1).
The fourth transistor T4, the second transistor T2, and the fifth transistor T5 are in an on-state, and the current IEL flows from the driving power supply line PVDD to the reference voltage line PVSS. Consequently, the current IEL flows to the light emitting element OLED, and the light emitting element OLED emits light.
Next, referring to
The scanning signal G (n) is supplied from a low level (LO) to a high level (HI), and the third transistor T3 is in an on-state in the reset period PRS. The light emission control signal EM (n) is supplied from a high level (HI) to a low level (LO), the fifth transistor T5 is in an off-state, and the sixth transistor T6 is in an on-state. Also, the fourth transistor T4 remains in an on-state and the first transistor T1 remains in an off-state.
The driving voltage VDDEL is supplied to the first node N1, the second node N2, each electrode electrically connected to the first node N1, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitor CS, based on the fifth transistor T5 and the third transistor T3 being in an on-state. In addition, the initialization voltage VINI is supplied to the first electrode 692 of the capacitor CS, the electrodes electrically connected to the first electrode 692, and the second electrode 684 of the light emitting element OLED based on the sixth transistor T6 being in an on-state. Consequently, the first node N1, the second node N2, each electrode electrically connected to the first node N1, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitor CS are reset, and the first electrode 692 of the capacitor CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light emitting element OLED are initialized. Further, since the fourth transistor T4 is in an off-state, the current does not flow from the driving power supply line PVDD toward the reference voltage line PVSS, and the current flows from the initialization voltage line VM toward the reference voltage line PVSS. The current flowing through the light emitting element OLED is generally a current based on a potential difference between the initialization voltage VINI and the reference voltage line PVSS. The potential difference between the initialization voltage VINI and the reference voltage line PVSS is small, and the light emitting element OLED does not emit light substantially.
Although a detailed illustration is omitted, the second transistor T2 is in an off-state if a potential difference between the gate electrode 622 of the second transistor T2 and the first electrode 624 (a potential difference between the gate electrode 622 and the first node N1) becomes the same as the threshold voltage Vth of the second transistor T2. Consequently, a difference between the drive voltage VDDEL and the threshold voltage Vth (VDDEL−Vth) is held by the first node N1 and each electrode electrically connected to the first node N1, and the drive voltage VDDEL is held by the second node N2, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitor CS.
Next, referring to
The light emission control signal EM (n+1) is supplied from a high level (HI) to a low level (LO), and the fourth transistor T4 is in an off-state, in a period between the reset period PRS and the sampling period PWR of the current frame. In addition, the third transistor T3 and the sixth transistor T6 remain in an on-state, and the first transistor T1 and the fifth transistor T5 remain in an off-state. In addition, the second transistor T2 is in an off-state because the potential difference between the gate electrode 622 of the second transistor T2 and the first electrode 624 (the potential difference between the gate electrode 622 and the first node N1) is the same as the threshold voltage Vth of the second transistor T2.
Further, for example, in the period between the reset period PRS and the sampling period PWR of the current frame, the difference (VDDEL−Vth) between the drive voltage VDDEL and the threshold voltage Vth corresponding to the reset voltage is held in the first node N1 and each electrode electrically connected to the first node N1, and the drive voltage VDDEL corresponding to the reset voltage is held in the second node N2, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitor CS. In the period between the reset period PRS and the sampling period PWR of the current frame, since the sixth transistor T6 remains in an on-state, the initialization voltage VINI is supplied to the first electrode 692 of the capacitor CS, the respective electrodes electrically connected to the first electrode 692, and the second electrode 684 of the light emitting element OLED. Further, since the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are in an off-state, no current flows from the driving power supply line PVDD to the reference voltage line PVSS. Similar to the reset period PRS, the current flows from the initialization voltage line VM toward the reference voltage line PVSS, and the light emitting element OLED does not substantially emit light.
The voltage RDATA (n) is selected based on the on-signal being supplied to the selection signal MUXR, in the period between the reset period PRS and the sampling period PWR of the current frame. Therefore, the image data signal SL (m+1) includes the voltage RDATA (n). Further, the image data signal SL (m+1) including the voltage RDATA (n) is supplied to the image data signal line 321. The image data signal line 321 holds the voltage RDATA (n) on the basis of an off-signal being supplied to the selection signal MUXR.
Next, referring to
The scanning signal G (n+1) is supplied from a low level (LO) to a high level (HI), and the first transistor T1 is in an on-state, in the sampling period PWR of the current frame. In addition, the third transistor T3 and the sixth transistor T6 remain in an on-state, and the fourth transistor T4 and the fifth transistor T5 remain in an off-state.
Based on the first transistor T1 being in an on-state, the voltage RDATA (n) is supplied to the first node N1 and the respective electrodes electrically connected to the first node N1. Further, if the voltage RDATA (n) is supplied to the first node N1, the voltage (VDDEL−Vth) held in the first node N1 gradually becomes the voltage RDATA (n). In addition, as the voltage of the first node N1 changes, the voltage between the gate/source of the second transistor T2 also changes, and the second transistor T2 is in an on-state. Consequently, the voltage RDATA (n) is supplied to the second node N2, the respective electrodes electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitor CS. In addition, since the sixth transistor T6 remains in an on-state, the initialization voltage VINI is supplied to the first electrode 692 of the capacitor CS, the respective electrodes electrically connected to the first electrode 692, and the second electrode 684 of the light emitting element OLED. Further, since the fourth transistor T4 and the fifth transistor T5 remain in an off-state, no current flows from the driving power supply line PVDD to the reference voltage line PVSS. Similar to the reset period PRS, the current flows from the initialization voltage line VM toward the reference voltage line PVSS, and the light emitting element OLED does not substantially emit light.
Although a detailed illustration is omitted, the second transistor T2 is in an off-state if the potential difference between the gate electrode 622 of the second transistor T2 and the first electrode 624 (the potential difference between the gate electrode 622 and the first node N1) becomes the same as the threshold voltage Vth of the second transistor T2. For example, the voltage RDATA (n) is supplied to the first node N1 and each electrode electrically connected to the first node N1. For example, the second transistor T2 is in an off-state if the voltage written to the second node N2 (the respective electrodes electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitor CS) becomes the voltage RDATA (n)+the threshold voltage Vth (RDATA (n)+Vth). At this time, the second node N2, the electrodes electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitor CS hold the voltage RDATA (n)+the threshold voltage Vth (RDATA (n)+Vth), and the first node N1 and the electrodes electrically connected to the first node N1 hold the voltage RDATA (n). Further, as described above, the first electrode 692 of the capacitor CS, the electrodes electrically connected to the first electrode 692, and the second electrode 684 of the light emitting element OLED are supplied with the initialization voltage VINI and hold the initialization voltage VINI. Therefore, a difference between the voltage held in the second electrode 694 of the capacitor CS and the voltage held in the first electrode 692 of the capacitor CS (a potential difference between the electrodes of the capacitor CS) becomes the voltage VDDEL+the threshold voltage Vth+the initialization voltage VINI (VDDEL+Vth+VINI). In this case, the capacitor CS holds data (information) of the threshold voltage Vth of the second transistor T2. As described above, the sampling period PWR of the current frame is a period in which the voltage corresponding to the image data displayed by the pixel 180 (the pixel circuit 181) is written to the pixel 180 (the pixel circuit 181), and is also a period (threshold correction period) in which the charge corresponding to the threshold voltage Vth of the second transistor T2 is held and the threshold value of the second transistor T2 is corrected.
Next, referring to
The scanning signal G (n) is supplied from a high level (HI) to a low level (LO), and the third transistor T3 is in an off-state, in a period after the sampling period PWR of the current frame. In addition, the first transistor T1 and the sixth transistor T6 remain in an on-state, and the second transistor T2, the fourth transistor T4, and the fifth transistor T5 remain in an off-state.
At this time, the second node N2, each electrode electrically connected to the second node N2, the gate electrode 622 of the second transistor T2, and the second electrode 694 of the capacitor CS hold the voltage RDATA (n)+the threshold voltage Vth (RDATA (n)+Vth), and the first node N1 and each electrode electrically connected to the first node N1 holds the voltage RDATA (n), and each electrode electrically connected to the first electrode 692 of the capacitor CS, each electrode electrically connected to the first electrode 692, and the second electrode 684 of the light emitting element OLED hold the initialization voltage VINI.
At this time, a high level (HI) is supplied to the scanning signal G (n+1), the first transistor T1 is in an on-state, the voltage RDATA (n) is supplied to the first electrode 614 and the second electrode 616 of the first transistor T1, and the first electrode 614 has the same potential as the second electrode 616. That is, since the source electrode and the drain electrode of the first transistor T1 have the same potential, no current flows through the first transistor T1. Further, since the second transistor T2, the fourth transistor T4, and the fifth transistor T5 are in an off-state, no current flows from the driving power supply line PVDD to the reference voltage line PVSS. Similar to the reset period PRS and the sampling period PWR, the current flows from the initialization voltage line VM toward the reference voltage line PVSS, and the light emitting element OLED does not substantially emit light.
Next, as shown in
Next, as shown in
For example, if the second transistor T2 is in an on-state, current flows from the second node N2 toward the first electrode 692 of the capacitive element CS, the respective electrodes electrically connected to the first electrode 692, and the second electrode 684 of the light emitting element OLED. Consequently, the voltages of the first electrode 692 of the capacitive element CS, the electrodes electrically connected to the first electrode 692, and the second electrode 684 of the light emitting element OLED increase. In addition, a current based on a potential difference between the second electrode 684 of the light emitting element OLED and the first electrode 682 flows to the light emitting element OLED, and the light emitting element OLED emits light. In addition, the potential difference between the second electrode 684 and the first electrode 682 of the light emitting element OLED may be low enough that the light emitting element OLED does not substantially emit light.
Next, referring to
As shown in
The self-luminous display device 10 is driven as described above, and image data (for example, voltage RDATA (n)+threshold voltage Vth+voltage β (RDARA (n)+Vth+β) corresponding to each pixel 180 (pixel circuit 181) is supplied to each pixel 180 (pixel circuit 181), a current (for example, the current IELA) corresponding to the image data is supplied to the light emitting element OLED included in each pixel 180 (pixel circuit 181), and each light emitting element OLED emits light with a brightness corresponding to the image data. As a result, the self-luminous display device 10 can display a desired image.
For example, in the conventional driving methods of the self-luminous display device different from the present invention, four circuits corresponding to the first transistor T1 and the sixth transistor T6, the third transistor T3, the fourth transistor T4, and a control circuit (for example, the gate driver and the light emission control circuit) for driving the fifth transistor T5 are required. Therefore, in the self-luminous display device which does not use a shift pulse similar to that of the present invention, the frame region becomes wider (larger).
On the other hand, in the self-luminous display device 10 of the present invention, the gate driver circuit 120 and the light emission control circuit 130 are one system, and the self-luminous display device 10 can drive the transistors included in the pixel 180 (the pixel circuit 181) using the shift pulse. By using the self-luminous display device 10, the number of control circuits for driving the transistors included in the pixel 180 (the pixel circuit 181) can be reduced. By using the self-luminous display device 10, a display device having a narrow frame region can be provided. Further, by using the self-luminous display device 10, since signals to be supplied to the gate electrode of the fourth transistor T4 and the gate electrode of the sixth transistor T6 can be shared, it is possible to simplify a wiring structure such as wiring routing connecting the transistors from a configuration of the conventional self-luminous display device which differs from the present invention. As a result, parasitic capacitances and resistances associated with the wiring routing can be reduced. Therefore, power associated with charging of the parasitic capacitance and the resistor can be reduced. Therefore, by using the self-luminous display device 10, it is possible to suppress power consumption of the display device more than the configuration of the conventional self-luminous display device different from the present invention.
Next, referring to
The data signal VDATA, the selection signal MUXR, the selection signal MUXG, and the selection signal MUXB are the same as the description with reference to
A driving method of the pixel 180 (pixel circuit 181) in the emission period PEM of the previous frame of the current frame (K−1st FRAME) is the same as the driving method described with respect to
Next, a driving method of the pixel 180 (the pixel circuit 181) in the black period PBWR, which is executed following the emission period PEM of the previous frame of the current frame (K−1st RAME), will be described. The black period PBWR of the current frame is a period overlapping a part of the one horizontal period N−1st HP to a part of the one horizontal period N+3rd HP.
The scanning signal G (n), the scanning signal G (n+1) and the light emission control signal EM (n) are supplied with a low level (LO) in the black period PBWR. The first transistor T1, the second transistor T2, the third transistor T3, and the fifth transistor T5 are in an off-state, and the sixth transistor T6 is in an on-state. The light emission control signal EM (n+1) is supplied with a high level (HI) or a low level (LO). Whether the fourth transistor T4 is in an on-state or an off-state, the second transistor T2 is in an off-state, and the current does not flow from the driving power supply line PVDD toward the reference voltage line PVSS.
Since the sixth transistor T6 is in an on-state, the initialization voltage VINI is supplied from the initialization voltage line VM to the first electrode 692 of the capacitor CS, the respective electrodes electrically connected to the first electrode 692, and the second electrode 684 of the light emitting element OLED. Thus, a current IRB flows from the initialization voltage line VM toward the reference voltage line PVSS. Since the current IRB flowing through the light emitting element OLED is a current for displaying black based on the initialization voltage VINI, the light emitting element OLED does not emit light substantially. Thus, the pixel 180 displays black. A voltage supplied to the initialization voltage line VM (a voltage supplied to the second electrode 684 of the light emitting element OLED) is not limited to the initialization voltage VINI, in the black period PBWR. For example, the voltage supplied to the initialization voltage line VM may be the reference voltage VSSEL, and may be a voltage adjusted according to the electric properties of the transistors in the respective pixels 180. The voltage supplied to the initialization voltage line VM can be appropriately adjusted as long as the light emitting element OLED is a voltage that does not substantially emit light or does not emit light.
A driving method of the pixel 180 (pixel circuit 181) in the light emission period PEM of the current frame (Kth FRAME) is the same as the driving method of the pixel 180 (pixel circuit 181) in the light emission period PEM of the previous frame of the current frame (K−1st FRAME). Therefore, description thereof will be omitted. In addition, voltages of the first node N1 of the light emitting period PEM, the first electrode 654 of the fifth transistor T5, and the second electrode 684 of the light emitting element OLED in the current frame (Kth FRAME) are voltages between the voltage VDL and the voltage VDH.
For example, a luminous transition speed after writing of image data (for example, a sampling period) is the same as a luminous transition speed after the period for displaying black in general, in a period for displaying black in a self-luminous display device. For example, a voltage capable of displaying black on the anode electrode is appropriately set in the period for displaying black. As a result, flicker can be adjusted in the self-luminous display device.
The initialization voltage VINI is supplied from the initialization voltage line VM to the second electrode 684 (anode electrode) of the light emitting element OLED, in the black period PBWR of the self-luminous display device 10 according to the first embodiment, so that the self-luminous display device 10 can display black. As a result, the self-luminous display device 10 can adjust flicker.
Further, since data for displaying black is supplied from the image data signal line to the first node N1 via the first transistor T1 in the conventional self-luminous display device, the image data signal line needs to supply image data corresponding to the image and data for displaying black. The image data corresponding to the image changes according to the luminance of the light emitting element. Therefore, in the conventional self-luminous display device, it is necessary to change an amount of change (for example, an amount of change in voltage) from the image data corresponding to the image to the data for displaying black in accordance with the luminance of the light emitting element. Since the image data signal line is supplied with the image data corresponding to the image and the data for displaying black, depending on the amount of change in the voltage, the change in brightness due to a coupling between the image data signal line and the gate electrode of the second transistor T2 may become a problem.
On the other hand, the initialization voltage VINI, which is a fixed voltage, is supplied from the initialization voltage line VM to the second electrode 684 of the light emitting element OLED in the black period PBWR of the self-luminous display device 10, so that the self-luminous display device 10 can display black. That is, data for displaying black does not need to be supplied from the image data signal line 321 to the first node N1 via the first transistor T1 in the black period PBWR of the self-luminous display device 10. Consequently, there is no change in brightness due to coupling between the image-data-signal line 321 and the gate-electrode 622 of the second transistor T2, in the self-luminous display device 10. Therefore, the self-luminous display device 10 can display an image in which flicker is suppressed more than the conventional self-luminous display device.
In the black period PBWR of the self-luminous display device 10, data for displaying black does not need to be supplied from the image data signal line 321 to the first node N1 via the first transistor T1. Therefore, in the black period PBWR of the self-luminous display device 10, the first transistor T1 and the third transistor T3 can be in an off-state. That is, the gate driver circuit 120 does not need to be driven in the black period PBWR of the self-luminous display device 10. Thus, for example, the control signal supplied to the gate driver circuit 120 is fixed to a low level (LO), the power supply voltage supplied to the gate driver circuit 120 is fixed to 0 V or GND (ground, earth, and the like), and the output (scanning signal G (n), scanning signal G (n+1), and the like) from the gate driver circuit 120 is supplied with a low level (LO). Therefore, by using the driving method of the self-luminous display device 10, the driving method of the display device can be simplified, and the power consumption of the display device can be reduced.
Referring to
An overview of the pixel circuit 182 will be described with reference to
The pixel circuit 182 is a circuit for driving the pixel 180 similar to the pixel circuit 181. As described above, the pixel circuit 182 differs from the pixel circuit 181 in that the fourth transistor T4 and the fifth transistor T5 are p-channel field effect transistors, and the transistor of the sixth transistor T6 is n-channel field effect transistor.
Referring to
Since the fourth transistor T4 and the fifth transistor T5 are p-channel field effect transistors and the transistor of the sixth transistor T6 is an n-channel field effect transistor in the pixel circuit 182 according to the second embodiment, the light emission control signal EM (n) and the light emission control signal EM (n+1) are inverted with respect to the pixel 180 (pixel circuit 181) according to the first embodiment.
The driving method of the self-luminous display device according to the second embodiment shown in
Further, the light emission control signal EM (n) may be supplied with a high level (HIL) lower than a high level (HI) in the self-luminous display device according to the second embodiment.
For example, since the fifth transistor T5 is a p-channel field effect transistor in the light emitting period PEM of the current frame (Kth FRAME), a high level (HI) to a low level (LO) is supplied to the light emission control signal EM (n). A high level (HI) to a low level (LO) is supplied to the light emission control signal EM (n) in the pixel circuit 182. Therefore, since a low level (LO) to a high level (HI) are supplied to the light emission control signal EM (n), it is possible to suppress an increase in a voltage of the anode electrode due to the coupling between the light emission control signal line 334 and the second electrode 684 (anode electrode) of the light emitting element OLED. If the voltage of the anode electrode increases, a larger current flows through the light emitting element OLED than the case where the pixel 180 displays black, and thus the pixel 180 is less likely to display black. On the other hand, since the self-luminous display device 10 (pixel 180 (pixel circuit 182)) according to the second embodiment can suppress an increase in the voltage of the anode electrode, it is possible to increase a margin at the time of displaying black.
Since the fourth transistor T4 is a p-channel field effect transistor in the self-luminous display device 10 (the pixel 180 (the pixel circuit 182)) according to the second embodiment, the high voltage of the light emission control signal EM(n) can be reduced from a high level (HI) to a high level (HIL) lower than a high level (HI). As a result, since the voltage supplied to the gate electrode 642 of the fourth transistor T4 can be reduced, the power consumption of the self-luminous display device 10 can be reduced.
Referring to
In a description of the third embodiment, a direction from a substrate toward an oxide semiconductor layer is referred to as “upper” or “above”, and a direction from the oxide semiconductor layer toward the substrate is referred to as “lower” or “below”. In the description of the third embodiment, for example, the substrate and the oxide semiconductor layer may be arranged upside down. An expression “oxide semiconductor layer on the substrate” merely describes the vertical relationship between an arrangement of the substrate and the oxide semiconductor layer, and other members may be arranged between the substrate and the oxide semiconductor layer. The expression “above” or “below” means a stacking order in a structure in which a plurality of layers are stacked. For example, in the case of expressing the pixel electrode above the transistor, a positional relationship between the transistor and the pixel electrode may be such that the positional relationship between the transistor and the pixel electrode does not overlap in plan view. On the other hand, the expression “pixel electrode vertically above the transistor” means a positional relationship in which the positional relationship between the transistor and the pixel electrode overlaps in a plan view.
[3-1. Configuration of Semiconductor Device 40]
As shown in
The gate electrode 505 is provided on the substrate 500. The gate insulating layer 510 and the gate insulating layer 520 are provided on the substrate 500 and the gate electrode 505. The metal oxide layer 530 is provided on the gate insulating layer 520. The metal oxide layer 530 is in contact with the gate insulating layer 520. The oxide semiconductor layer 540 is provided on the metal oxide layer 530. The oxide semiconductor layer 540 is in contact with the metal oxide layer 530. A surface of a main surface of the oxide semiconductor layer 540 in contact with the metal oxide layer 530 is referred to as a lower surface 542. An end portion of the metal oxide layer 530 and an end portion of the oxide semiconductor layer 540 substantially coincide with each other.
A semiconductor layer or an oxide semiconductor layer in the third embodiment is not provided between the metal oxide layer 530 and the substrate 500.
The metal oxide layer 530 is in contact with the gate insulating layer 520, and the oxide semiconductor layer 540 is in contact with the metal oxide layer 530, in the third embodiment. However, the configuration according to the third embodiment is not limited to the configuration exemplified here. For example, other layers may be provided between the gate insulating layer 520 and the metal oxide layer 530, and other layers may be provided between the metal oxide layer 530 and the oxide semiconductor layer 540.
In
The gate electrode 560 faces the oxide semiconductor layer 540. The gate insulating layer 550 is provided between the oxide semiconductor layer 540 and the gate electrode 560. The gate insulating layer 550 is in contact with the oxide semiconductor layer 540. A surface of the main surface of the oxide semiconductor layer 540 in contact with the gate insulating layer 550 is referred to as an upper surface 541. A surface between the upper surface 541 and the lower surface 542 is referred to as a side surface 543. The insulating layers 570 and 580 are provided on the gate insulating layer 550 and the gate electrode 560. Openings 571 and 573 that reach the oxide semiconductor layer 540 are provided in the insulating layers 570 and 580. The source electrode 201 is provided inside the opening 571. The source electrode 201 is in contact with the oxide semiconductor layer 540 at a bottom portion of the opening 571. The drain electrode 203 is provided inside the opening 573. The drain electrode 203 is in contact with the oxide semiconductor layer 540 at a bottom portion of the opening 573.
The gate electrode 505 has a function as a bottom gate of the semiconductor device 40 and a function as a light shielding film for the oxide semiconductor layer 540. The gate insulating layer 510 functions as a barrier film that shields impurities that diffuse from the substrate 500 toward the oxide semiconductor layer 540. The gate insulating layers 510 and 520 each have a function as a gate insulating layer with respect to the bottom gate. The metal oxide layer 530 is a layer containing a metal oxide containing aluminum as a main component, and has a function as a gas barrier film for shielding a gas such as oxygen or hydrogen.
The oxide semiconductor layer 540 is divided into a source region S, a drain region D, and a channel region CH. The channel region CH is a region of the oxide semiconductor layer 540 vertically below the gate electrode 560. The source region S is a region of the oxide semiconductor layer 540 that does not overlap the gate electrode 560 and is closer to the source electrode 201 than the channel region CH. The drain region D is a region of the oxide semiconductor layer 540 that does not overlap the gate electrode 560 and is closer to the drain electrode 203 than the channel region CH. The oxide semiconductor layer 540 in the channel region CH has physical properties as a semiconductor. The oxide semiconductor layer 540 in the source region S and the drain region D has physical properties as a conductor.
The gate electrode 560 functions as a light shielding film for the top gate and the oxide semiconductor layer 540 of the semiconductor device 40. The gate insulating layer 550 has a function as a gate insulating layer with respect to the top gate, and has a function of releasing oxygen by a heat treatment in a manufacturing process. The insulating layers 570 and 580 have a function of insulating the gate electrode 560 and the source/drain electrode 200 and reducing parasitic capacitance therebetween. An operation of the semiconductor device 40 is mainly controlled by a voltage supplied to the gate electrode 560. An auxiliary voltage is supplied to the gate electrode 505. However, in the case where the gate electrode 505 is simply used as a light shielding film, a specific voltage may not be supplied to the gate electrode 505 and may be floating. That is, the gate electrode 505 may be simply referred to as a “light shielding film”.
In the third embodiment, although a configuration in which a dual-gate transistor in which a gate electrode is provided both above and below the oxide semiconductor layer is used as the semiconductor device 40 is exemplified, the configuration is not limited to this configuration. For example, as the semiconductor device 40, a bottom-gate transistor in which the gate electrode is provided only below the oxide semiconductor layer, or a top-gate transistor in which the gate electrode is provided only above the oxide semiconductor layer may be used. The above configuration is merely an embodiment, and the present invention is not limited to the above configuration.
As shown in
The third embodiment exemplifies a configuration in which all of the lower surface 542 of the oxide semiconductor layer 540 is covered with the metal oxide layer 530. However, the configuration according to the third embodiment is not limited to the configuration shown here. For example, a part of the lower surface 542 of the oxide semiconductor layer 540 may not be in contact with the metal oxide layer 530. For example, all of the lower surface 542 of the oxide semiconductor layer 540 in the channel region CH may be covered with the metal oxide layer 530, and all or a part of the lower surface 542 of the oxide semiconductor layer 540 in the source region S and the drain region D may not be covered with the metal oxide layer 530. That is, all or a part of the lower surface 542 of the oxide semiconductor layer 540 in the source region S and the drain region D may not be in contact with the metal oxide layer 530. However, in the above configuration, a part of the lower surface 542 of the oxide semiconductor layer 540 in the channel region CH may not be covered with the metal oxide layer 530, and another part of the lower surface 542 may be in contact with the metal oxide layer 530.
In the third embodiment, although the gate insulating layer 550 is formed over the entire surface and the openings 571 and 573 are provided in the gate insulating layer 550, the configuration is not limited to this configuration. The gate insulating layer 550 may be patterned in a shape different from the shapes in which the openings 571 and 573 are provided. For example, the gate insulating layer 550 may be patterned so as to expose all or a part of the oxide semiconductor layer 540 in the source region S and the drain region D. That is, the gate insulating layer 550 in the source region S and the drain region D may be removed, and the oxide semiconductor layer 540 and the insulating layer 570 may be in contact with each other in these regions.
In
[3-2. Material of Each Member of the Semiconductor Device 40]
As the substrate 500, a rigid substrate having translucency, such as a glass substrate, a quartz substrate, and a sapphire substrate, is used. In the case where the substrate 500 needs to have flexibility, a substrate containing a resin such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluororesin substrate is used as the substrate 500. In the case where a substrate containing a resin is used as the substrate 500, impurities may be introduced into the resin in order to improve heat resistance of the substrate 500. In particular, in the case where the semiconductor device 40 is used in a top emission type self-luminous display device, since the substrate 500 does not need to be transparent, impurities that deteriorate transparency of the substrate 500 may be used.
A general metal material is used as the gate electrode 505, the gate electrode 560, and the source/drain electrode 200. For example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof are used as the members. The above materials may be used as the gate electrode 505, the gate electrode 560, and the source/drain electrode 200 in a single layer or in a stacked layer.
A general insulating material is used as the gate insulating layers 510 and 520 and the insulating layers 570 and 580. For example, inorganic insulating layers such as silicon oxide (SiOx), silicon oxynitride (SiOxNy), silicon nitride (SiNx), silicon nitride oxide (SiNxOy), aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), aluminum nitride oxide (AlNxOy), and aluminum nitride (AlNx) are used as the insulating layers.
As the gate insulating layer 550, an insulating layer containing oxygen among the insulating layers described above is used. For example, an inorganic insulating layer such as silicon oxide (SiOx), silicon oxynitride (SiOxNy), aluminum oxide (AlOx), or aluminum oxynitride (AlOxNy) is used as the gate insulating layer 550.
As the gate insulating layer 520, an insulating layer having a function of releasing oxygen by a heat treatment is used. The temperature of the heat treatment in which the gate insulating layer 520 releases oxygen is, for example, 600° C. or less, 500° C. or less, 450° C. or less, or 400° C. or less. That is, the gate insulating layer 520 emits oxygen at a heat treatment temperature performed in the manufacturing process of the semiconductor device 40 in a case where the glass substrate is used as the substrate 500, for example.
As the gate insulating layer 550, an insulating layer with few defects is used. For example, in the case where a composition ratio of oxygen in the gate insulating layer 550 is compared with a composition ratio of oxygen in an insulating layer having the same composition as that of the gate insulating layer 550 (hereinafter referred to as “other insulating layer”), the composition ratio of oxygen in the gate insulating layer 550 is closer to a stoichiometric ratio with respect to the insulating layer than the composition ratio of oxygen in the other insulating layer. Specifically, in the case where silicon oxide (SiOx) is used for each of the gate insulating layer 550 and the insulating layer 580, a composition ratio of oxygen in the silicon oxide used as the gate insulating layer 550 is closer to a stoichiometric ratio of silicon oxide than a composition ratio of oxygen in the silicon oxide used as the insulating layer 580. For example, as the gate insulating layer 550, a layer in which no defects are observed when evaluated by electron spin resonance (ESR) may be used.
SiOxNy and AlOxNy described above are silicon-containing and aluminum-containing compounds that contain a smaller proportion (x>y) of nitrogen (N) than oxygen (O). SiNxOy and AlNxOy are silicon-containing and aluminum-containing compounds that contain a lower proportion of oxygen than nitrogen (x>y).
As the metal oxide layer 530 and a metal oxide layer 590 used in the manufacturing process as described later, a metal oxide layer containing aluminum as a main component is used. For example, as the metal oxide layer 530 (or the metal oxide layer 590), an inorganic insulating layer such as aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), aluminum nitride oxide (AlNxOy), or aluminum nitride (AlNx) is used. The “metal oxide layer containing aluminum as a main component” means that a ratio of aluminum contained in the metal oxide layer 530 (or the metal oxide layer 590) is 1% or more of the total amount of the metal oxide layer 530 (or the metal oxide layer 590). The ratio of aluminum contained in the metal oxide layer 530 (or the metal oxide layer 590) may be 5% or more and 70% or less, 10% or more and 60% or less, or 30% or more and 50% or less of the entire metal oxide layer 530. The ratio may be a mass ratio or a weight ratio.
As the oxide semiconductor layer 540, a metal oxide having characteristics of a semiconductor can be used. For example, as the oxide semiconductor layer 540, an oxide semiconductor containing two or more metals containing indium (In) is used. A ratio of indium to the entire oxide semiconductor layer 540 is 50% or more. In addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconia (Zr), and lanthanoids are used as the oxide semiconductor layer 540. As the oxide semiconductor layer 540, an element other than the elements described above may be used.
The oxide semiconductor layer 540 may be amorphous or crystalline. The oxide semiconductor layer 540 may be a mixed phase of amorphous and crystal. As described below, in the oxide semiconductor layer 540 in which the ratio of indium is 50% or more, oxygen vacancies are likely to be formed. A crystalline oxide semiconductor is less likely to form oxygen vacancies than an amorphous oxide semiconductor. Therefore, the oxide semiconductor layer 540 as described above is preferably crystalline.
[3-3. Problems Newly Recognized in the Process Leading to the Present Invention]
Since the ratio of indium in the oxide semiconductor layer 540 is 50% or more, the semiconductor device 40 with high mobility can be realized. On the other hand, in such an oxide semiconductor layer 540, oxygen contained in the oxide semiconductor layer 540 is easily reduced, and oxygen vacancies are easily formed in the oxide semiconductor layer 540.
In the semiconductor device 40, in a heat treatment process of the manufacturing process, hydrogen is released from a layer (for example, the gate insulating layers 510 and 520) provided closer to the substrate 500 than the oxide semiconductor layer 540, and the hydrogen reaches the oxide semiconductor layer 540, so that oxygen vacancies are generated in the oxide semiconductor layer 540. This generation of the oxygen vacancy is more pronounced as a pattern size of the oxide semiconductor layer 540 is larger. In order to suppress the generation of such oxygen vacancies, it is necessary to suppress the hydrogen from reaching the lower surface 542 of the oxide semiconductor layer 540. The above is the first issue.
Apart from the problems described above, there is the following second problem. The upper surface 541 of the oxide semiconductor layer 540 is affected by a process (for example, a patterning process or an etching process) after the oxide semiconductor layer 540 is formed. On the other hand, the lower surface 542 of the oxide semiconductor layer 540 (the surface of the oxide semiconductor layer 540 on the substrate 500 side) is not affected as described above.
Therefore, oxygen vacancies formed on the upper surface 541 of the oxide semiconductor layer 540 are larger than oxygen vacancies formed on the lower surface 542 of the oxide semiconductor layer 540. That is, the oxygen vacancies in the oxide semiconductor layer 540 are not uniformly present in a thickness direction of the oxide semiconductor layer 540, but are present in a non-uniform distribution in the thickness direction of the oxide semiconductor layer 540. Specifically, the oxygen vacancies in the oxide semiconductor layer 540 are smaller toward the lower surface 542 of the oxide semiconductor layer 540 and larger toward the upper surface 541 of the oxide semiconductor layer 540.
In the case where an oxygen supply process is uniformly performed on the oxide semiconductor layer 540 having the oxygen vacancy distribution as described above, when oxygen is supplied in an amount necessary for repairing the oxygen vacancy formed on the upper surface 541 side of the oxide semiconductor layer 540, oxygen is excessively supplied to the lower surface 542 side of the oxide semiconductor layer 540. As a result, on the lower surface 542 side, a defect level different from the oxygen vacancy is formed due to the excess oxygen, and a phenomenon such as a characteristic variation in the reliability test or a decrease in a field effect mobility occurs. Therefore, in order to suppress such a phenomenon, it is necessary to supply oxygen to the upper surface 541 side of the oxide semiconductor layer 540 while suppressing the supply of oxygen to the lower surface 542 side of the oxide semiconductor layer 540.
The problem described above is a newly recognized problem in the process leading to the present invention, and is not a problem that has been conventionally recognized. In the conventional configuration and manufacturing method, there is a relationship of a trade-off between the initial characteristics and the reliability test, in which the characteristic variation due to the reliability test occurs even if the initial characteristics of the semiconductor device are improved by the oxygen supply process to the oxide semiconductor layer. However, with the configuration according to the third embodiment, the problem described above is solved, and good initial characteristics and reliability test results of the semiconductor device 40 can be obtained.
[3-4. Manufacturing Method of Semiconductor Device 40]
A method of manufacturing the semiconductor device 40 will be described with reference to
As shown in
By using silicon nitride as the gate insulating layer 510, the gate insulating layer 510 can block impurities that diffuse from the substrate 500 side toward the oxide semiconductor layer 540, for example. The silicon oxide used as the gate insulating layer 520 is a physical silicon oxide that releases oxygen by a heat treatment.
As shown in
A thickness of the metal oxide layer 530 is, for example, 1 nm or more and 100 nm or less, 1 nm or more and 50 nm or less, 1 nm or more and 30 nm or less, or 1 nm or more and 10 nm or less. In the third embodiment, aluminum oxide is used as the metal oxide layer 530. Aluminum oxide has a high barrier property against gas. In the third embodiment, the aluminum oxide used as the metal oxide layer 530 blocks hydrogen and oxygen released from the gate insulating layer 520, and suppresses the released hydrogen and oxygen from reaching the oxide semiconductor layer 540.
A thickness of the oxide semiconductor layer 540 is, for example, 10 nm or more and 100 nm or less, 15 nm or more and 70 nm or less, or 20 nm or more and 40 nm or less. The oxide-semiconductor layers 540 prior to a heat treatment (OS annealing) described later are amorphous.
In the case where the oxide semiconductor layer 540 is crystallized by OS annealing to be described later, the oxide semiconductor layer 540 after a film formation and prior to OS annealing is preferably amorphous (with few crystalline components of the oxide semiconductor). That is, a film formation condition of the oxide semiconductor layer 540 is preferably a condition in which the oxide semiconductor layer 540 immediately after the film formation does not crystallize as much as possible. For example, in the case where the oxide semiconductor layer 540 is formed by a sputtering method, the oxide semiconductor layer 540 is formed while controlling a temperature of an object to be film-formed (the substrate 500 and the structure formed thereon).
If the film formation is performed on the object to be film-formed by a sputtering method, ions generated in a plasma and atoms recoiled by the sputtering target collide with the object to be film-formed, so that a temperature of the object to be film-formed increases with the film forming process. If the temperature of the object to be formed during the film forming process increases, microcrystals are contained in the oxide semiconductor layer 540 immediately after the film forming process, and crystallization due to subsequent OS annealing is inhibited. In order to control the temperature of the object to be film-formed as described above, for example, the film formation can be performed while cooling the object to be film-formed. For example, it is possible to cool the object to be film-formed from the other side of a surface to be film-formed so that the temperature of the surface to be film-formed of the object to be film-formed (hereinafter referred to as “film formation temperature”) is 100° C. or less, 70° C. or less, 50° C. or less, or 30° C. or less. As described above, by forming the oxide semiconductor layer 540 while cooling the object to be film-formed, it is possible to form the oxide semiconductor layer 540 having a small crystal component in a state immediately after the film formation.
As shown in
After the oxide semiconductor layer 540 is patterned, the oxide semiconductor layer 540 is subjected to the heat treatment (OS annealing) (“OS annealing” in step S2004 in
As shown in
As shown in
A thickness of the metal oxide layer 590 is, for example, 5 nm or more and 100 nm or less, 5 nm or more and 50 nm or less, 5 nm or more and 30 nm or less, or 7 nm or more and 15 nm or less. In the third embodiment, aluminum oxide is used as the metal oxide layer 590. Aluminum oxide has a high barrier property against gas. In the third embodiment, aluminum oxide used as the metal oxide layer 590 suppresses oxygen implanted into the gate insulating layer 550 when the metal oxide layer 590 is formed from being diffused outward.
For example, in the case where the metal oxide layer 590 is formed by a sputtering method, a process gas used in sputtering remains in the film of the metal oxide layer 590. For example, in the case where Ar is used as the process gas for sputtering, Ar may remain in the film of the metal oxide layer 590. Residual Ar can be detected by a SIMS (Secondary Ion Mass Spectrometry) analysis on the metal oxide layer 590.
With the gate insulating layer 550 formed on the oxide semiconductor layer 540 and the metal oxide layer 590 formed on the gate insulating layer 550, a heat treatment for supplying oxygen (oxidation annealing) to the oxide semiconductor layer 540 is performed (“oxidation annealing” in step S2008 of
Oxygen emitted from the gate insulating layer 520 by the oxidation annealing is blocked by the metal oxide layer 530, and thus oxygen is hardly supplied to the lower surface 542 of the oxide semiconductor layer 540. Oxygen emitted from the gate insulating layer 520 diffuses from a region where the metal oxide layer 530 is not formed to the gate insulating layer 550 provided on the gate insulating layer 520, and reaches the oxide semiconductor layer 540 via the gate insulating layer 550. As a result, the oxygen emitted from the gate insulating layer 520 is hardly supplied to the lower surface 542 of the oxide semiconductor layer 540, and is mainly supplied to the side surface 543 and the upper surface 541 of the oxide semiconductor layer 540. Further, oxygen emitted from the gate insulating layer 550 is supplied to the upper surface 541 and the side surface 543 of the oxide semiconductor layer 540 by oxidation annealing. Although there is a case where hydrogen is released from the gate insulating layers 510 and 520 by the oxidation annealing, the hydrogen is blocked by the metal oxide layer 530.
As described above, by the process of the oxidation annealing, it is possible to supply oxygen to the upper surface 541 and the side surface 543 of the oxide semiconductor layer 540 having a large amount of oxygen vacancies while suppressing the supply of oxygen to the lower surface 542 of the oxide semiconductor layer 540 having a small amount of oxygen vacancies.
Similarly, in the oxidation annealing described above, oxygen implanted in the gate insulating layer 550 is blocked by the metal oxide layer 590, and thus is suppressed from being released into the atmosphere. Accordingly, the oxygen is efficiently supplied to the oxide semiconductor layer 540 by the oxidation annealing, and the oxygen vacancies are repaired.
As shown in
As shown in
With the gate electrode 560 patterned, a resistance of the source region S and the drain region D of the oxide semiconductor layer 540 is reduced (“SD resistance reduction” in step S2011 of
As shown in
As shown in
In the semiconductor device 40 manufactured by the manufacturing method described above, in a range where the channel length L of the channel region CH is 2 μm or more and 4 μm or less, and the channel width W of the channel region CH is 2 μm or more and 25 μm or less, an electric property having a mobility of 50 cm2/Vs or more, 55 cm2/Vs or more, or 60 cm2/Vs or more can be obtained. A mobility in the third embodiment is a field effect mobility in a saturation region of the semiconductor device 40. The mobility in the third embodiment means a maximum value of the field effect mobility in a region (that is, the saturation region) in which a potential difference (Vds) between the source electrode and the drain electrode is larger than a value (Vg-Vth) obtained by subtracting a threshold voltage (Vth) of the semiconductor device 40 from a voltage (Vg) supplied to the gate electrode.
[3-5. Example of Electrical Characteristics of Semiconductor Device 40]
An example of the electrical characteristics of the semiconductor device will be mainly described with reference to
In addition, a pixel circuit 183 according to the third embodiment shown in
As shown in
That is, the second transistor OT2 is capable of supplying the same current as the second transistor TR with a gate-source voltage Vgs smaller than the second transistor TR. Therefore, the second transistor OT2 can be driven in the saturated range using the source-drain voltage Vds smaller than the second transistor TR. As a result, by using the semiconductor device 40, the pixel circuit of the present invention can be driven at a lower voltage than the pixel circuit of the comparative example.
By using the semiconductor device 40, a potential difference between the voltages supplied to the first driving power line PVDD and the reference potential line PVSS of the pixel circuit (a potential difference between the driving voltage VDDEL and the reference voltage VSSEL) can be set to be small. The self-luminous display device using the semiconductor device 40 can reduce power consumption because the power supply voltage can be reduced.
As the embodiment of the present invention, each of the embodiments described above or a part of each of the embodiments described above can be appropriately combined as long as they do not conflict with each other.
It is to be understood that the present invention provides other functional effects that are different from the operational effects provided by the aspects of the embodiments described above, and those that are obvious from the description of the present specification or those that can be easily predicted by a person skilled in the art.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-182886 | Nov 2022 | JP | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 10916199 | Zhu | Feb 2021 | B2 |
| 11238786 | Byun | Feb 2022 | B2 |
| 11663952 | Kim | May 2023 | B2 |
| 11810517 | Park | Nov 2023 | B2 |
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| Number | Date | Country |
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| 1020200086783 | Jul 2020 | KR |
| 1020220089325 | Jun 2022 | KR |
| Entry |
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| Office Action issued on Jul. 31, 2024, in corresponding Korean Application No. 10-2023-0148796, 13 pages. |
| Number | Date | Country | |
|---|---|---|---|
| 20240161698 A1 | May 2024 | US |
