Patent Application
20250218340
This application claims the benefit of the Korean Patent Application No. 10-2023-0197068 filed on Dec. 29, 2023, which is hereby incorporated by reference as if fully set forth herein.
The present disclosure relates to a display apparatus and a driving method thereof.
As information technology advances, the market for display apparatuses which are connection mediums connecting a user with information is growing. Therefore, the use of display apparatuses such as light emitting display apparatuses, quantum dot display (QDD) apparatuses, and liquid crystal display (LCD) apparatuses is increasing.
The display apparatuses described above include a display panel which includes a plurality of subpixels, a driver which outputs a driving signal for driving the display panel, and a power supply which generates power which is to be supplied to the display panel or the driver.
In such display apparatuses, when the driving signal (for example, a scan signal and a data signal) is supplied to each of the subpixels provided in the display panel, a selected subpixel may transmit light or may self-emit light, and thus, an image may be displayed.
The present disclosure may allow an embedded point to point interface (EPI) frequency to be unsynchronized with a parasitic resonance frequency of a connector (for example, a cable) when transmitting a signal through an EPI interface, thereby minimizing an electromagnetic interference (EMI) problem. Also, the present disclosure may decrease EMI by using a resonance controller, and thus, may secure the degree of freedom in design for a length of the connector and may remove a subsidiary material such as a fixing tape, thereby reducing the manufacturing cost.
To achieve these technical features and other characteristics and in accordance with the purpose of the disclosure, as embodied and broadly described herein, a display apparatus includes a first circuit board where a timing controller is disposed, a connector connected to the first circuit board, a second circuit board connected to the first circuit board, based on the connector, a controller disposed on the first circuit board to output a control signal, and a parasitic resonance control circuit configured to vary a parasitic value of the connector, based on the control signal output from the controller.
The controller may control a voltage applied to the parasitic resonance control circuit to vary at least one of a parasitic resonance frequency of the connector and a parasitic resonance magnitude of the connector.
The parasitic resonance control circuit may include at least one of a first parasitic resonance control circuit including a varactor diode where a capacitance varies and a second parasitic resonance control circuit including a field effect transistor (FET) operating as a resistor in a deep triode region.
The controller may be configured as a sensing type which senses a voltage from a conductor disposed at a periphery of the connector to obtain a sensing value and outputs the control signal, based on the obtained sensing value, or the controller may be configured as a non-sensing type which outputs the control signal as random bits.
The controller may sense a voltage from at least one of a low voltage electrode part and a ground pad part disposed at a periphery of the connector to obtain a sensing value.
The parasitic resonance control circuit may be disposed at both ends of a pad part on which the connector is attached in the first circuit board.
The ground pad part may be disposed in an island shape to be isolated from a ground electrode disposed in the first circuit board.
The ground pad part may be disposed in a first layer of the first circuit board, and the low voltage electrode part may be disposed in a second layer of the first circuit board.
The first circuit board may include a pattern portion formed by removing a metal layer disposed in a second layer of the first circuit board, based on a region where the pad part is formed.
In another aspect of the present disclosure, a driving method of a display apparatus, including a first circuit board where a timing controller is disposed, a connector connected to the first circuit board, a second circuit board connected to the first circuit board, based on the connector, a controller disposed on the first circuit board to output a control signal, and a parasitic resonance control circuit configured to vary a parasitic value of the connector, based on the control signal output from the controller, includes: analyzing a noise level, based on the sensing value; when the noise level is higher than a threshold value, determining that the parasitic value of the connector does not correspond to an avoidable control value, and changing the control signal; and when the noise level is lower than the threshold value, determining that the parasitic value of the connector corresponds to the avoidable control value, and fixing the control signal.
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the disclosure and together with the description serve to explain the principle of the disclosure. In the drawings:
Hereinafter, the present disclosure will be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the disclosure are shown. The disclosure may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the disclosure to those skilled in the art.
A display apparatus according to the present disclosure may be applied to televisions (TVs), video players, personal computers (PCs), home theaters, electronic devices for vehicles, and smartphones, but is not limited thereto. The display apparatus according to the present disclosure may be implemented as a light emitting display apparatus, a quantum dot display (QDD) apparatus, or a liquid crystal display (LCD) apparatus. Hereinafter, for convenience of description, a light emitting display apparatus self-emitting light by using an inorganic light emitting diode or an organic light emitting diode will be described for example.
As illustrated in
A supply unit 110 (a set or a host system) may output a video data signal supplied from the outside or an image data signal stored in an internal memory thereof. The video supply unit 110 may supply a data signal and the various driving signals to the timing controller 120.
The timing controller 120 may output a gate timing control signal GDC for controlling an operation timing of the scan driver 130, a data timing control signal DDC for controlling an operation timing of the data driver 140, and various synchronization signals (a vertical synchronization signal Vsync and a horizontal synchronization signal Hsync). The timing controller 120 may provide the data driver 140 with the data timing control signal DDC and a data signal DATA supplied from the video supply unit 110. The timing controller 120 may be implemented as an integrated circuit (IC) type and may be mounted on a printed circuit board (PCB), but is not limited thereto.
The scan driver 130 may output a scan signal (or a scan voltage) in response to the gate timing control signal GDC supplied from the timing controller 120. The scan driver 130 may supply the scan signal to a plurality of subpixels, included in the display panel 150, through a plurality of gate lines GL1 to GLm. The scan driver 130 may be implemented as an IC type or may be directly provided on the display panel 150 in a gate in panel (GIP) type, but is not limited thereto.
In response to the data timing control signal DDC supplied from the timing controller 120, the data driver 140 may sample and latch the data signal DATA, convert a digital data signal into an analog data voltage on the basis of a gamma reference voltage, and output the analog data voltage. The data driver 140 may respectively supply data voltages to the subpixels of the display panel 150 through a plurality of data lines DL1 to DLn. The data driver 140 may be implemented as an IC type or may be mounted on the display panel 150 or a PCB, but is not limited thereto.
The power supply 180 may generate a first power having a high level and a second power having a low level, based on an external input voltage supplied from the outside, and may output the first voltage and the second voltage through a first power line EVDD and a second power line EVSS. The power supply 180 may generate and output a voltage (for example, a gate voltage including a gate high voltage and a gate low voltage) needed for driving of the scan driver 130 or a voltage (a drain voltage including a drain voltage and a half drain voltage) needed for driving of the data driver 140, in addition to the first power and the second power.
The display panel 150 may display an image, based on the first power, the second power, and a driving signal including the scan signal and a data voltage. The subpixels of the display panel 150 may each self-emit light. The display panel 150 may be manufactured based on a substrate, having stiffness or flexibility, such as glass, silicon, or polyimide. Also, the subpixels emitting light may include pixels including red, green, and blue, or may include pixels including red, green, blue, and white.
For example, one subpixel SP may be connected to a first data line DL1, a first gate line GL1, the first power line EVDD, and the second power line EVSS and may include a pixel circuit which includes a switching transistor, a driving transistor, a capacitor, and an organic light emitting diode. The subpixel SP used in the light emitting display apparatus may self-emit light, and thus, a configuration of a circuit may be complicated. Also, an organic light emitting diode emitting light and a compensation circuit compensating for a degradation in a driving transistor supplying a driving current needed for driving of the organic light emitting diode may be variously implemented. Accordingly, the subpixel SP is simply illustrated as a block type.
Hereinabove, each of the timing controller 120, the scan driver 130, and the data driver 140 has been described as an individual element. However, based on an implementation type of the light emitting display apparatus, one or more of the timing controller 120, the scan driver 130, and the data driver 140 may be integrated into one IC.
As illustrated in
The shift register 131 may operate based on the clock signals Clks and the start signal Vst output from the level shifter 135 and may output scan signals Scan[1] to Scan[m] for turning on or off a transistor formed in the display panel. The shift register 131 may be formed as a thin film type in the display panel, based on a GIP type.
As illustrated in
As illustrated in
As illustrated in
For example, the timing controller 120 and the power supply 180 may be disposed on a first circuit board 126. The first circuit board 126 may be connected to a second circuit board 148, based on a first connector 121 such as a cable. The plurality of data drivers 140a to 140d may be disposed on a plurality of third circuit boards 141a to 141d. The display panel 150 and the second circuit board 148 may be electrically connected to each other by the plurality of third circuit boards 141a to 141d. However, this may be merely an embodiment, and the present disclosure is not limited thereto.
As illustrated in
The data transmitter Tx included in the timing controller 120 may include a first data processor 123, a clock adjuster 124, a signal synthesizer 125, and a transfer buffer unit 126.
The first data processor 123 may perform data processing on various control signals CNS and an RGB data signal RGB, which are to be output from the timing controller 120, in the form capable of serial transmission. To this end, the first data processor 123 may include a serializer.
The clock adjuster 124 may adjust a clock signal CLK so that the RGB data signal RGB and the various control signals CNS to be output from the timing controller 120, based on an appropriate clock signal CLK. To this end, the clock adjuster 124 may include a phase-locked loop (PLL).
The signal synthesizer 125 may synthesize the RGB data signal RGB, the various control signals CNS, and the clock signal CLK, output from the first data processor 123, in the form of data packets. To this end, the signal synthesizer 125 may include a first input terminal connected to an output terminal of the first data processor 123, a second input terminal connected to an output terminal of the clock adjuster 124, and an output terminal connected to an input terminal of the transfer buffer unit 126.
The transfer buffer unit 126 may transfer a data packet, output from the signal synthesizer 125, through an EPI interface EPI connected to the data driver 140. To this end, the transfer buffer unit 126 may include a first terminal connected to a first transfer line PL of the EPI interface EPI and a second terminal connected to a second transfer line NL. That is, the transfer buffer unit 126 may be connected to a pair of transfer lines PL and NL.
The data driver 140 may include a reception buffer unit 146, a second data processor 143, and a clock recovery unit 144.
The reception buffer unit 146 may receive the data packet transferred through the EPI interface EPI connected to the timing controller 120. To this end, the reception buffer unit 146 may include a first terminal connected to the first transfer line PL of the EPI interface EPI and a second terminal connected to the second transfer line NL.
The second data processor 143 may perform de-serialization for extraction the RGB data signal RGB and the various control signals CNS in a serial data packet transferred through the reception buffer unit 146. To this end, the second data processor 143 may include a de-serializer.
The clock recovery unit 144 may extract or recover the clock signal CLK in the serial data packet transferred through the reception buffer unit 146.
In
As seen in
As illustrated in
The timing controller 120 disposed on the first circuit board 126 may be connected to a signal line PSL. The signal line PSL may be connected to a pad part PAD disposed on the first circuit board 126. The first connector 121 may include a transfer line FSL which is connected to pads included in the pad part PAD and lines for transferring signals.
The low voltage electrode part EVSS may be disposed under the signal line PSL which electrically connects the timing controller 120 to the pad part PAD. The low voltage electrode part EVSS may be disposed in a second layer 2F, instead of a first layer 1F, of the first circuit board 126 where the timing controller 120 and the like are disposed and may be formed in a tetragonal island shape so as to be isolated from a ground electrode GND included in the first circuit board 126. A contact portion CNT of the low voltage electrode part EVSS formed in the second layer 2F may be exposed through a contact hole CH formed in the first layer 1F of the first circuit board 126. The controller CON may be connected to the low voltage electrode part EVSS through the contact portion CNT.
The first circuit unit REC may be disposed at both ends of the pad part PAD. The first circuit unit REC may vary a capacitance of a resonance control capacitor, based on a signal output from the controller CON. The first circuit unit REC may control a parasitic resonance frequency of the first connector 121, based on a capacitor.
The second circuit unit VAR may be adjacent to the first circuit unit REC and may be disposed at the two ends of the pad part PAD. The second circuit unit VAR may control a parasitic resonance magnitude (amplitude) of the first connector 121, based on a resistance.
In the above description, an example where the first circuit board 126 includes the first layer 1F and the second layer 2F has been described. However, the first circuit board 126 may be configured as two layers or four layers.
As illustrated in
The controller CON may include a first control line SL1 for outputting a control signal and a second control line SL2 for obtaining a sensing value. A first control line SL1 may be selectively connected to at least one of the first circuit unit REC and the second circuit unit VAR. A second control line SL2 may be selectively connected to at least one of the low voltage electrode part EVSS and the ground pad part IGND.
The controller CON may sense a voltage from at least one of the low voltage electrode part EVSS and the ground pad part IGND through the second control line SL2 to obtain a sensing value. The controller CON may analyze a noise level of an EPI frequency, based on the sensing value, and may provide a control value for avoiding the parasitic resonance frequency of the first connector 121. The controller CON may output a control signal for controlling at least one of the first circuit unit REC and the second circuit unit VAR, based on the control value.
In
As illustrated in
The method may sense a voltage from at least one of the low voltage electrode part EVSS and the ground pad part IGND to obtain a sensing value and may detect noise of an EPI frequency (EPI 1UI multiplication noise detect), based on the sensing value (S300). In
The method may vary the control signal for each condition, based on the sensing value, and may analyze a detected noise level DTL (S400). At this time, when the detected noise level DTL is higher than an internally predetermined threshold value Vth (DTL≥Vth), the method may determine that a control value of a current control signal and a capacitance of a resonance control capacitor Cap corresponding thereto do not correspond to a control value for avoiding the parasitic resonance frequency of the first connector 121 and may repeat preceding steps. On the other hand, when the detected noise level DTL is lower than the internally predetermined threshold value Vth (DTL<Vth), the method may determine that the control value of the current control signal and the capacitance of the resonance control capacitor Cap corresponding thereto correspond to the control value for avoiding the parasitic resonance frequency of the first connector 121 and may fix the control signal Control (S500).
The controller CON may output the control signal Control provided based on the control value for avoiding the parasitic resonance frequency of the first connector 121 to fix the capacitance of the resonance control capacitor Cap (S600).
As illustrated in
The voltage adjuster PWR may operate based on the control signal SEL output from the controller CON and may vary an input voltage input through an input terminal VIN to output through an output terminal VOUT. The voltage adjuster PWR may include a switch SW and resistors R1 to R4 serially connected between the input terminal VIN and a ground terminal GND. The switch SW may connect the output terminal VOUT to at least one of nodes S00, S01, S10, and S11 of the resistors R1 to R4 serially connected to one another, based on the control signal SEI for varying the input voltage input through the input terminal VIN to output through the output terminal VOUT.
The first circuit unit REC may vary a capacitance of a resonance control capacitor CDa to control the parasitic resonance frequency of the first connector, based on an output voltage output from the voltage adjuster PWR.
The resonance control capacitor CDa may include a first electrode connected to the ground terminal GND of the voltage adjuster PWR and a second electrode connected to the output terminal VOUT of the voltage adjuster PWR. The resonance control capacitor CDa may be selected as a varactor diode which has a capacitor characteristic and has a capacitance which varies based on a level of an applied voltage, but is not limited thereto.
A direct current (DC) block capacitor DCB may include a first electrode connected to the output terminal VOUT of the voltage adjuster PWR and a second electrode connected to the noise level sensing point NLP. The DC block capacitor DCB may prevent a DC component from flowing in from the noise level sensing point NLP. To this end, a capacitance of the DC block capacitor DCB may be higher than that of the resonance control capacitor CDa, but is not limited thereto.
The resonance controller according to the first embodiment may have a structure (a sensing type) which obtains a noise level NL from the noise level sensing point NLP and provides a control value for avoiding the parasitic resonance frequency of the first connector, based on whether a detected noise level is higher or lower than the internally predetermined threshold value. However, the resonance controller may provide the control value for avoiding the parasitic resonance frequency of the first connector despite being implemented in a structure (a non-sensing type) which does not obtain the noise level NL from the noise level sensing point NLP. This may be as illustrated in
The resonance controller according to the second embodiment illustrated in
As illustrated in
The second circuit unit VAR may be connected to a ground pad part IGND through a DC block capacitor DCB. The second circuit unit VAR may vary a resistance value based on an output voltage output based on a control signal SEL output from the controller CON so that a parasitic resonance magnitude varies.
The second circuit unit VAR may include an FET and a fixed resistor FR. The FET may include a gate electrode connected to an output terminal VOUT of the voltage adjuster PWR, a first electrode connected to a second electrode of the DC block capacitor DCB, and a second electrode connected to one end of the fixed resistor FR. The fixed resistor FR may include the one end connected to the second electrode of the FET and the other end connected to a ground terminal GND.
As see in a circle defined by a dotted line in
The resonance controller according to the third embodiment may have a structure which varies a parasitic resonance magnitude, based on the second circuit unit VAR for varying a resistance value.
The resonance controller according to an embodiment may decrease EMI, based on the resonance controller illustrated in
As illustrated in
As illustrated in
The first phase (Phase-I) may be a period where a clock training pattern is transferred so that the clock recovery unit 144 included in the data driver 140 extracts or recovers a normal and stable clock signal CLK. The second phase (Phase-II) may be a period where a control signal CON for controlling an apparatus included in the data driver 140 is transferred. The third phase (Phase-III) may be a period where an RGB data signal RGB is transferred to the data driver 140. Accordingly, the first phase (Phase-I) and the second phase (Phase-II) may be transferred during a blank period where a display panel does not display an image, and the third phase (Phase-III) may be transferred during an active period where the display panel displays an image.
The first phase (Phase-I) may be defined as a period which is provided for configuring a transfer line for stably transferring and receiving a signal between a timing controller and a data driver. The timing controller and the data driver may perform an operation for optimizing an interface during the first phase (Phase-I), based on various environment variables (a case where power is applied to an apparatus, a case where a line is unstable, etc.), and this period may be used as a driving period of a resonance controller.
As illustrated in
As illustrated in
Table 2 may show a simulation result using a first circuit unit included in a resonance controller, and Table 3 may show a simulation result using a second circuit unit included in the resonance controller.
Referring to the following Table 2 and Table 3, the resonance controller according to an embodiment may improve EMI by about 3.8 dB through parasitic resonance avoidance control using the first circuit unit and may improve EMI by about 3 dB through parasitic resonance magnitude control using the second circuit unit.
Hereinabove, the present disclosure may allow an EPI frequency to be unsynchronized with a parasitic resonance frequency of a connector (for example, a cable) when transmitting a signal through an EPI, thereby minimizing an EMI problem. Also, the present disclosure may control a parasitic resonance frequency of the connector (avoid or distribute a parasitic resonance frequency), based on a sensing type or a non-sensing type. Also, the present disclosure may decrease EMI by using a resonance controller, and thus, may secure the degree of freedom in design for a length of the connector and may remove a subsidiary material such as a fixing tape, thereby reducing the manufacturing cost.
The effects according to the present disclosure are not limited to the above examples, and other various effects may be included in the specification.
While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure including those of the following claims.
The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary to employ concepts of the various embodiments to provide yet further embodiments.
These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0197068 | Dec 2023 | KR | national |
