The features and advantages of embodiments of the present invention are apparent in reference to the detailed description the following drawings.
The present invention will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.
In the drawings, it will be understood that when an element or layer is referred to as being “on”, “connected to” or “coupled to” another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.
A display device and its driving method according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.
Referring to
The display panel 300 includes pixels PX that are coupled to signal lines G1-Gn, D1-Dm in a matrix form. The signal lines includes gate (scanning) lines G1-Gn and GL for transferring scanning signals, data lines D1-Dm and DL for transferring data voltages, and drive voltage lines VL for transferring a driving voltage Vdd. The gate lines G1-Gn, GL run parallel with each other in a row direction. The data lines D-Dm, DL run parallel with driving voltage lines VL in a column direction.
As shown in
Each pixel PX of the OLED display device includes an organic light emitting element LD, a driving transistor Qd, a storage capacitor Cst and a switching transistor Qs.
The switching transistor Qs includes a control terminal, an input terminal, and an output terminal, with the control terminal connected to the gate line GL, the input terminal connected to the data line DL, and the output terminal connected to the driving transistor Qd. Also, the switching transistor Qs allows for a data signal to be transferred from the data line DL in response to a gate signal on the gate line GL.
The driving transistor Qd includes a control terminal, an input terminal, and an output terminal, with the control terminal connected to the switching transistor Qs, the input terminal connected to the driving voltage line VL, and the output terminal connected to the organic light emitting element (OLED) LD. Also, the driving transistor Qd produces an output current ILD. The output current ILD varies according to the voltage difference between the control terminal and the output terminal of the driving transistor Qd.
The storage capacitor Cst is connected between the control terminal and input terminal of the driving transistor Qd. This storage capacitor Cst charges based on a data signal which is applied to the control terminal of the driving transistor Qd, and maintains its level even after the switching transistor Qs is turned off.
The organic light emitting element LD is an organic light emitting diode OLED, and comprises a cathode coupled with common voltage Vss and an anode coupled with the output terminal of the driving transistor Qd. The organic light emitting element LD emits light in proportion to the output current ILD of the driving transistor Qd to display an image.
The switching transistor Qs and the driving transistor Qd are n-type field effect transistors (FETs) made of amorphous silicon or polycrystalline-silicon. At least one of them may be a p-type FET. It should be noted that the connection relationship of the transistors Qs and Qd, the capacitor Cst, and the LD may vary according to the particular application without departing from the principles of embodiments of the present invention.
In
The gate driver 400 is coupled with gate lines G1-Gn and provides gate signals to the gate lines G1-Gn, in which the gate signals comprise a high voltage Von by which the switching transistor Qs is turned on and a low voltage Voff by which the switching transistor Qs is turned off.
The data driver 500 which is coupled with data lines D1-Dm receives a plurality of reference gray voltages from the gray voltage generator 800 and generates data voltages. The data voltages which are produced based on the reference gray voltages are transferred to the data lines D1-Dm, in which each reference gray voltage data voltage is divided into several voltages which are the data voltages.
Signal controller 600 controls gate driver 400, data driver 500 and gray voltage generator 800. The drivers 400, 500, 600, and 800 may be formed on the display panel 300 together with the signals G1-Gn, D1-Dm and thin film transistors Q.
Alternatively, the drivers 400, 500, 600, and 800 may be formed on the display panel 300 with the use of one chip, with the use of a tape carrier package TCP in the form of flexible printed circuit film, or mounted on a separate printed circuit board. As an additional alternative, drivers 400, 500, 600, and 800 may be formed in one or more chips within or outside panel 300.
The operation and method of this organic light emitting display device will now be explained in detail.
The signal controller 600 receives an input image signal R, G, B and its input control signal for controlling display of the image signal from an external graphics controller (not shown). The input image signal R, G, B includes luminance information of each pixel, in which the luminance may be represented by the number of gray levels, for example 1024(=210), 256(=28), or 64(=26) gray levels. For example, the input control signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a main clock signal MCLK, and a data enable signal DE.
The signal controller 600 generates an output image signal DAT, a gate (scanning) control signal CONT1, a data control signal CONT2 and a gray voltage control signal CONT3 in response to the input signals R, G, B and an input control signal in order to apply them to the display panel 300. The signal controller 600 provides the gate control signal CONT1 to the gate driver 400, and the gray voltage control signal CONT3 to the gray voltage generator 800. At the same time, both the data control signal CONT2 and the output image signal DAT are provided to the data driver 500.
The gate control signal CONT1 includes an injection (scanning) start signal STV and at least one clock, in which the injection start signal STV indicates that injection of high voltage Von starts and the clock signal controls the output period of high voltage Von. The gate control signal CONT1 may include an output enable signal OE which limits the duration time of the high voltage Von.
The data control signal CONT2 includes a horizontal synchronization start signal STH which indicates the start of the transfer of output image signal DAT to one row of pixels PX. The data control signal CONT2 may include a data clock signal HCLK and a load signal LOAD which indicates that analog data voltage is to be transferred to the data lines D1-Dm.
The gray voltage control signal CONT3 includes gamma data (GAMMA) for generating reference contrast (gray) voltages, in which the gamma data GAMMA are digital signals. The gray voltage generator 800 generates reference gray voltages for data driver 500 in response to the gamma data GAMMA received from the signal controller 600. The gamma data changes with time, as does the reference gray voltage values.
The data driver 500 generates gray voltages for all gray levels by dividing the reference gray voltages. In response to the data control signal CONT2 from the signal controller 600, the data driver 500 receives an output image data DAT, with respect to one row of pixels PX, and selects gray voltages corresponding to the output image data DAT. Thereafter, the output image data DAT, which are digital data voltages, are changed into analog data voltages, and provided to the corresponding data lines D1-Dm by data driver 500.
The gate driver 400, which is also called an injection driver or scanning driver, provides an injection signal having a high voltage Von to gate lines G1-Gn in response to the gate control signal CONT1 of signal controller 600. Then, switching transistors Qs coupled with the gate lines G1-Gn are turned on and therefore data voltages on the data lines D1-Dm are provided to the terminals of driving transistors Qd in each pixel.
The data voltages provided to the driving transistor Qd are charged in storage capacitors Cst. Though the switching transistors Qs are turned off, the charged data voltages in the storage capacitors Cst can be preserved. Owing to the data voltages preserved in the storage capacitors Cst, the driving transistors Qd generate output current ILD based on the magnitude of the data voltages. Accordingly, the organic light emitting element (OLED) LD emits light in proportion to the magnitude of output current ILD so that each pixel PX can display its image.
After one horizontal cycle (1H) which is one cycle of the horizontal synchronization signal Hsync and the data enable signal DE is finished, the data driver 500 and the gate driver 400 repeat their operation on the next pixel row. By this method, all gate lines G1-Gn sequentially receive the gate signal during one frame period and thus data are applied to all pixels PX. When one frame finishes, the next frame starts, with the same operation repeatedly performed.
The gray voltage generator according to an exemplary embodiment of the present invention will now be described in detail.
Referring to
If each pixel receives a different driving voltage Vdd, which is referred to as a voltage drop, luminance of each pixel may be compensated by increasing the voltage applied to the data line DL by as much as the corresponding voltage drop.
As explained above, the data driver 500 generates data voltage by dividing the reference gray voltage from the gray voltage generator 800. By providing a compensation voltage in addition to the reference gray voltage, the voltage-drop along the pixel column is eliminated. The compensation voltage may be as much as the voltage-drop value. The voltage-drop value of each pixel row may be measured by direct measurement of the driving voltage Vdd which is provided to each pixel row. So, the compensation voltage for the voltage-drop may have a different value for every pixel row. Alternatively, the voltage-drop value of each pixel row may be determined from the voltage difference between the driving voltage Vdd of the first pixel row and the last pixel row, in which the voltage difference between the first pixel row and the last pixel row is divided by the number of pixel rows. So, an average voltage-drop value with respect to each pixel row can be calculated.
When the amount of voltage drop of the driving voltage Vdd is reflected on the reference gray voltage, it can be reflected on every pixel row or every multiple (m) of pixel rows. For example, when the compensation voltage for the voltage-drop value is applied to the reference gray voltage every m pixel rows, where the number of whole pixel rows is equal to “n” (where m is an integer having 1≦m≦n), a voltage increase (Vc) may be determined by the following equation.
Vc=ΔV×m/n [Equation 1]
Here, ΔV is a driving voltage difference between the first pixel row and the last pixel row.
The structure and operation of the gray voltage generator of the display device in accordance with an embodiment of the present invention will now be described in detail with reference to
Referring to
The reference voltage input terminals REFH, REFL receive the references voltages VREFH, VREFL which are used for producing reference gray voltages along with the ground voltage GND. The reference voltages are composed of upper reference voltage VREFH having a relatively higher voltage and lower reference voltage VREFL having a relatively lower voltage.
The serial data input signal SDI is a data signal which includes information for generating a reference gray voltage and is usually supplied from signal controller 600. The serial data input signal SDI may include 3 bits, which designate the output terminal of the reference gray voltage, and 10 bits which designate the magnitude of the reference gray voltage. Also, the serial data input signal SDI may include a digital signal which controls the operation of the gray voltage generator 800.
Referring to
The 9th to 0th bits, B9-B0, of the serial data input signal SDI are identified as D9, D8, D7, D6, D5, D4, D3, D2, D1, and D0 in
The gray voltage generator 800 provides reference gray voltages to the corresponding output terminals OUTA, OUTB, OUTC, OUTD, OUTE, OUTF, OUTG, and OUTH after calculating the reference gray voltages based on the gamma data. The method of calculating is as follows.
Vout=VREFL+{GAMMA DATA/1024}×(VREFH−VREFL) [Equation 2]
Wherein, VOUT is a reference gray voltage which is provided from the reference gray voltage output terminals OUTA, OUTB, OUTC, OUTD, OUTE, OUTF, OUTG, and OUTH.
Referring to
The variation of luminance in this display device in accordance with an embodiment of the present invention is explained with reference to
Referring to
Referring to
After the same image data is applied to display devices having corresponding reference gray voltages as listed in
In
In particular, the luminance of
In
Ln={(Lmax−Lmin)/Lmax}×100 [Equation 3]
Herein, Lmax represents a maximum value and Lmin represents a minimum value among luminance values at the nine measurement points,
Referring to
For example, after applying different image data to two points P11, P12 for two different display devices having corresponding reference gray voltages of
In
Referring to
As shown in L4 in
When the gray level of the measurement positions is higher than at other portions, luminance may increase because of a high data voltage applied according to the change in the gray level than the compensation value for compensating the driving voltage Vdd, which may degrade the luminance uniformity. However, the luminance difference between the luminance at the measurement positions P11 and P12 is 5 cd/m2, a level that may not degrade the luminance uniformity. Accordingly, in the display device in which the reference gray voltages are compensated according to the exemplary embodiment of the present invention, the luminance uniformity can be sustained in spite of the change in the gray level.
Accordingly, durability of display device may be extended and aperture ratio may be preserved because there is no change in the structure of the driving voltage line. According to the exemplary embodiment of the present invention, the voltage drop of a driving current can be compensated without changing the structure of the driving voltage lines, thereby preventing degradation of luminance at a portion on a screen and increasing uniformity of display. Accordingly, the elements included in the display device may be free from stress to achieve a certain luminance level, and the life span of the display device can be lengthened. In addition, because the structure of the driving voltage lines is not changed, a sufficient aperture ratio of the display device can be obtained.
Although the present invention has been described by way of exemplary embodiments, it should be understood that many changes and substitutions may further be made by those skilled in the art without departing from the scope of the present invention which is defined by the appended claims.
Number | Date | Country | Kind |
---|---|---|---|
10-2006-0065285 | Jul 2006 | KR | national |