Patent Application
20250191523
This application claims the priority of Chinese Patent Application No. 202311707873.1, filed on Dec. 11, 2023, the content of which is incorporated herein by reference in its entirety.
The present disclosure generally relates to the field of display technology and, more particularly, relates to a display device and its driving method.
With the continuous development of display technology, users have increasingly higher requirements for performance of display devices in all aspects.
Operation of a display device includes processes of powering on and off. Currently, the processes of powering on and off take a long time, affecting the users' experience.
One aspect of the present disclosure provides a display device. The display device includes a display panel. The display panel includes pixel circuits arranged in multiple rows. Each pixel circuit includes a light-emitting control transistor and a driving transistor. The light-emitting control transistor is used to control a corresponding light-emitting element to enter a light-emitting stage; and the driving transistor is used to provide a driving current for the corresponding light-emitting element. A driving process of the display panel includes a first stage and a display stage. The first stage is located at least before or after the display stage. In the first stage, at least one of light-emitting control transistors and driving transistors in each row of pixel circuits is turned off. A duration of the first stage is t, and a data refresh frequency of the pixel circuits in the display stage is f, t≤1/f.
Another aspect of the present disclosure provides a driving method of a display device. The display device includes a display panel. The display panel includes pixel circuits arranged in multiple rows. Each pixel circuit includes a light-emitting control transistor for controlling a corresponding light-emitting element to enter a light-emitting stage and a driving transistor for providing a driving current to the corresponding light-emitting element. A driving process of the display panel including a first stage and a display stage, and the first stage is located at least before or after the display stage. The driving method includes: in the first stage, controlling at least one of light-emitting control transistors and driving transistors in each row of pixel circuits to be turned off. A duration of the first stage is t, and a data refresh frequency of the pixel circuit in the display stage is f, wherein t≤1/f.
Other aspects or embodiments of the present disclosure can be understood by those skilled in the art in light of the description, the claims, and the drawings of the present disclosure.
The following drawings are merely examples for illustrative purposes according to various disclosed embodiments and are not intended to limit the scope of the present disclosure.
Reference will now be made in detail to exemplary embodiments of the disclosure, which are illustrated in the accompanying drawings. Hereinafter, embodiments consistent with the disclosure will be described with reference to drawings. In the drawings, the shape and size may be exaggerated, distorted, or simplified for clarity. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts, and a detailed description thereof may be omitted.
Further, in the present disclosure, the disclosed embodiments and the features of the disclosed embodiments may be combined under conditions without conflicts. It is apparent that the described embodiments are some but not all of the embodiments of the present disclosure. Based on the disclosed embodiments, persons of ordinary skill in the art may derive other embodiments consistent with the present disclosure, all of which are within the scope of the present disclosure.
Moreover, the present disclosure is described with reference to schematic diagrams. For the convenience of descriptions of the embodiments, the cross-sectional views illustrating the device structures may not follow the common proportion and may be partially exaggerated. Besides, those schematic diagrams are merely examples, and not intended to limit the scope of the disclosure. Furthermore, a three-dimensional (3D) size including length, width, and depth should be considered during practical fabrication.
In the present disclosure, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship between these entities or operations or order. Moreover, the terms “including”, “comprising” or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device that includes a series of elements includes not only those elements, but also those that are not explicitly listed or also include elements inherent to this process, method, article or equipment. If there are no more restrictions, the elements defined by the sentence “including . . . ” do not exclude the existence of other same elements in the process, method, article, or equipment that includes the elements.
It should be understood that when describing the structure of a component, when a layer or region is referred to as being “on” or “above” another layer or another region, the layer or region may be directly on the other layer or region, or indirectly on the other layer or region, for example, layers/components between the layer or region and another layer or another region. And, for example, when the component is reversed, the layer or region may be “below” or “under” the other layer or region. In the present disclosure, the term “electrical connection” refers to that two components are directly electrically connected with each other, or the two components are electrically connected via one or more other components.
In the present disclosure, the term “and/or” is just an association relationship describing related objects, indicating that there may be three relationships. For example, A and/or B, may mean: A alone exists, A and B exist simultaneously, or B alone exists. Further, the character “/” in the present disclosure generally indicates that the related objects are an “or” relationship.
In the present disclosure, the term “electrical connection” may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components. The term “drive” may mean “control” or “operate”. The term “part” may mean “partially”. The term “pattern” may refer to a “member”. The term “end” may refer to an “end segment” or an “end edge”. The display panel may be a display device or a module/part of a display device.
The present disclosure provides a display device and its driving method.
In one embodiment shown in
As shown in
One pixel circuit 20 may be electrically connected to one corresponding light-emitting element 30 of the plurality of light-emitting elements 30, and the pixel circuit 20 may be used to drive the corresponding light-emitting element 30 to emit light. The light-emitting element 30 may include an organic light-emitting diode (OLED). Further, the pixel circuit 20 may be electrically connected to a data line DATA.
In one embodiment, as shown in
In some embodiments, the pixel circuit 20 may further include a data writing transistor M2, a threshold compensation transistor M5, a reset transistor M4, and an initialization transistor M7.
Gates of the light-emitting control transistors M1 and M6 may be electrically connected to a light-emitting control signal line EMIT. Gates of at least some different transistors among the data writing transistor M2, the threshold compensation transistor M5, the reset transistor M4, and the initialization transistor M7 may be electrically connected to different scan lines.
The driving process of the display panel may include first stages and a display stage. The first stages may be located before and/or after the display stage. The display stage may include at least one display frame. One of the first stages before the display stage may be called a power-on stage, and another one of the first stages after the display stage may be called a power-off stage.
In the first stages, light-emitting control transistors M1 and M6 in each row of pixel circuits 20 may be turned off, and/or the driving transistor M3 in each row of pixel circuits 20 may be turned off. It can be understood that, when the light-emitting control transistors M1 and M6 in each row of pixel circuits 20 are turned off, the corresponding light-emitting elements 30 driven by each row of pixel circuits 20 may not emit light; and, when the driving transistors M3 in each row of pixel circuits 20 are turned off, the corresponding light-emitting elements 30 driven by each row of pixel circuits 20 may also do not emit light.
The duration of the first stages may be t, and the data refresh frequency of the pixel circuits 20 in the display stage may be f, t≤1/f. The data refresh frequency may be a frequency at which the data signal is effectively written to the gates of the drive transistors. 1/f may be the duration of a refresh frame, and the refresh frame may be understood as a display frame.
In the present disclosure, by controlling the duration of the power-on and/or power-off stages within one refresh frame, the time required for power-on and power-off may be shortened, enabling fast power-on and power-off, and improving the user experience. Further, in the first stages, when the light-emitting control transistors and driving transistors of each row of pixel circuits are both turned off, a double insurance to prevent the light-emitting elements from emitting light, thereby helping to avoid the flash screen of the display device during the power-on and/or power-off stages.
In some embodiments, the display device may be able to perform display with different frequencies in different areas, and the pixel circuits may have multiple data refresh frequencies during the display stage. For example, the data refresh frequency of some display areas may be 60 Hz, and the data refresh frequency of some other display areas may be 90 Hz. f may be the maximum value among multiple data refresh frequencies. When f is larger, 1/f may be smaller. Therefore, the duration t of the first stage may be smaller, further shortening the time required for powering on and off.
In some embodiments, as shown in
In one embodiment shown in
The gate of the first setting transistor T7 may be electrically connected to the first control signal line RST_E, the first electrode of the first setting transistor T7 may be electrically connected to the second potential signal line VGH, and the second electrode of the first setting transistor T7 may be electrically connected to the gate of the first output transistor T2 (including direct electrical connection and indirect electrical connection).
The first potential signal line VGL may be used to provide the enabling voltage of the light-emitting control transistors M1 and M6, and the second potential signal line VGH may be used to provide the disabling voltage of the light-emitting control transistors M1 and M6. For example, in one embodiment, the light-emitting control transistors M1 and M6 may be P-type transistors, their enabling voltage may be the low voltage vgl, and their disabling voltage may be the high voltage vgh.
Each of the plurality of emission shift circuits 40 may have the circuit structure shown in
As shown in
In the first stage, since the enabling voltage is on the first control signal line RST_E, the first setting transistor T7 may be turned on, and the high voltage vgh on the second potential signal line VGH may be transmitted to the gate of the first output transistor T2, such that the first output transistor T2 in each emission shift circuit 40 may be turned off. Each emission shift circuit 40 may be prevented from outputting the low voltage vgl on the first potential signal line VGL, and may instead output the high voltage vgh on the second potential signal line VGH, thereby controlling the light-emitting control transistors M1 and M6 to be turned off in the first stage.
For example, in one embodiment, as shown in
For example, within one signal refresh period of the clock signal line CK_E and the clock signal line XCK_E, all of the plurality of emission shift circuits 40 may output the high voltage vgh on the second potential signal line VGH. When the signal on the clock signal line XCK_E jumps from high level to low level, the transistors T1 of a portion of the plurality of emission shift circuits 40 may be turned on, such that the portion of the plurality of emission shift circuits 40 may output the high voltage vgh on the second potential signal line VGH. When the signal on the clock signal line CK jumps from high level to low level, the transistors T1 of another portion of the plurality of emission shift circuits 40 may be turned on, such that the another portion of the plurality of emission shift circuits 40 may output the high voltage vagh on the second potential signal line VGH.
Within a data refresh frame, there may be usually multiple transitions of signals on the clock signal line CK_E and the clock signal line XCK_E. The length of a signal refresh cycle of the clock signal line CK_E and the clock signal line XCK_E may be shorter than the length of the data refresh frame.
For example, as shown in
As shown in
In some embodiments, in the first stage, the gates of the driving transistors M3 in each row of pixel circuits 20 may be written with the first voltage V1, and the first voltage V1 may be larger than or equal to the voltage of the first power line PVDD in the display stage. The voltage of the first power line PVDD during the display stage may be a positive voltage.
The driving transistor M3 may be a P-type transistor. In the first stage, a larger first voltage V1 may be written to the gate of the driving transistor M3, to turn off the driving transistor M3 and prevent the voltage on the driving transistor M3 from flowing to the light-emitting element 30. Therefore, the light-emitting element 30 may be prevented from emitting light in the first stage, solving the problem of screen flickering in the power-on and power-off stages of the display device.
In some embodiments, the first voltage V1 may be smaller than or equal to the black state voltage VGMP. When the voltage required to write is larger, the power consumption may be larger. Therefore, in the first stage, the voltage written to the gate of the driving transistor may be controlled to be smaller than or equal to the black-state voltage VGMP, to avoid excessive power consumption.
In some embodiment, as shown in
In the first stage, the bias transistors M8 and the threshold compensation transistors M5 in each row of pixel circuits 10 may be turned on.
The bias signal line DVH may be electrically connected to the display driving chip 200 of the display device. In the first stage, the display driving chip 200 may provide the first voltage V1 to the bias signal line DVH.
In the present embodiment, in the first stage, the bias transistor M8 and the threshold compensation transistor M5 may be turned on, and the first voltage V1 on the bias signal line DVH may be transmitted to the first electrode of the driving transistor M3 through the bias transistor M8, and then transmitted to the gate of the driving transistor M3 through the threshold compensation transistor M5, such that the driving transistor M3 is turned off in the first stage.
For example, in one embodiment, as shown in
For example, in one embodiment, in the first stage, the first voltage V1 provided by the display driving chip 200 to the bias signal line DVH may be equal to the black state voltage VGMP.
In some embodiments, the bias transistors M8 in each row of pixel circuits 10 may be turned on in the first stage.
For example, in one embodiment, as shown in
The signal output by the plurality of scan shift circuits 50 may be used to control the state of the switching transistors in the pixel circuits 20. For example, the switching transistors may include at least one of the data writing transistor M2, the threshold compensation transistor M5, the reset transistor M4, the initialization transistor M7, or the bias transistor M8 as shown in
In one embodiment, for example, as shown in
As shown in
As shown in
The first A potential signal line VGLa may be used to provide an enabling voltage of the bias transistor M8. For example, the bias transistor M8 may be a P-type transistor, and the enabling voltage provided by the first A potential signal line VGLa may be the low voltage vgl. The voltages provided by the first A potential signal line VGLa and the first potential signal line VGL may be the same.
Each first scan shift circuit 51 may have a circuit structure shown in
As shown in
In one embodiment, in the first stage, since the first A scan start signal line STV* transmits the enabling voltage, the second A output transistor T2a may be turned on, such that the first scan shift circuit 51 outputs the low voltage vgl on the first A potential signal line VGLa to control the bias transistor M8 to be turned on in the first stage.
For example, as shown in
When no signal is input to the first scan shift circuit 51 (for example, in the initial state), the potential inside the first scan shift circuit 51 may default to the ground potential GND. As shown in
For example, as shown in
In some embodiments, as shown in
The second A potential signal line VGHa may be used to provide a disabling voltage of the bias transistor M8. For example, the bias transistor M8 may be a P-type transistor, and the disabling voltage provided by the second A potential signal line VGHa may be the high voltage vgh. The voltages provided by the second A potential signal line VGHa and the second potential signal line VGH may be the same.
As shown in
In the present disclosure, by setting the second A setting transistor T7a, the state of the second A setting transistor T7a may be flexibly controlled according to needs, thereby improving the flexibility of the circuit.
For example, as shown in
The above are some examples in which the bias transistors M8 in each row of pixel circuits 10 are turned on in the first stage. It should be noted that, in various embodiments of the present disclosure, the bias transistors M8 in each row of pixel circuits 10 may be turned on in the first stage by using different manners which include, but are not limited to, the above examples.
In some embodiments, the threshold compensation transistors M5 in each row of pixel circuits 10 may be turned on in the first stage.
In one embodiment, as shown in
As shown in
As shown in
The gate of the second B setting transistor T7b may be electrically connected to the second B control signal line RST_S2N. The first electrode of the second B setting transistor T7b may be electrically connected to the second B potential signal line VGHb. The second electrode of the second B setting transistor T7b may be electrically connected to the gate of the second B output transistor T2b.
The first B potential signal line VGLb may be used to provide a disabling voltage of the threshold compensation transistor M5, and the second B potential signal line VGHb may be used to provide the enabling voltage of the threshold compensation transistor M5. For example, in one embodiment, the threshold compensation transistor M5 may be N-type, the disabling voltage provided by the first B potential signal line VGLb may be the low voltage vgl. and the enabling voltage provided by the second B-potential signal line VGHb may be the high voltage vgh. The voltages provided by the first B potential signal line VGLb and the first potential signal line VGL may be the same. The voltages provided by the second B potential signal line VGHb and the second potential signal line VGH may be the same.
Each second scan shift circuit 52 may have a circuit structure shown in
As shown in
For the N-type threshold compensation transistor M5, for example, as shown in
In the present embodiment, in the first stage, since the second B scan start signal line STV_S2N has the disabling voltage and the second B control signal line RST_S2N has the enabling voltage, the second B setting transistor T7b may be turned on, and the second B output transistor T2b may be turn off, to make the second scan shift circuit 52 output the high voltage vgh on the second B potential signal line VGHb. Therefore, the N-type threshold compensation transistor M5 may be turned on in the first stage.
For example, as shown in
When no signal is input to the second scan shift circuit 52 (for example, in the initial state), the potential inside the second scan shift circuit 52 may default to the ground potential GND. In the first stage, when the voltage on the clock signal line XCK_S2 jumps to low voltage for the first time, the transistor T1b may be turned on, and the high voltage vgh on the second B scan start signal line VGHb may be input to the second scan line S2N. Within a data refresh frame, there may be usually multiple transitions of the signals on the clock signal line CK_S2 and the clock signal line XCK_S2. Therefore, the duration for which all the second scan shift circuit 52 output the high voltage vgh may be smaller than the duration of one data refresh frame.
For example, as shown in
In some other embodiments, as shown in
The P-type threshold compensation transistor M5 may be controlled still using the second scan shift circuits shown in
Different from the control timing of the N-type threshold compensation transistor M5, for the P-type threshold compensation transistor M5, for example, as shown in
In the present embodiment, in the first stage, since the second B scan start signal line STV_S2N has the enabling voltage, the second B output transistor T2b may be turned on, thereby causing the second scan shift circuit 52 to output the low voltage on the first A potential signal line VGLa and controlling the threshold compensation transistor M5 to be turned on in the first stage.
In one embodiment, the duration of all the second scan shift circuits 52 outputting the low voltage vgl may be smaller than the duration of one data refresh frame, which is similar to the above example in which the duration of all the first scan shift circuits 51 outputting the low voltage vgl is smaller than the duration of one data refresh frame.
In some embodiments, for the P-type threshold compensation transistor M5, the transistor T7b shown in
The above embodiments in which the threshold compensation transistors M5 in each row of pixel circuits 10 are all be turned on in the first stage are used as examples to illustrate the present disclosure, and do not limit the scope of the present disclosure. The threshold compensation transistors M5 in each row of pixel circuits 10 may all be turned on in the first stage using suitable manners which include, but are not limited to, the above examples.
In some embodiments, as shown in
In the first stage, the bias transistors M8 of each row of pixel circuits 10 may be all turned on, the threshold compensation transistors M5 of each row of pixel circuits 10 may be all turned on, and the reset transistors M4 of each row of pixel circuits 10 may be all turned off.
In this embodiment, the reset transistor M4 may be turned off, which prevents the reset signal on the reset signal line VREF1 from being written to the gate of the driving transistor M3, thereby avoiding affecting the off state of the driving transistor M3 in the first stage.
In some embodiments, in the first stage, the display driving chip 200 may not provide the reset voltage to the reset signal line VREF1. In the display stage, the display driving chip 200 may provide the reset voltage to the reset signal line VREF1. That is, the reset signal line VREF1 may be powered on at the beginning of the display stage and powered off at the end of the display stage.
In some embodiments, the reset transistors M4 in each row of pixel circuits 10 may all be turned off in the first stage.
As shown in
As shown in
As shown in
The gate of the third C setting transistor T7c may be electrically connected to the third C control signal line RST_S1N. The first electrode of the third C setting transistor T7c may be electrically connected to the third C potential signal line VGHc. The second electrode of the third C setting transistor T7c may be electrically connected to the gate of the third C output transistor T2c.
The first C potential signal line VGLc may be used to provide a disabling voltage of the reset transistor M4, and the second C potential signal line VGHc may be used to provide the enabling voltage of the reset transistor M4. For example, in one embodiment, the reset transistor M4 may be N-type, the disabling voltage provided by the first C potential signal line VGLc may be the low voltage vgl. and the enabling voltage provided by the second C potential signal line VGHc may be the high voltage vgh. The voltages provided by the first C potential signal line VGLc and the first potential signal line VGL may be the same. The voltages provided by the second C potential signal line VGHc and the second potential signal line VGH may be the same.
Each third scan shift circuit 53 may have a circuit structure shown in
For the N-type reset transistor M4, for example, as shown in
The P-type reset transistor M4 may be controlled still using the second scan shift circuits shown in
Different from the control timing of the N-type reset transistor M4, for the P-type reset transistor M4, for example, as shown in
The above embodiments in which the reset transistors M4 in each row of pixel circuits 10 are all be turned off in the first stage are used as examples to illustrate the present disclosure, and do not limit the scope of the present disclosure. The reset transistors M4 in each row of pixel circuits 10 may all be turned off in the first stage using suitable manners which include, but are not limited to, the above examples.
In previous embodiments, in the first stage, the bias transistor M8 may be turned on, and the first voltage V1 may be written to the gate of the driving transistor M3 through the threshold compensation transistor M5. In some other embodiments, in the first stage, the first voltage V1 may be written to the gate of the driving transistor M3 through the reset transistor M4.
In some embodiments, as shown in
In the first stage, the reset transistors M4 in each row of pixel circuits 10 may all be turned on.
As shown in
In this embodiment, in the first stage, the reset transistor M4 may be turned on, and the reset signal line VREF1 may provide the first voltage V1 which is transmitted to the gate of the driving transistor M3 through the reset transistor M4, such that the driving transistor M3 is turned off in the first stage.
For example, as shown in
For example, in the first stage, the first voltage V1 provided by the display driving chip 200 to the reset signal line VREF1 may be between the voltage Vdd and the black state voltage VGMP. The voltage of the first power line PVDD during the display stage may be Vdd.
In some embodiments, the reset transistors M4 in each row of pixel circuits 10 may all be turned on in the first stage.
In one embodiment, the third scan shift circuit 53 shown in
For the N-type reset transistor M4, for example, as shown in
In this embodiment, in the first stage, since the third C scan start signal line STV_S1N has the disabling voltage and the third C control signal line RST_S1N has an enabling voltage, the third C setting transistor T7c may be turned on, and the third C output transistor T2c may be turned off, thereby causing the third scan shift circuit 53 to output the high voltage vgh on the second C-potential signal line VGHb. Therefore, the N-type reset transistor M4 may be turned on in the first stage.
The P-type reset transistor M4 may be controlled still using the second scan shift circuits shown in
Different from the control timing of the N-type reset transistor M4, for the P-type reset transistor M4, for example, as shown in
In one embodiment, for the P-type reset transistor M4, in the first stage, as shown in
As shown in
The above embodiments in which the reset transistors M4 in each row of pixel circuits 10 are all turned on in the first stage are used as examples to illustrate the present disclosure, and do not limit the scope of the present disclosure. The reset transistors M4 in each row of pixel circuits 10 may all be turned on in the first stage using suitable manners which include, but are not limited to, the above examples.
In the first stage, when the reset transistor M4 is used to write the first voltage to the gate of the driving transistor M3, the threshold compensation transistors M5 of each row of pixel circuits 10 may all be turned on or all turned off.
In one embodiment, for example, when the threshold compensation transistors M5 of each row of pixel circuits 10 are turned on, the threshold compensation transistor M5 and the reset transistor M4 may be in the same state in the first stage, and the threshold compensation transistor M5 and the reset transistor M4 may share a scan shift circuit.
In another embodiment, in the first stage, the threshold compensation transistors M5 of each row of pixel circuits 10 may be all turned off.
In some embodiments, the threshold compensation transistors M5 in each row of pixel circuits 10 may be turned off in the first stage.
For example, the second scan shift circuit as shown in
For the N-type threshold compensation transistor M5, in the first stage, the display driving chip may provide the enabling voltage (such as low voltage vgl) of the second B output transistor T2b to the second B scan start signal line STV_S2N, and provide the disabling voltage (for example, a high voltage vgh) of the second B setting transistor T7b to the second B control signal line RST_S2N, thereby controlling the N-type threshold compensation transistor M5 to turn off in the first stage.
For the P-type threshold compensation transistor M5, as shown in
For the P-type threshold compensation transistor M5, the transistor T7b shown in
The above embodiments in which the threshold compensation transistors M5 in each row of pixel circuits 10 are all turned off in the first stage are used as examples to illustrate the present disclosure, and do not limit the scope of the present disclosure. The threshold compensation transistors M5 in each row of pixel circuits 10 may all be turned off in the first stage using suitable manners which include, but are not limited to, the above examples.
In some embodiments, as shown in
As shown in
As shown in
As shown in
The clock signal line XCK_S4 may be used to alternately provide the enabling voltage and the disabling voltage of the data writing transistor M2. For example, for the P-type data writing transistor M2, the enabling voltage may be the low voltage vgl, and the disabling voltage may be the high voltage vgh.
Each fourth scan shift circuit 54 may have a circuit structure shown in
As shown in
In this embodiment, in the first stage, since the fourth D scan start signal line STV_SP maintains a high voltage, the fourth D output transistor T8d may be prevented from being turned on in the first stage, thereby enabling each fourth scan shift circuit 54 to output the high voltage in the first stage to control the data writing transistor M2 to turn off in the first stage.
In some embodiments, in the first stage, the display driving chip 200 may provide the reference voltage VCI of the display driving chip 200 to the data line DATA, and other voltages provided by the display driving chip may be converted from the reference voltage VCI. In the first stage, the reference voltage VCI may be directly provided to the data line, Therefore, the conversion process may be reduced to improve efficiency.
In other embodiments, to improve the flickering problem caused by the leakage of the data writing transistor in the first stage, the display driving chip 200 may provide the black state voltage VGMP to the data line DATA in the first stage.
In some embodiments, as shown in
In the first stage, the display driving chip may not provide power supply voltage to the first power line PVDD and the second power line PVEE. In the display stage, the display driving chip may provide power supply voltage to the first power line PVDD and the second power line PVEE. During the display stage, the display driving chip may provide positive voltage to the first power line PVDD and negative voltage to the second power line PVEE.
And/or, as shown in
The first power line PVDD, the second power line PVEE, and the initialization signal line VREF2 may have low potential GND in the first stage, and the first power line PVDD, the second power line PVEE, and the initialization signal line VREF2 may start to provide power normally during the display stage.
The situation corresponding to timing shown in
The situation corresponding to timing shown in
The situation corresponding to timing shown in
The situation corresponding to timing shown in
The present disclosure also provides a driving method of a display device.
As shown in
One pixel circuit 20 may include a driving transistor M3, and light-emitting control transistors M1 and M6. The driving transistor M3 may be used to generate a driving current to drive the corresponding light-emitting element 30 to emit light, and the magnitude of the driving current may affect the brightness of the corresponding light-emitting element 30. The light-emitting control transistors M1 and M6 may be used to control the corresponding light-emitting element 30 to enter a light-emitting stage. For example, when the light-emitting control transistors M1 and M6 are turned on, the driving current generated by the driving transistor M3 may be transmitted to the corresponding light-emitting element 30, and the corresponding light-emitting element 30 may emit light.
The driving process of the display panel may include a first stage and a display stage, and the first stages may be located at least before or after the display stage.
As shown in
S191, in the first stage, controlling at least one of the light-emitting control transistors and the driving transistors in each row of pixel circuits to turn off.
The duration of the first stage may be t, and the data refresh frequency of the pixel circuits in the display stage may be f, where t≤1/f.
In the present disclosure, by controlling the duration of the power-on and power-off stages within one refresh frame, the time required for power-on and power-off may be shortened, fast power-on and power-off may be achieved, and the user experience may be improved. Further, in the first stage, the light-emitting control transistors and driving transistors of each row of pixel circuits may be all turned off. Therefore, a double insurance to prevent the light-emitting elements from emitting light may be provided, thereby helping to avoid the flash screen of the display device during the power-on and power-off stages.
In some embodiments, the display panel may further include a plurality of cascaded emission shift circuits. The plurality of emission shift circuits may be electrically connected to the gates of the emission control transistors through the emission control signal lines. The plurality of emission shift circuits may include a first emission shift circuit, and the first emission shift circuit may be electrically connected to the emission start signal line.
The first emission shift circuit may include a first input transistor, a first setting transistor, and a first output transistor. The first input transistor may be electrically connected between the emission start signal line and the gate of the first output transistor, the first electrode of the first output transistor may be electrically connected to the first potential signal line, and the second electrode of the first output transistor may be electrically connected to the light-emitting control signal line.
The gate of the first setting transistor may be electrically connected to the first control signal line, the first electrode of the first setting transistor may be electrically connected to the second potential signal line, and the second electrode of the first setting transistor may be electrically connected to the gate of the first output transistor.
The first potential signal line may be used to provide an enabling voltage of the light-emitting control transistors, and the second potential signal line may be used to provide a disabling voltage of the light-emitting control transistors.
The display device may further include a display driving chip.
The driving method may include: in the first stage, the display driving chip provides the disabling voltage of the first output transistor to the emission start signal line connected to it, and provides the enabling voltage of the first setting transistor to the first control signal line.
In some embodiments, the light-emitting control transistors and the driving transistors may be electrically connected between the first power line and the first electrode of the light-emitting element.
The driving method may include: in the first stage, a first voltage is written to the gates of the driving transistors in each row of pixel circuits. The first voltage may be larger than or equal to the voltage of the first power line during the display stage.
In some embodiments, the first voltage may be smaller than or equal to the black state voltage.
In some embodiments, the pixel circuit may further include a bias transistor and a threshold compensation transistor. The first electrode of the bias transistor may be electrically connected to the bias signal line, and the second electrode of the bias transistor may be electrically connected to the first electrode of the driving transistor. The first electrode of the threshold compensation transistor may be electrically connected to the second electrode of the driving transistor, and the second electrode of the threshold compensation transistor may be electrically connected to the gate of the driving transistor.
In the first stage, the bias transistors and the threshold compensation transistors in each row of pixel circuits may all be turned on.
The display device may further include a display driving chip.
The driving method may further include: the display driving chip provides a first voltage to the bias signal line.
In some embodiments, the display panel may also include a plurality of cascaded first scan shift circuits. The first scan shift circuits may be electrically connected to the gate of the bias transistors through the first scan lines. The first scan shift circuits may include a first A scan shift circuit. The first A scan shift circuit may be electrically connected to the first A scan start signal line.
The first A scan shift circuit includes a second A input transistor and a second A output transistor. The second A input transistor may be electrically connected between the first A scan shift circuit and the gate of the second A output transistor. The first electrode of the second A output transistor may be electrically connected to the first A potential signal line, and the second electrode of the second A output transistor may be electrically connected to the first scan line.
The first A potential signal line may be used to provide an disabling voltage of the bias transistor.
The display device may further include a display driving chip.
The driving method may include: in the first stage, the display driving chip provides the disabling voltage of the second A output transistor to the first A scan start signal line.
In some embodiments, the first A scan shift circuit may also include a second A setting transistor. The gate of the second A setting transistor may be electrically connected to the second A control signal line. The first electrode of the second A setting transistor may be electrically connected to the second A potential signal line, and the second electrode of the second A setting transistor may be electrically connected to the gate of the second A output transistor.
The second A potential signal line may be used to provide the disabling voltage for the bias transistor.
The driving method may include: in the first stage, the display driving chip provides the disabling voltage of the second A setting transistor to the second A control signal line.
In some embodiments, the threshold compensation transistor may be an N-type transistor.
The display panel may further include a plurality of cascaded second scan shift circuits, and the second scan shift circuits may be electrically connected to the gates of the threshold compensation transistors through the second scan lines. The second scan shift circuits may include a second B scan shift circuit. The second B scan shift circuit may be electrically connected to the second B scan start signal line.
The second B scan shift circuit may include a second B input transistor, a second B setting transistor, and a second B output transistor. The second B input transistor may be electrically connected between the second B scan start signal line and the gate of the second B output transistor. The first electrode of the second B output transistor may be electrically connected to the second scan line, and the second electrode of the second B output transistor may be electrically connected to the second scan line.
The gate of the second B setting transistor may be electrically connected to the second B control signal line, the first electrode of the second B setting transistor may be electrically connected to the second B potential signal line, and the second electrode of the second B setting transistor may be electrically connected to the gate of the second B output transistor.
The first B potential signal line may be used to provide the disabling voltage to the threshold compensation transistor, and the second B potential signal line may be used to provide the enabling voltage of the threshold compensation transistor.
The display device may also include a display driving chip.
The driving method may include: in the first stage, the display driving chip provides the disabling voltage of the second B output transistor to the second B scan start signal line, and provides the enabling voltage of the second B setting transistor to the second B control signal line.
In some other embodiments, the threshold compensation transistor may be a P-type transistor.
The display panel may further include a plurality of cascaded second scan shift circuits, and the second scan shift circuits may be electrically connected to the gates of the threshold compensation transistors through the second scan lines. The second scan shift circuits may include a second B scan shift circuit. The second B scan shift circuit may be electrically connected to the second B scan start signal line.
The second B scan shift circuit may include a second B input transistor and a second B output transistor. The second B input transistor may be electrically connected between the second B scan start signal line and the gate of the second B output transistor. The first electrode of the second B output transistor may be electrically connected to the first B potential signal line, and the second electrode of the second B output transistor may be electrically connected to the second scan line.
The first B potential signal line may be used to provide the enabling voltage of the threshold compensation transistor.
The display device may also include a display driving chip.
The driving method may include: in the first stage, the display driving chip provides the enabling voltage of the second B output transistor to the second B scan start signal line.
In some embodiments, the pixel circuit may also include a reset transistor, and the reset transistor may be electrically connected between the gate of the driving transistor and the reset signal line.
The driving method may include: in the first stage, controlling the reset transistors of each row of pixel circuits to be turned off.
In some embodiments, the driving method may include: in the first stage, the display driving chip does not provide the reset voltage to the reset signal line, and in the display stage, the display driving chip provides the reset voltage to the reset signal line.
In some embodiments, the pixel circuit may also include a reset transistor, and the reset transistor may be electrically connected between the gate of the driving transistor and the reset signal line.
In the first stage, the reset transistors in each row of pixel circuits may be all turned on.
The display device may also include a display driving chip.
The driving method may include: in the first stage, the display driving chip provides a first voltage to the reset signal line.
In some embodiments, the reset transistor may be an N-type transistor.
The display panel may further include a plurality of cascaded third scan shift circuits, and the third scan shift circuits may be electrically connected to the gates of the reset transistors through third scan lines. The third scan shift circuits may include a third C scan shift circuit, and the third C scan shift circuit may be electrically connected to the third C scan start signal line.
The third C scan shift circuit may include a third C input transistor, a third C setting transistor, and a third C output transistor. The third C input transistor may be electrically connected between the third C scan start signal line and the gate of the third C output transistor. The first electrode of the third C output transistor may be electrically connected to the first C potential signal line, and the second electrode of the third C output transistor may be electrically connected to the third scan line.
The gate electrode of the third C setting transistor may be electrically connected to the third C control signal line, the first electrode of the third C setting transistor may be electrically connected to the second C potential signal line, and the second electrode of the third C setting transistor may be electrically connected to the gate of the third C output transistor.
The first C potential signal line may be used to provide the disabling voltage of the reset transistor, and the second C potential signal line may be used to provide the disabling voltage of the reset transistor.
The display device may also include a display driving chip.
The driving method may include: in the first stage, the display driving chip provides the disabling voltage of the third C output transistor to the third C scan start signal line, and provides the disabling voltage of the third C setting transistor to the third C control signal line.
In some other embodiments, the reset transistor may be a P-type transistor.
The display panel may further include a plurality of cascaded third scan shift circuits, and the third scan shift circuits may be electrically connected to the gates of the reset transistors through third scan lines. The third scan shift circuits may include a third C scan shift circuit, and the third C scan shift circuit may be electrically connected to the third C scan start signal line.
The third C scan shift circuit may include a third C input transistor and a third C output transistor. The third C input transistor may be electrically connected between the third C scan start signal line and the gate of the third C output transistor. The first electrode of the third C output transistor may be electrically connected to the first C potential signal line, and the second electrode of the third C output transistor may be electrically connected to the third scan line.
The first C potential signal line may be used to provide the disabling voltage of the reset transistor.
The display device may also include a display driving chip.
The driving method may include: in the first stage, the display driving chip provides the enabling voltage of the third C output transistor to the third C scan start signal line.
In some embodiments, the pixel circuit may also include a threshold compensation transistor. The first electrode of the threshold compensation transistor may be electrically connected to the second electrode of the driving transistor, the second electrode of the threshold compensation transistor may be electrically connected to the gate electrode of the driving transistor, and the gate electrode of the threshold compensation transistor may be electrically connected to the third scan shift circuit.
In some embodiment, in the first stage, the threshold compensation transistors in each row of pixel drive circuits may be turned off.
In some embodiments, the pixel circuit may further include a data writing transistor, and the data writing transistor may be electrically connected between the first electrode of the driving transistor and the data line.
The display panel may further include a plurality of cascaded fourth scan shift circuits. The fourth scan shift circuits may be electrically connected to the gates of the data writing transistors through the fourth scan lines. The fourth scan shift circuits may include a fourth D scan shift circuit. The fourth D scan shift circuit may be electrically connected to the fourth D scan start signal line.
The fourth D scan shift circuit may include a fourth D input transistor and a fourth D output transistor. The fourth input transistor may be electrically connected between the fourth scan start signal line and the gate of the fourth output transistor. The first electrode of the fourth D output transistor may be electrically connected to the clock signal line, and the second electrode of the fourth D output transistor may be electrically connected to the fourth scan line.
The clock signal line may be used to alternately provide the enabling voltage and the disabling voltage to the data writing transistor.
The display device may also include a display driving chip.
The driving method may include: in the first stage, the display driving chip provides the disabling voltage of the fourth D output transistor to the fourth D scan start signal line.
In some embodiments, the driving method may include: in the first stage, the display driving chip provides the reference voltage of the display driving chip to the data line.
In some embodiments, the light-emitting control transistors, the driving transistor and the light-emitting element may be connected in series between the first power line and the second power line.
The display device may further include a display driving chip.
The driving method may include: in the first stage, the display driving chip does not provide power voltage to the first power line and the second power line; and, in the display stage, the display driving chip provides power voltage to the first power line and the second power line.
In some embodiments, the pixel circuit may also include an initialization transistor. The initialization transistor may be electrically connected between the initialization signal line and the first electrode of the light-emitting element. In the first stage, the display driving chip may not provide the initialization voltage to the initialization signal line. In the display stage, the display driving chip may provide the initialization voltage to the initialization signal line.
In some embodiments, the pixel circuit may have multiple data refresh frequencies during the display stage, and f may be the maximum value among the multiple data refresh frequencies.
In various embodiments, the display device may be, but is not limited to, a cell phone, a wearable device, a computer, a television, a vehicle display device, or another device with a display function, which is not limited in the present disclosure.
In this document, relational terms such as “first” and “second” are only used to distinguish one entity or operation from another entity or operation and do not necessarily require or imply that there is a relationship between these entities or operations. There is no such actual relationship or sequence. Furthermore, the terms “comprises,” “comprises,” or any other variations thereof are intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also those not expressly listed other elements, or elements inherent to the process, method, article or equipment. Without further limitation, an element defined by the statement “comprises a . . . ” does not exclude the presence of additional identical elements in a process, method, article, or apparatus that includes the stated element.
Various embodiments have been described to illustrate the operation principles and exemplary implementations. It should be understood by those skilled in the art that the present disclosure is not limited to the specific embodiments described herein and that various other obvious changes, rearrangements, and substitutions will occur to those skilled in the art without departing from the scope of the disclosure. Thus, while the present disclosure has been described in detail with reference to the above described embodiments, the present disclosure is not limited to the above described embodiments, but may be embodied in other equivalent forms without departing from the scope of the present disclosure, which is determined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202311707873.1 | Dec 2023 | CN | national |
