Patent Application
20150206472
This application claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2014-0006906 filed on Jan. 20, 2014 in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety.
The present invention relates to a display device, and more particularly, to a display device and a driving method thereof.
A liquid crystal display (LCD) generally includes two display panels and a liquid crystal layer interposed interbetween The liquid crystal display generates an electric field in the liquid crystal layer by applying a DC voltage to the two electrodes, and obtains a desired image by adjusting the transmittance of light passing through the liquid crystal layer by adjusting the intensity of the electric field. The liquid crystal display may have a response time required to increase or decrease luminance thereof according to a change of a gray value of a received image signal. The response time includes a rising time and a falling time. The rising time is a time required to increase the luminance when a gray value to be displayed is increased from a previous frame to a current frame. The falling time is a time required to decrease the luminance when a gray value to be displayed is decreased from the previous frame to the current frame. The rising time and the falling time may be asymmetric depending on a type of the liquid crystal in the liquid crystal display. Asymmetry between the rising time and the falling time may cause a flicker effect when a motion picture is displayed in the liquid crystal display.
According to an exemplary embodiment of the present invention, a display device is provided. The display device includes a plurality of pixels, a data driver, a signal controller, and a data processor. The data driver is configured to apply a first data voltage to a first data line of a plurality of data lines. The first data line is connected to a first pixel of the plurality of pixels. The signal controller is configured to transfer an image data signal and a data control signal for controlling an operation of the data driver. The image data signal includes a first image signal and a second image signal. The data processor is configured to detect a first region including a moving pattern in the first image signal, to apply a first dynamic capacitance control (DCC) to the first region, to apply a second DCC to a second region other than the moving pattern region, to generate the second image signal by combining the first region to which the first DCC is applied and the second region to which the second DCC is applied, and to transfer the second image signal to the signal controller. During a first time period, the first data voltage is higher than a reference data voltage corresponding to a first luminance to be displayed by a first predetermined level, or during a second time period, the first data voltage is lower than the reference voltage by a second predetermined level. A rising time and a falling time of luminance of the first pixel are the same as each other when the first DCC is applied, and the rising time and the falling time of the luminance of the first pixel are not controlled when the second DCC is applied.
The data processor may include a frame memory, a moving pattern detector, a first DCC unit, and a second DCC unit. The frame memory may be configured to store the first image signal in a frame unit. The moving pattern detector may be configured to divide an image signal of a current frame into a plurality of current detection blocks. The moving pattern detector may be configured to divide an image signal of a previous frame stored in the frame memory into a plurality of previous detection blocks, to detect a detection block including the moving pattern among the plurality of current detection blocks, and to transfer the plurality of current detection blocks to the first DCC unit or the second DCC unit. The first DCC unit may be configured to perform the first DCC on the plurality of current detection blocks transferred from the moving pattern detector. The second DCC unit may be configured to perform the second DCC on the plurality of current detection blocks transferred from the moving pattern detector.
The data processor may further include a data buffer. The data buffer may be configured to hold the first image signal in the frame unit and to transfer the held first image signal to the frame memory and the moving pattern detector.
The plurality of current detection blocks and the plurality of previous detection blocks may have the same size.
The moving pattern detector may be configured to determine whether a first difference between an average luminance of the plurality of current detection blocks and an average luminance of the plurality of previous detection blocks is smaller than a first reference value, and to transfer the plurality of current detection blocks to the second DCC unit when the first difference is larger than or equal to the first reference value.
The moving pattern detector may be configured to determine whether a second difference between luminance of each pixel in the plurality of current detection blocks and luminance of each pixel in the plurality of previous detection blocks is larger than a second reference value when the first difference is smaller than the first reference value.
The moving pattern detector may be configured to transfer the plurality of current detection blocks to the second DCC unit when the second difference is smaller than or equal to the second reference value.
The moving pattern detector may be configured to transfer the plurality of second detection blocks to the first DCC unit when the second difference is larger than the second reference value.
Each of the plurality of pixels may include a pixel electrode, a common electrode, and a liquid crystal layer. A data voltage may be applied to the pixel electrode. A common voltage may be applied to the common electrode. The liquid crystal layer may be provided between the pixel electrode and the common electrode.
The rising time may be a time required to increase the luminance of the first pixel from 10% to 90% of an amount of the increased luminance.
After the first time period of the rising time, the first data voltage may be changed to the reference data voltage when the luminance of the first pixel is substantially equal to the first luminance to be displayed.
The falling time may be a time required to decrease the luminance of the first pixel from 90% to 10% of an amount of the decreased luminance.
After the second time period of the falling time, the first data voltage may be changed to the reference voltage when the luminance of the first pixel is substantially equal to the first luminance to be displayed.
According to an exemplary embodiment of the present invention, a driving method of a display device is provided. The driving method includes receiving first frame data, receiving second frame data after the first frame data have been received, dividing the received first frame data into a plurality of first detection blocks, dividing the second frame data into a plurality of second detection blocks, detecting a detection block including a moving pattern among the plurality of second detection blocks, applying a first DCC to the detection block including the moving pattern, and applying a second DCC to a detection block from among the plurality of second detection blocks in which the moving pattern is not included. A first data voltage applied to a first pixel in the display device is higher than a reference voltage corresponding to a first luminance to be displayed by a first predetermined level, or lower than the reference voltage by a second predetermined level. A rising time and a falling time of luminance of the first pixel are the same as each other when the first DCC is applied, and the rising time and the falling time of the luminance of the first pixel are not controlled when the second DCC is applied.
The driving method of the display device may further include storing the first frame data in a frame unit.
The plurality of first detection blocks and the plurality of second detection blocks may have the same size.
The detecting of the detection block including the moving pattern among the plurality of second detection blocks may include determining whether a first difference between an average luminance of the plurality of second detection blocks and an average luminance of the plurality of first detection blocks is smaller than a first reference value, and applying the second DCC to the plurality of second detection blocks when the first difference is larger than or equal to the first reference value.
The detecting of the detection block including the moving pattern among the plurality of detection blocks may further include determining whether a second difference between luminance of each pixel in the plurality of second detection blocks and luminance of each pixel in the plurality of first detection blocks is larger than a second reference value.
The detecting of the detection block including the moving pattern among the plurality of detection blocks may further include applying the second DCC when the second difference is equal to or smaller than the second reference value.
The detecting of the detection block including the moving pattern among the plurality of detection blocks may further include applying the first DCC when the second difference is larger than the second reference value.
According to an exemplary embodiment of the present invention, a data processor in a display device is provided. The data processor includes a frame memory, a moving pattern detector, a first DCC unit, a second DCC unit, and a data output section. The data processor is configured to store a first image signal in a frame unit. The moving pattern detector is configured to divide an image signal of a current frame into a plurality of current detection blocks, to divide an image signal of a previous frame stored in the frame memory into a plurality of previous detection blocks, to detect a detection block including a moving among the plurality of current detection blocks, and to transfer the plurality of current detection blocks to the first DCC unit or the second DCC unit depending on whether the plurality of current detection blocks includes the moving pattern. The first DCC unit is configured to perform a first DCC on the plurality of current detection blocks transferred from the moving pattern detector. The second DCC unit is configured to perform a second DCC on the plurality of current detection blocks transferred from the moving pattern detector. The data output section is configured to generate a second image signal by combining the output image signals from the first DCC unit and the second DCC unit.
A more complete appreciation of the present disclosure and many of the attendant aspects thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention may be modified in various forms, and is not limited to the exemplary embodiments disclosed herein.
In the exemplary embodiments, like reference numerals may designate the same constituent element throughout the specification and thus, description about the same constituent element may be omitted.
Referring to
The display unit 400 includes a plurality of signal lines having a plurality of scanning lines S1 to Sn and a plurality of data lines D1 to Dm, and a plurality of pixels PXs. The plurality of pixels PXs are connected to the plurality of signal lines S1 to Sn and D1 to Dm, respectively, and are arranged in a matrix form. The plurality of scanning lines S1 to Sn are substantially extended in a row direction and are substantially parallel to each other. The plurality of data lines D1 to Dm are substantially extended in a column direction and are substantially parallel to each other.
The display unit 400 may be a liquid crystal panel assembly. For example, referring to
At least one polarizer (not shown) for polarizing light may be attached to the outside surface of the display unit 400.
Referring back to
To reduce a response time of a liquid crystal in the display device, a DCC (e.g., first DCC or second DCC) generates a data voltage corresponding to a higher gray value than an original gray value to be displayed by a predetermined value or a lower gray value than the original gray value to be displayed by a predetermined value. The response time of the liquid crystal includes a rising time in which luminance rises from a low gray value to a high gray value and a falling time in which the luminance drops from the high gray value to the low gray value.
For example, when a data voltage corresponding to the low gray value is applied to a particular pixel in a previous frame and a data voltage corresponding to the high gray value is applied to the pixel in the current frame, the DCC (e.g., first DCC or second DCC) outputs a data voltage corresponding to a higher gray value than the original gray value to be displayed in the current frame to reduce the rising time of the luminance at the pixel. Further, when a data voltage of the high gray is applied to a particular pixel in a previous frame and a data voltage corresponding to the low gray is applied to the pixel in the current frame, the DCC (e.g., first DCC or second DCC) outputs a data voltage corresponding to the lower gray value than the original gray value to be displayed in the current frame to reduce the falling time of the luminance at the pixel.
Although the data processor 500 and the signal controller 100 may be separately provided, as shown in
The signal controller 100 receives the second image signal ImS' and an input control signal for controlling the display of the second image signal ImS′. The input control signal includes a data enable signal DE, a horizontal synchronizing signal Hsync, a vertical synchronization signal Vsync, and a main clock signal MCLK.
The signal controller 100 transfers an image data signal DAT and a data control signal CONT2 to the data driver 300. The data control signal CONT2, which is a signal for controlling an operation of the data driver 300, may include a horizontal synchronization start signal STH for indicating a transmission start of the image data signal DAT, a load signal LOAD for directing an output of a gray voltage to the data lines D1 to Dm, and a data clock signal HCLK. The data control signal CONT2 may further include an inversion signal RVS for inverting a polarity in voltage of the image data signal DAT with respect to the common voltage Vcom.
The signal controller 100 transfers a scan control signal CONT1 to the scan driver 200. The scan control signal CONT1, which is a signal for controlling an operation of the scan driver 200, may include a scanning start signal STV of the scan driver 200 and at least one clock signal CKV for controlling an output of a gate-on voltage. The scan control signal CONT1 may further include an output enable signal OE for controlling a duration time of the gate-on voltage.
The data driver 300 is connected to a plurality of data lines D1 to Dm disposed at the display unit 400 and selects the gray voltage corresponding to the image data signal DAT. For example, the data driver 300 may generate the gray voltages with respect to the entire grayscale by dividing a predetermined number of reference gray voltages, and the data driver 300 may select a gray voltage corresponding to the image data signal DAT from among them. The data driver 300 applies the selected gray voltage to the data lines D1 to Dm as the data voltage.
The scan driver 200 is connected to the plurality of scanning lines S1 to Sn disposed at the display unit 400 and applies scanning signals to the plurality of scanning lines S1 to Sn. The scanning signals are generated by using the gate-on voltage that turns on a switching element (see, e.g., Q of
Each of the signal controller 100, the scan driver 200, the data driver 300, and the data processor 500 may be directly mounted on the display unit 400 in at least one IC chip form, may be mounted on a flexible printed circuit (FPC) film to be attached to the display unit 400 in a tape carrier package (TCP) form, or may be mounted on a separate printed circuit board (PCB). In addition, the signal controller 100, the scan driver 200, the data driver 300, and the data processor 500 may be integrated in the display unit 400 together with the plurality of scanning lines S1 to Sn and the plurality of data lines D1 to Dm.
Hereinafter, a single pixel PX of the display unit 400 will be described. Referring back to
The switching element Q is a three-terminal element such as a thin film transistor or the like provided to a thin film transistor array panel 10. The switching element Q includes a gate terminal connected to a corresponding one of the scanning lines S1 to Sn, an input terminal connected to a corresponding one of the data lines D1 to Dm, and an output terminal connected to the liquid crystal capacitor Clc and the storage capacitor Cst. The thin film transistor includes amorphous silicon or polysilicon.
The thin film transistor may be an oxide thin film transistor (oxide TFT) in which a semiconductor layer is made of an oxide semiconductor.
The oxide semiconductor may include an oxide such as a titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), germanium (Ge), zinc (Zn), gallium (Ga), tin (Sn), indium (In), or the like, or a composite oxide such as zinc oxide (ZnO), indium-gallium-zinc oxide (InGaZnO4), indium-zinc oxide (In—Zn—O), zinc-tin oxide (Zn—Sn—O) indium-gallium oxide (In—Ga—O), indium-tin oxide (In—Sn—O), indium-zirconium oxide (In—Zr—O), indium-zirconium-zinc oxide (In—Zr—Zn—O), indium-zirconium-tin oxide (In—Zr—Sn—O), indium-zirconium-gallium oxide (In—Zr—Ga—O), indium-aluminum oxide (In—Al—O), indium-zinc-aluminum oxide (In—Zn—Al—O), indium-tin-aluminum oxide (In—Sn—Al—O), indium-aluminum-gallium oxide (In—Al—Ga—O), indium-tantalum oxide (In—Ta—O), indium-tantalum-zinc oxide (In—Ta—Zn—O), indium-tantalum-tin oxide (In—Ta—Sn—O), indium-tantalum-gallium oxide (In—Ta—Ga—O), indium-germanium oxide (In—Ge—O), indium-germanium-zinc oxide (In—Ge—Zn—O), indium-germanium-tin oxide (In—Ge—Sn—O), indium-germanium-gallium oxide (In—Ge—Ga—O), titanium-indium-zinc oxide (Ti—In—Zn—O), hafnium-indium-zinc oxide (Hf—In—Zn—O), or the like.
The semiconductor layer includes a channel region in which an impurity is not doped, and source and drain regions which are formed by doping the impurity at both sides of the channel region. Here, the impurity is changed according to a type of the thin film transistor. For example, an N-type impurity or a-P type impurity may exist.
When the semiconductor layer is made of the oxide semiconductor, a separate protective layer may be added to protect the oxide semiconductor from being exposed to the external environment such as high temperature.
The liquid crystal capacitor Clc includes a pixel electrode PE of the thin film transistor array panel 10 and a common electrode CE of the common electrode panel 20 as two terminals, and the liquid crystal layer 15 interposed between the pixel electrode PE and the common electrode CE functions as a dielectric material. The liquid crystal layer 15 has dielectric anisotropy. A pixel voltage is formed by a difference in voltage between the pixel electrode PE and the common electrode CE.
The pixel electrode PE is connected to the switching element Q. The common electrode CE is formed over the entire surface of the common electrode panel 20 to receive the common voltage Vcom. Unlike
The storage capacitor Cst, which is an auxiliary capacitor for the liquid crystal capacitor Clc, may be formed by the pixel electrode PE and a separate signal line (not shown) facing the pixel electrode PE via an insulator. The separate signal line is provided on the thin film transistor array panel 10. and is supplied with a predetermined voltage such as the common voltage Vcom.
A color filter CF may be formed in a partial region of the common electrode CE on the common electrode panel 20. For example, each pixel PX may uniquely display a primary color (e.g., red, green, blue), and may form a desired color by a spatial combination of the primary colors. In addition, each pixel PX may alternately display the primary colors according to time, and may form a desired color by a temporal combination of the primary colors.
As an example of the spatial division, each pixel PX includes the color filter CF that displays one of the primary colors and is formed in a partial region of the common electrode panel 20 corresponding to the pixel electrode PE. However, the color filter CF may be formed on an upper or lower surface of the pixel electrode PE of the thin film transistor array panel 10.
Referring to
The data input section 510 receives a first image signal ImS from the outside. The data input section 510 transfers the first image signal ImS to the data buffer 520.
The data buffer 520 holds the first image signal ImS, and transfers the held first image signal ImS to the frame memory 530 and the moving pattern detector 540. Here, the data buffer 520 may hold the first image signal ImS in a frame unit, and may transfer the first image signal ImS held in the frame unit to the frame memory 530 and the moving pattern detector 540.
The frame memory 530 stores the first image signal ImS transferred from the data buffer 520 in the frame unit. When the moving pattern detector 540 detects a moving pattern in a current frame, the frame memory 530 transfers an image signal of the previous frame, which is stored therein, to the moving pattern detector 540. For example, the image signal of the previous frame may be stored in the frame memory 530.
The moving pattern detector 540 detects the moving pattern by using the image signal (e.g., first image signal ImS) of the current frame transferred from the data buffer 520 with the image signal of the previous frame transferred from the frame memory 530. The moving pattern is a specific pattern that moves with time in the motion picture.
A method for detecting the moving pattern will be described with reference to
Referring to
The moving pattern detector 540 divides each of the first frame data (e.g., an image signal of a previous frame) and the second frame data (e.g., an image signal of a current frame) into a plurality of detection blocks (S120). For example, an image of a single frame displayed by the first frame data may be divided into a plurality of first detection blocks. Further, an image of a single frame displayed by the second frame data may be divided into a plurality of second detection blocks. The plurality of first detection blocks of the first frame data and the plurality of second detection blocks of the second frame data have the same size. For example, as shown in
The moving pattern detector 540 determines whether a first difference between an average luminance BY2 of the plurality of second detection blocks of the current frame and an average luminance BY1 of the plurality of first detection blocks of the previous frame is smaller than a first reference value α (S130). The first difference between the average luminance BY2 of the plurality of second detection blocks and the average luminance BY1 of the plurality of first detection blocks may be calculated as an absolute value. The first reference value α is a reference value for determining a difference (e.g., first difference) in average luminance of the detection blocks between the frames.
The moving pattern detector 540 selects the second DCC when the first difference between the average luminance BY2 of the plurality of second detection blocks of the current frame and the average luminance BY1 of the plurality of first detection blocks of the previous frame is larger than or equal to the first reference value α (S160). The second DCC is a DCC that is applied to the region other than the moving pattern region.
When the first difference between the average luminance BY2 of the plurality of second detection blocks of the current frame and the average luminance BY1 of the plurality of first detection blocks of the previous frame is smaller than the first reference value α, the moving pattern detector 540 determines whether a second difference between luminance PY2 of each pixel included in the plurality of second detection blocks and luminance PY1 of each pixel included in the plurality of first detection blocks is larger than a second reference value β (S140). The second difference between the luminance PY2 of each pixel included in the plurality of second detection blocks and the luminance PY1 of each pixel included in the plurality of first detection blocks may be calculated as an absolute value. The second reference value β is a reference value for determining a difference (e.g., second difference) in luminance of each pixel included in the plurality of detection blocks between the frames.
The moving pattern detector 540 selects the second DCC when the second difference between the luminance PY2 of each pixel included in plurality of the second detection blocks and the luminance PY1 of each pixel included in the plurality of first detection blocks is smaller than or equal to the second reference value β (S160).
The moving pattern detector 540 selects the first DCC when the second difference between the luminance PY2 of each pixel included in the plurality of second detection blocks and the luminance PY1 of each pixel included in the plurality of first detection blocks is larger than the second reference value β (S150). The first DCC is a DCC that is applied to the moving pattern region. For example, when the first difference between the average luminance BY2 of the plurality of second detection blocks and the average luminance BY1 of the plurality of first detection blocks is smaller than the first reference value α and the second difference between the luminance PY2 of each pixel included in the plurality of second detection blocks and the luminance PY1 of each pixel included in the plurality of first detection blocks is larger than the second reference value β, the plurality of second detection blocks is determined to include the moving pattern.
When the first DCC is selected, the moving pattern detector 540 outputs the plurality of second detection blocks of the current frame to the first DCC unit 550, and when the second DCD is selected, the moving pattern detector 540 outputs the plurality of second detection blocks of the current frame to the second DCC unit 560 (S170).
For example, when the average luminance BY1 of the plurality of first detection blocks of the (k−1)-th frame (e.g., previous frame) and the average luminance BY2 of the plurality of second detection blocks of the k-th frame (e.g., current frame) are substantially the same as each other, the first difference between the average luminance BY2 of the plurality of second detection blocks of the k-th frame (e.g., current frame) and the luminance BY1 of the plurality of first detection blocks of the (k−1)-th frame (e.g., previous frame) may be determined to be smaller than the first reference value α.
In addition, when the second difference between the luminance PY1 of each pixel in a dotted line of the plurality of first detection blocks of the (k−1)-th frame (e.g., previous frame) and the luminance PY2 of each pixel of a dotted line of the plurality of second detection blocks of the k-th frame (e.g., current frame) is larger than the second reference value β, the corresponding second detection blocks in the dotted line of the k-th frame (e.g., current frame) may be determined to include the moving pattern.
Table 1 shows a method for detecting the moving pattern described above.
According to the above-described method, the moving pattern detector 540 determines whether a plurality of detection blocks (e.g., plurality of second detection blocks) includes the moving pattern, and transfers one detection block including the moving pattern to the first DCC unit 550 and another detection block in which the moving pattern is not included to the second DCC unit 560.
Referring back to
The second DCC unit 560 applies the second DCC to the detection block in which the moving pattern is not included. The second DCC is a DCC in which the rising time and falling time are not considered. For example, in the second DCC, the rising time and the falling time are different from each other. For example, the second DCC unit 560 operates regardless of the rising and falling times by using the second DCC.
The data output section 570 receives the detection block to which the first DCC is applied from the first DCC unit 550 and the detection block to which the second DCC is applied from the second DCC unit 560. The data output section 570 combines the detection block to which the first DCC is applied and the detection block to which the second DCC is applied and generates a second image signal ImS′ of the current frame. The data output section 570 may output the generated second image signal ImS′ to the signal controller 100.
The moving pattern may be detected by comparing spatial frequencies between frames for displaying the motion picture. For example, the spatial frequencies correspond to Fourier series of a spatial periodic function of a moving pattern having a predetermined period and thus the moving pattern may be detected.
Hereinafter, a first DCC and a second DCC will be described with reference to
The rising time T-rise may be a time required to increase the luminance of the pixel from 10% to 90% of an amount of the increased luminance when a data voltage with a higher gray value than that of the previous frame is applied to the pixel electrode PE. The falling time T-fall may be a time required to decrease the luminance of the pixel from 90% to 10% of an amount of the decreased luminance when a data voltage with a lower gray value than that of the previous frame is applied to the pixel electrode PE.
When the data voltage with the higher gray value than that of the previous frame is generated in the current frame, at first, an outputted data voltage (e.g., preceding data voltage) is higher than an original data voltage corresponding to a gray value to be displayed by a predetermined level, and is changed to the original data voltage corresponding to the gray value to be displayed by a predetermined level when the luminance of the pixel reaches the value corresponding to the desired gray value to be displayed. For example, since at first, the data voltage is higher than the original data voltage corresponding to the gray value to be displayed by the predetermined level, the pixel voltage may be rapidly increased and thus, the rising time T-rise of the luminance at the pixel may be reduced.
In addition, when the data voltage with the lower gray value than that of the previous frame is generated in the current frame, at first, an outputted data voltage (e.g., preceding data voltage) is lower than an original data voltage corresponding to a gray value to be displayed by a predetermined level, and the data voltage is changed to the original voltage corresponding to the gray value to be displayed by a predetermined level when the luminance of the pixel reaches the value corresponding to the desired gray value to be displayed. For example, since at first, the data voltage is lower than the original data voltage corresponding to the gray value to be displayed, the pixel voltage may be rapidly decreased and the falling time T-fall of the luminance may be reduced.
As shown in
Table 2 is an example showing the rising time T-rise and the falling time T-fall when a gray value is changed from one gray value (see, e.g., first column of Table 2) to another gray value (see, e.g., first row of Table 2) in the first DCC. A unit of the rising time T-rise and the falling time T-fall is ms.
As shown in
Table 3 is an example showing the rising time T-rise and the falling time T-fall when a gray value is changed from one gray value (see, e.g., first column of Table 3) to another gray value (see, e.g., first row of Table 3) in the second DCC. The unit of the rising time T-rise and the falling time T-fall is ms.
Referring to Table 3, when a gray value is changed from one gray value to another gray value, generally, the rising time T-rises are longer than the falling times T-fall excepting for some cases (e.g., a case when the gray value is changed from 31 to 63, or from 127 to 159). Here, the maximum rising time T-rise is 8.88 ms when the gray value is changed from 127 to 191. Further, an average of difference values between the rising time T-rise and the falling time T-fall is 4.65 ms excepting for a white gray value and a black gray value.
Table 2 in which the rising time T-rise and the falling time T-fall are the same as each other is made by matching the falling time T-fall to the rising time T-rise in Table 3. The maximum rising time T-rise in Table 2 is 8.88 ms when the gray value is changed from 127 to 191, similar to Table 3. In addition, an average of difference values between the rising time T-rise and the falling time T-fall is 5.99 ms excepting for the white gray value and black gray value in Table 2.
For example, the rising time T-rise may be shorter than the falling time T-fall, as shown in
As described above, the first DCC is applied to the detection block including the moving pattern and the second DCC is applied to the detection block in which the moving pattern is not included and thus the flicker of the motion picture may be reduced and the response speed of the liquid crystal may be prevented from being deteriorated. This will be described below with reference to
Referring to
In addition, when the first DCC is not applied to the detection block including the moving pattern and the second DCC having different rising time T-rise and falling time T-fall is applied to the detection block including the moving pattern, the flicker I may occur by the difference between the rising time T-rise and the falling time T-fall, as shown in
Referring to
In a display device, when displaying the moving pattern by applying only the second DCC without applying the first DCC and measuring the moving pattern by using a detector, the rising slow and falling fast phenomena may be generated, as shown in
In addition, the number of raw frames when the image is photographed and the number of display frames when the display device displays the image may be different from each other. In this case, a pull-down method of repeatedly displaying the raw frames according to a specific rule may be used. For example, when the image is photographed, the image is photographed at 24 frames per second and is displayed at 60 frames per second (e.g., 60 Hz) through the display device.
In this case, in the display device, when applying only the second DCC without applying the first DCC to the moving pattern, the rising slow and falling fast phenomena may be generated, and a moving pattern region may become relatively dark in the motion picture compared to the still image. For example, the moving pattern region may be a region in which the moving pattern is included.
Hereinafter, the flicker generated when the image is displayed using the full-down method will be described with reference to
Referring to
For example, according to the 3:2 full-down method, the raw frame A of the photographed image is displayed as three display frames A1, A2, and A3, the raw frame B of the photographed image is displayed as two display frames B1 and B2, the raw frame C of the photographed image is displayed as three display frames C1, C2, and C3, and the raw frame D of the photographed image is displayed as two display frames D1 and D2.
The three display frames A1, A2, and A3 should be displayed in the same image. The two display frames B1 and B2 should be displayed in the same image. The three display frames C1, C2, and C3 should be displayed in the same image. The two display frames D1 and D2 should be displayed in the same image.
In this case, when applying only the second DCC without applying the first DCC to the moving pattern, the rising slow and falling fast phenomena may be generated in the display frames A1, B1, C1, and D1. When measuring the luminance of each of the display frames A1, B1, C1, and D1, the luminance may be relatively low in the display frames A1, B1, C1, and D1. For example, in the case C (e.g., 6 pixels moving), the luminance is lower than the luminance of the cases A (e.g., 1 pixel moving) and B (e.g., 3 pixels moving) in the display frames A1, B1, C1, and D1.
As described above, a flicker may occur in the display frames A1, B1, C1, and D1. An image repeatedly becomes bright and dark by the flicker and thus the luminance in the display frame A1, B1, C1, and D1 may be relatively low. The flicker may occur in accordance with a size and a moving speed of an image pattern. For example, when a moving pattern has a size of 3×3, if the moving pattern moves at speeds of e.g., 3, 9, 15 pixels per frame, the flicker may occur, but if the moving pattern moves at speeds of e.g., 6, 12, 18 pixels per frame, the flicker might not occur. When the moving pattern has a size of 6×6, if the moving pattern moves at speeds of 6, 18, . . . pixels per frame, the flicker may occur, but if the moving pattern moves at speeds of 12, 24, . . . pixels per frame, the flicker might not occur.
According to the exemplary embodiment of the present invention, when the data processor 500 applies the first DCC to the detection block including the moving pattern, the flicker might not occur regardless of the size and moving speed of the moving pattern by preventing the luminance from being lowered in the display frames A1, B1, C1, and D1.
Although the present invention has been described with reference to exemplary embodiments thereof, it will be understood that the present invention should not be limited to the disclosed embodiments, but, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2014-0006906 | Jan 2014 | KR | national |
