Patent Application
20110032282
The present application claims priority from Japanese application JP 2009-185306 filed on Aug. 7, 2009, the content of which is hereby incorporated by reference into this application.
1. Field of the Invention
The present invention relates to a display device and a driving method therefor, and more particularly, to a self-luminous display device equipped with electroluminescence (EL) elements, organic EL elements, or other self-luminous elements serving as self-luminous type display elements, and also to a driving method therefor.
2. Description of the Related Art
Self-luminous elements, typified by EL elements and organic EL elements, have characteristics that they emit light with brightness proportional to the amount of current flowing therethrough, and accordingly gray-scale display is enabled by controlling the amount of current flowing through the self-luminous element. A display device may be manufactured by arranging a plurality of such self-luminous elements.
Meanwhile, there are fluctuations in characteristics among drive transistors for controlling the amounts of current flowing through the self-luminous elements due to non-uniformity in a manufacturing process therefor. The characteristic fluctuations result in fluctuations in drive current of the self-luminous elements, eventually leading to brightness fluctuations among pixels, which are responsible for degrading image quality.
As one of the circuits for solving such a problem, Japanese Patent Application Laid-open No. 2003-5709 discloses the following technology. That is, in each horizontal period (one-line period), a display data signal is written with reference to the characteristics of the drive transistor and thereafter a triangular wave for controlling an emission timing is input, to thereby perform gray-scale display while canceling the characteristic fluctuation of the drive transistor as well as controlling an emission time.
The technology disclosed in Japanese Patent Application Laid-open No. 2003-5709 is a driving method called time modulation scheme, in which the emission time is controlled based on a magnitude comparison between a data voltage (signal voltage) and a triangular wave voltage, with a display period divided into a signal write period (signal voltage write period, data write period) and a triangular wave input period (triangular wave voltage input period, emission period, turn-on time). For example, in the driving method, the signal write period and the emission period are separately provided in each frame period or each horizontal period.
In such driving, in order to ensure a long emission time in each frame period, it is necessary to provide a frame memory so that a display period may be reduced to ensure a long blanking period, and hence peripheral circuitry has a large scale. Alternatively, it is conceivable to provide a line buffer to ensure a long emission time in each horizontal period. In fact, however, not all the horizontal blanking period can be set as the emission period. As described later, light emission cannot be performed until a pixel drive voltage (triangular wave) is written in place of the signal voltage, and hence a long emission time cannot be ensured. In addition, there is a fear that fluctuations in write characteristics among the drive transistors and a difference in write condition may lead to fluctuations in drive current of the self-luminous elements, with the result that brightness fluctuations may occur to degrade image quality.
The present invention has been made in view of the above-mentioned problems, and it is therefore an object of the present invention to provide a display device capable of preventing degradation in displayed image quality due to fluctuations in write characteristics among drive transistors or a difference in write condition, and provide a driving method therefor.
(1) In order to solve the above-mentioned problems, there is provided a display device including: a display portion including: a plurality of pixels arrayed in a matrix of rows and columns, the plurality of pixels each including a self-luminous element and a drive element for supplying a current to the self-luminous element; a plurality of data lines for supplying a display signal voltage to the plurality of pixels; and a plurality of scanning lines intersecting with the plurality of data lines; and a data line drive circuit for providing a first period in which the display signal voltage in accordance with display data is output to the plurality of data lines, and a second period in which a control voltage for controlling the drive element to control light emission of the self-luminous element is output to the plurality of data lines, to thereby supply the display signal voltage and the control voltage to the plurality of pixels. The data line drive circuit further provides, after the second period, a third period in which a given voltage signal is applied to a control terminal of the drive element. The data line drive circuit is configured to: output the display signal voltage in accordance with the display data in the first period; output the control voltage for controlling the light emission of the self-luminous element in the second period; and output the given voltage signal for setting the control terminal of the drive element to have a given correction voltage in the third period.
(2) In order to solve the above-mentioned problems, there is provided a driving method for a display device, the display device including: a plurality of pixels arrayed in a matrix of rows and columns, the plurality of pixels each including a self-luminous element and a drive element for supplying a current to the self-luminous element; a plurality of data lines for supplying a display signal voltage to the plurality of pixels; and a plurality of scanning lines intersecting with the plurality of data lines, the driving method including sequentially repeating: a first period in which the display signal voltage in accordance with display data is output to the plurality of data lines; a second period in which a control voltage for controlling the drive element to control light emission of the self-luminous element is output to the plurality of data lines; and a third period in which a given voltage signal is applied to a control terminal of the drive element.
According to the present invention, an emission time may be ensured by a line memory, eliminating the need for a frame memory, to thereby simplify a configuration of peripheral circuitry. Besides, the fluctuations in write characteristics maybe corrected to correct the difference in write condition due to corrective line writing, to thereby perform high-brightness image display.
Other effects of the present invention become clear from the entire description of the specification.
In the accompanying drawings:
Hereinafter, embodiments to which the present invention is applied are described with reference to the accompanying drawings. It should be noted that, in the following description, the same components are denoted by the same reference numerals so that repetitive description thereof is omitted.
The vertical synchronization signal 1 is a signal indicating one cycle (one-frame cycle) of a display screen, the horizontal synchronization signal 2 is a signal indicating one horizontal cycle, and the data enable signal 3 is a signal indicating a period (display effective period) in which the display data 4 is effective. All those signals are input in synchronization with the synchronization clock 5. It should be noted that, in this embodiment, the display data 4 for one screen is transferred sequentially in the raster scanning scheme, starting from data on a pixel (not shown) provided at the upper left end of an image. Information on each pixel is constituted by 6-bit digital data.
The horizontal image storage circuit 12 is capable of storing the display data 4 for at least two horizontal scanning lines (two lines) of the self-luminous element display 20 (described in detail later). In this embodiment, the horizontal image storage circuit 12 stores display data for three lines to be read out sequentially.
In temporarily storing the display data 4 into the horizontal image storage circuit 12, the display control portion 6 generates the storage circuit control signal 9 and the storage circuit control address 10 as a write control signal and a write address, respectively, and outputs those signal and address to the horizontal image storage circuit 12 together with the storage data 11. On the other hand, in reading out the storage data 11 in synchronization with a display timing of the self-luminous element display 20 as the read-out data 13, the display control portion 6 generates the storage circuit control signal 9 and the storage circuit control address 10 as a read control signal and a read address, respectively, and outputs those signal and address to the horizontal image storage circuit 12. The display control portion 6 further generates the data line control signal 7 and the scanning line control signal 8 based on the read control signal, the read address, and the read-out data 13, and outputs the generated signals.
The self-luminous element display 20 has a display configuration using light-emitting diodes or organic electroluminescence (EL) elements as display elements, and includes a plurality of self-luminous elements (pixels) (not shown) arranged in matrix. In a display operation of the self-luminous element display 20, in accordance with the data line drive signal 15 output from the data line drive circuit 14, a signal voltage and a triangular wave signal are applied to the pixels on a line selected by the scanning line drive signal 17 output from the scanning line drive circuit 16, to thereby control an emission time of each pixel. The self-luminous element emits light when applied with the self-luminous element emission voltage 19 for the controlled emission time. It should be noted that the data line drive circuit 14 and the scanning line drive circuit 16 may be implemented by separate large scale integrated circuits (LSIs) or a single LSI, and may be formed on the same glass substrate where pixel portions are formed. In this embodiment, the self-luminous element display 20 has a resolution of 240×320 dots.
As illustrated in
The another terminal of the drive inverter 37 is further connected to one terminal of the reset switch 35. Another terminal of the reset switch 35 is connected to a control terminal (gate terminal) of the drive inverter 37 and one terminal of the write capacitor 36. A control terminal (gate terminal) of the reset switch 35 is connected to the first scanning line 23. Another terminal of the write capacitor 36 is connected to the first data line 21.
The correction switch 38 is characteristic of a drive circuit formed in each pixel of the self-luminous element display 20 according to the first embodiment. One terminal of the correction switch 38 is connected to the control terminal of the drive inverter 37, and another terminal thereof is connected to the first data line 21. A control terminal (gate terminal) of the correction switch 38 is connected to the first correction control line 27.
This way, in the display device according to the first embodiment, a display area of the self-luminous element display 20 is partitioned into a plurality of pixel regions (regions 31 to 34 indicated by the dotted lines of
Next, referring to
The reset switch 35 is turned “ON” by the first scanning line 23 to short-circuit the input and output of the drive inverter 37. When the reset switch 35 is turned “ON”, a reference voltage is set depending on characteristics of transistors forming the drive inverter 37 included in each pixel. With reference to the reference voltage, the write capacitor 36 is charged to the signal voltage supplied from the first data line 21, to thereby write the signal voltage into each pixel.
The drive inverter 37 outputs “Low” when the triangular wave to be input after the writing of the signal voltage is higher than the signal voltage written into the write capacitor 36, and outputs “High” when the triangular wave is lower than the signal voltage.
Upon the input of the triangular wave, the emission control switches 39 of all the pixels are turned “ON”, and hence when the output of the drive inverter 37 becomes “High”, the corresponding organic EL element 40 emits light. After the light emission, the correction switch 38 is turned “ON” to set a gate voltage of the drive inverter 37 to a correction voltage supplied from the first data line 21, to thereby enable the above-mentioned signal voltage write operation to be performed with the same characteristics between a period immediately after the light emission and the remaining period followed by the period.
Meanwhile, as described above, the number of pixels of the self-luminous element display 20 according to the first embodiment is 240×320. As the scanning lines, 320 horizontally-extending signal lines, from the first scanning line 23 to the 320th scanning line 24, are arrayed in the vertical direction. In a case where each pixel of the self-luminous element display 20 is formed of three dots of R, G, and B arranged side by side in the horizontal direction, 720 pixel regions indicated by the dotted lines of
The input and output of the drive inverter 37 are short-circuited by the reset switch 35 being turned “ON” for data writing. As a result, the potentials of the input node and the output node of the drive inverter 37 are set to the signal voltage write reference potential 43, which appears at the intersection between the input/output characteristic 41 and the input/output short-circuiting condition 42 indicated by the straight line of Vin=Vout. The writing of the signal voltage is performed with reference to the signal voltage write reference potential 43.
As illustrated in
In the data write period in which the input voltage is set as a signal voltage (Vsig) and the reset pulse and the emission control pulse are set to “High”, the input node voltage of the drive inverter 37 becomes a drive inverter threshold voltage, which is determined based on the characteristics of the drive inverter 37 and the organic EL element 40. The triangular wave voltage applied in the triangular wave periods drops from High in terms of triangular wave to Low in terms of triangular wave over a plurality of lines. Then, the triangular wave voltage rises again from Low in terms of triangular wave to High in terms of triangular wave.
According to the conventional display device illustrated in
A display voltage write period (data write period) is set for three successive lines (three lines in sequence for each line), in which the reset pulse is set to “High” to turn “ON” the reset switch 35. Subsequently, a triangular wave period (triangular wave voltage application period) is set for three lines collectively, in which only the emission control pulse is set to “High”. The operation of the drive inverter 37 on this occasion is the same as the operation described above with reference to
[Emission Operation with Correction for Every Two or More Plurality of Lines]
As illustrated in
In other words, in the display device according to the first embodiment, in the data write period for three lines illustrated in
In the subsequent triangular wave period for three lines, which is made up of the shift period, the emission allocated period (second period), and the correction period (third period), a period since the end of the data write period until the rise of the emission control pulse corresponds to the shift period. The shift period is a period for the shift from the display signal voltage to the triangular wave voltage. Further, a period since the end of the shift period until the input of the correction pulse corresponds to the emission allocated period, and a period in which the correction pulse 601 is input corresponds to the correction period.
As described above, according to the first embodiment, the data write period and the triangular wave period are each set every three lines, and the correction period is provided immediately before the end of the triangular wave period, to thereby correct the gate voltage fluctuation of the drive inverter 37 and reset the emission voltage held in a parasitic capacitor of the organic EL element 40 immediately after light emission.
During the light emission, a current Id flows through the drive inverter 37 toward the organic EL element 40. As illustrated in
According to the first embodiment, however, as illustrated in
In other words, also in the display device according to the first embodiment, as illustrated in
In
The one-line latch circuit 49 latches the display shift data 48 corresponding to one line, and outputs the latched data as the one-line latched data 51 in synchronization with the horizontal latch clock 50 as well as outputting the horizontal blanking period signal 52 indicating a period in which no one-line latched data 51 is output.
The gray-scale voltage selection circuit 53 selects one level among 64 levels of the gray-scale voltage in accordance with the one-line latched data 51, and outputs the selected voltage as the one-line display data 54.
The triangular wave period data generation circuit 55 generates the triangular wave signal 56 having a one-frame period as one cycle, and the correction voltage 57 to be input via the correction switch 38 at the end of the emission period. Further, the triangular wave period data generation circuit 55 generates the triangular wave switch signal 58 indicating the output timing of the triangular wave signal 56, and the correction voltage switch signal 59 indicating the output timing of the correction voltage 57.
In accordance with the triangular wave switch signal 58 and the correction voltage switch signal 59, the gray-scale voltage/triangular wave/correction voltage switch circuit 60 switches among the one-line display data 54, the triangular wave signal 56, and the correction voltage 57 and outputs the switched one as the data line drive signal 15.
In other words, in the data line drive circuit 14 according to the first embodiment, for example, upon the inputs of the data start signal 45, the data clock 46, and the display serial data 47 as illustrated in
Based on the one-line latched data 51, the gray-scale voltage selection circuit 53 selects one level among 64 levels of the gray-scale voltage for each pixel on one line. Then, a voltage value of the level selected for each pixel on one line is output to the gray-scale voltage/triangular wave/correction voltage switch circuit 60 as the one-line display data 54.
On the other hand, as described above, the triangular wave period data generation circuit 55 generates the triangular wave signal 56 having a cycle of a one-frame period, the correction voltage 57 to be input via the correction switch 38 at the end of the emission period, the triangular wave switch signal 58 indicating the output timing of the generated triangular wave signal 56, and the correction voltage switch signal 59 indicating the output timing of the generated correction voltage 57. The triangular wave signal 56, the correction voltage 57, the triangular wave switch signal 58, and the correction voltage switch signal 59 are output to the gray-scale voltage/triangular wave/correction voltage switch circuit 60.
In accordance with the triangular wave switch signal 58 and the correction voltage switch signal 59, the gray-scale voltage/triangular wave/correction voltage switch circuit 60 selects any one of the one-line display data 54, the triangular wave signal 56, and the correction voltage 57, and outputs the selected signal as the data line drive signal 15.
The reference clock generation circuit 61 illustrated in
The correction voltage storage circuit 66 is a location where the voltage level for correcting the gate voltage fluctuation of the drive inverter 37 described above is stored. The correction voltage storage circuit 66 outputs the stored value as the correction voltage data 67. The digital/analog conversion circuit 65 performs digital/analog conversion on the correction voltage data 67, and outputs the converted data as the correction voltage 57. In this embodiment, the following description is given assuming that the arbitrary initial value is set to “63”, which is a maximum value of 6-bit data similarly to the display data, and that the counter output 64 and the correction voltage data 67 are also 6-bit digital data.
The triangular wave switch signal generation circuit 68 generates the triangular wave switch signal 58 indicating the output timing of the triangular wave signal 56. The correction voltage switch signal generation circuit 69 generates the correction voltage switch signal 59 indicating the output timing of the correction voltage 57.
In other words, in the triangular wave period data generation circuit 55 according to the first embodiment, based on the horizontal blanking period signal 52 input from the one-line latch circuit 49, the reference clock generation circuit 61 generates the reference clock 62 for generating the triangular wave signal 56, and the reference clock 62 is then output to the up/down counter circuit 63. When supplied with the horizontal blanking period signal 52 and the reference clock 62, the up/down counter circuit 63 starts to operate with the horizontal blanking period signal 52 as a trigger, counts down from the arbitrary initial value to “0” in synchronization with the reference clock 62, and then counts up again until the value returns to the initial value so as to output the counter output 64 as a result of the counting to the digital/analog conversion circuit 65.
The counter output 64 is subjected to the digital/analog conversion by the digital/analog conversion circuit 65, and the converted analog voltage is output as the triangular wave signal 56. At this time, the digital/analog conversion circuit 65 performs digital/analog conversion also on the voltage level to be input from the correction voltage storage circuit 66 for correcting the gate voltage fluctuation, and then outputs the converted voltage as the correction voltage 57.
Further, based on the horizontal blanking period signal 52, the triangular wave switch signal generation circuit 68 generates and outputs the triangular wave switch signal 58 indicating the output timing of the correction voltage 57. Based on the horizontal blanking period signal 52, the correction voltage switch signal generation circuit 69 generates and outputs the correction voltage switch signal 59.
The display serial data 47 illustrated in the waveform group (a) is captured into the data shift circuit 44 in synchronization with the data clock 46, with the pulse that sets the write data start signal 45 to “High” as a trigger of the capture start. For example, the n-th line display serial data 47 starts to be captured upon the rise of the data clock 46 for writing following the n-th line data capture start pulse. After all pieces of data for one line are captured, the data is output as the one-line latched data 51 in a period between the rise and fall of the horizontal latch clock 50. For example, the n-th line write data is output as the n-th line latched data upon the rise of the horizontal latch clock 50 following the capture start of data of a subsequent line.
As illustrated in the waveform group (b), the triangular wave switch signal 58 is set to “High” after the output of the one-line latched data 51 for three lines (for example, the first to third lines), and during “High” of the triangular wave switch signal 58, the triangular wave signal 56 is output as the data line drive signal 15. At the end of the emission period, the correction voltage switch signal 59 is set to “High”, and the correction voltage 57 is output as the data line drive signal 15. In other words, as the data line drive signal 15, the one-line display data 54 is output in the data write period while the triangular wave signal 56 and the correction voltage 57 are output in the triangular wave period. Further, in this embodiment, the vertical blanking period in each one-frame period is set as a vertical blanking triangular wave period in which the triangular wave signal is output, and at the end of the vertical blanking triangular wave period, a period in which the correction voltage 57 is output is provided.
As described above, in the display device according to the first embodiment, the drive circuit formed in each pixel of the self-luminous element display 20 is provided with the correction switch 38 for establishing connection between the data line and the gate terminal as the control terminal of the drive inverter 37 forming the drive circuit. The correction period is provided at the end of the triangular wave period in which light emission is performed. In the correction period, the potential of the data line is set to the correction potential that is a given preset potential, and the correction switch 38 is turned “ON”. Accordingly, the potential of the gate terminal of the drive inverter 37 is set once to the correction potential before subsequent data writing. Therefore, the gate voltage fluctuation of the drive inverter 37 caused after the light emission may be made constant to enable the sequential display voltage writing over the plurality of lines (three lines in this embodiment) to be performed with the uniform characteristics in each data write period, regardless of the order of writing.
It should be noted that, according to the display device of the first embodiment, as illustrated in
In the case where the correction switch 38 is configured as illustrated in
The connection position of the correction switch 38 in the circuit illustrated in
In the case where the correction switch 38 is configured as illustrated in
Further, in the display device according to the first embodiment, as the correction voltage to be supplied to the data line at the input timing of the correction pulse, the GND level voltage is output from an output amplifier of the digital/analog conversion circuit. However, how to supply the correction voltage is not limited thereto. For example, there may be employed a configuration in which a switch for connecting the data line to a signal line of GND is provided so that the switch may be turned “ON” at the input timing of the correction pulse to allow the data line to have the GND level potential.
In the pixel according to the second embodiment illustrated in
A reset switch 35 is connected between the another terminal and a gate terminal of the drive inverter 37. A gate terminal of the reset switch 35 is connected to a scanning line (not shown). A connection node between the reset switch 35 and the gate terminal of the drive inverter 37 is connected to one terminal of a write capacitor 36, and another terminal of the write capacitor 36 is connected to a data line 34. As described above, the pixel configuration of the display device according to the second embodiment is the same as the pixel configuration of the conventional display device.
Next, referring to
As illustrated in the waveform group (a) of
As illustrated in the waveform group (b) of
Also in the data line drive circuit according to the second embodiment, the correction period is provided after the emission allocated period. In the correction period, the triangular wave switch signal 58 is switched from “High” to “Low”, and signals of preset voltage levels are continuously output a plurality of times to the data line as the data line drive signals 15. In other words, the data line drive circuit according to the second embodiment outputs an alternating voltage to the data line in the correction period.
The application of the alternating data line drive signal 15 in the correction period of the display device according to the second embodiment is performed by means of coupling to the write capacitor 36 so that the gate voltage of the drive inverter 37 immediately after light emission may be set to a given potential. Because of the correction period provided before the data write period, the gate voltage fluctuation of the drive inverter 37 caused immediately after the light emission may be made constant. As a result, the display voltage writing immediately after the light emission and the subsequent sequential display voltage writing may be performed with the same characteristics.
As described above, in the display device according to the second embodiment, the correction period is provided at the end of the triangular wave period as the emission period, and in the correction period, the signals of the preset voltage levels are continuously applied to the write capacitor 36 a plurality of times. Then, using the capacitive coupling, the gate terminal potential of the drive inverter 37 is set to the correction potential, and thereafter subsequent data writing is performed. The display device according to the second embodiment configured as described above may also provide the same effect as in the display device according to the first embodiment.
In addition, the display device according to the second embodiment is capable of setting the gate terminal potential of the drive inverter 37 to the correction potential only by means of the output of the data line drive circuit 14. Therefore, such a special effect can be obtained that the drive circuit for driving the organic EL element and hence the pixels are simplified.
It should be noted that, in the display device according to each of the first and second embodiments, the present invention has been described exemplifying the case where the triangular wave is used as a voltage that varies in an arbitrary cycle (control voltage), but the control voltage is not limited thereto. For example, in place of the triangular wave, such a voltage as to exhibit a non-linear wave gradually increasing or decreasing along with a display straight line may be used to emphasize or de-emphasize the gray-scale change for display. Further, the time modulation is not limited to the one using the triangular wave, and the present invention is also applicable to a display device having a configuration in which a gate voltage level of the drive inverter is used to control a current flowing through the organic EL element.
Further, by the operation of the display device according to each of the first and second embodiments, the self-luminous element display that performs gray-scale control by means of horizontal blanking emission requiring no frame memory is capable of prolonging an emission time to perform high-brightness image display.
The present invention is a technology applicable to display devices of a mobile phone, a digital still camera (DSC), and an information processing terminal such as a personal digital assistant (PDA), as well as to large-sized display devices such as a TV set and an information signboard.
The invention devised by the inventors of the present invention has been specifically described above by way of the above-mentioned embodiments of the invention. However, the present invention is not limited to the above-mentioned embodiments of the invention, and various modifications may be made thereto without departing from the gist of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2009-185306 | Aug 2009 | JP | national |
