Patent Grant
7391396
The present invention relates to a display device, and, more particularly, to a display device and a method of driving a display device so as to achieve high luminance and excellent motion picture display characteristics.
Flat panel type display devices, such as a liquid crystal display device, a plasma display device, a field emission display device, an organic light emitting display device and the like have been popularly used as color monitors for computers or other information equipment, or as display devices in television receiver sets. Among these flat panel type display devices, there has been a so-called hold-type display device which operates on the basis of the light emitting characteristics of pixels. The liquid crystal display device and the plasma display device are typical examples of a hold-type image display device. For example, the liquid crystal display device displays images with the following constitution and manner of operation.
Further, the liquid crystal display device includes a display control circuit CRL, which constitutes display control means for supplying display data DATAin for displaying images, control signals (various clock signals including dot clocks CL, display timing signals DTMG, vertical synchronizing signals VSYNC, horizontal synchronizing signals HSYNC and the like), gray scale voltages and the like to the drain driver DR and the gate driver GR, and a power source circuit PWU. The display control circuit CRL is provided with a timing controller Tcon which generates various display timing signals for controlling the display. Pixels PX are arranged on crossing portions where the gate lines GL and the drain lines DL cross each other.
The input display data DATAin that is transmitted from an external signal source (a host computer), such as a computer, a personal computer or a television image receiving circuit, and various voltage signals, such as the dot clocks DCLK, display timing signals DTMG, the vertical synchronizing signals VSYNC, and the horizontal synchronizing signals HSYNC, are inputted to the display control circuit CRL. The display control circuit CRL includes a gray scale reference voltage generating part and the like (not shown in the drawing) besides the timing controller Tcon, and it converts the input display data DATAin and the various voltage signals from the outside into output data (display data) DATAout in a form suitable for display on the liquid crystal display panel PNL. The display data DATAout and the various clock signals CL are supplied to the drain drivers DR and the gate drivers GR in the manner shown in the drawing. In such a constitution, a carry output CRY of the preceding stage of the drain driver DR is directly supplied to the carry input of the drain driver of the succeeding stage. Reference symbol DB indicates a data bus of the display data DATAout.
The liquid crystal display device having such a constitution has been steadily replacing a cathode ray tube (CRT) display due to its beneficial features, such as low power consumption. The acceleration of such replacement is brought about by technological innovations which have led to enhancement of the image quality of the liquid crystal display device. Particularly, in recent years, a demand for motion picture display, as represented by a television image, is becoming stronger, and improvements have been made in liquid crystal materials and driving methods to satisfy this demand.
However, while the CRT employs an impulse type light emission by electron beam scanning using an electron gun, as mentioned previously, the liquid crystal display device employs a hold type light emission using a backlight system or the like, in which a linear lamp (a fluorescent lamp) or the like is used as an illumination light source; and, hence, it has been considered difficult for the liquid crystal display device to produce a complete motion picture display. That is, when a motion picture display is produced using a liquid crystal display device, due to the holding characteristics thereof, so-called motion picture profile deterioration (generally referred to as “blurring” or “motion picture blurring”) is generated, and, hence, the image quality is degraded. The phenomenon is not limited to a liquid crystal display device and is generated in the same manner in a plasma display device or the like, for example.
Referring to
In the above-mentioned hold-type display device, such as a liquid crystal display device, a so-called “hold-type” display which displays the image over one frame period is produced. On the other hand, in a CRT, a so-called “impulse-type” display, which displays an image only for a moment and displays black during the remaining period, is produced. The cause which brings about the blurring of the image when the motion picture is displayed using a hold-type display device is strongly influenced by the above-mentioned hold-type characteristic. Accordingly, if an impulse-type display can be realized in this type of device, it is possible for the hold-type display device to realize a high-definition display with no motion picture blurring.
As techniques which have been proposed to overcome this drawback, a method which uses an improvement in the liquid crystal material which constitutes the liquid crystal layer of the liquid crystal display panel (also referred to as a liquid crystal cell), an improvement of the display mode, and the use of a direct backlight as a light source has been reported in Japanese Unexamined Patent Publication Hei11(1999)-109921. In a hold-type display device which uses a so-called direct backlight, in which a light source is directly mounted on a back surface of the liquid crystal display panel, has been proposed to use an illumination method which is referred to as blinking of the backlight. Here, a plurality of linear lamps (cold cathode fluorescent lamps or the like), or a light emitting diode array, are arranged in a direction parallel to gate lines right below a main surface (back surface) of the liquid crystal display panel, and the timings of respective lighting start times of the linear lamps are shifted from above to below on a display screen and are synchronized with the scanning cycles of the image display signals.
Further, Japanese Unexamined Patent Publication 2001-343949 discloses an attempt to widen the dynamic range of a display by inserting white signals or black signals between gray scale displays of respective colors in a projection type image display device.
The above-mentioned liquid crystal display device employs a method which controls the lighting time of the light source, in other words, inserts black images (also referred to as black signals) between the frames, and so the liquid crystal display device can enhance the motion picture display characteristics by obviating the generation of the motion picture profile deterioration to some extent. However, as a result, the light emission time which occurs during one period of the scanning becomes short; and, hence, the luminance efficiency of the illumination light is lowered, whereby a sufficient luminance cannot be obtained, and the whole image is darkened in proportion to the insertion ratio of the black image.
Accordingly, it is an object of the present invention to obtain a motion picture display of high luminance and high quality by eliminating the occurrence of motion picture profile deterioration at the time of displaying the motion picture on a hold-type display device by processing of video signals.
To achieve the above-mentioned object, in a driving method of the present invention, video data of a plurality of continuous frames, which are continuously inputted from an external signal source, are respectively stored in a plurality of frame memories, the video data which is stored in the first frame memory is read out in response to a 2 m (m being an integer of 1 or more) multiplied-speed clock signal which is obtained by multiplying a pixel clock signal inputted from an external signal source 2 m times, thus forming display data in a first field, and
the video signals of two continuous frames are compared in accordance with every pixel display unit, wherein, when the pixel display unit of the succeeding frame has a higher luminance than the pixel display unit of the preceding frame, first display data is supplied to a display part as display data of a second field, and, when the pixel display unit of the succeeding frame has a lower luminance than the pixel display unit of the preceding frame, second display data is supplied to the display part as display data of the second field.
Further, in the same manner as described above, the video data which is stored in the first frame memory is read out in response to the 2 m multiplied-speed clock signal thus forming the display data in the first field; wherein, when the pixel display unit of the succeeding frame has a luminance which is higher than a given value, the first display data is supplied to the display part as the display data of the second field, and, when the pixel display unit of the succeeding frame has a luminance which is lower than a given value, the second display data is supplied to the display part as the display data of the second field.
Further, according to one aspect of the present invention, a display control circuit CRL is provided with a frame memory having two or more frames (or a memory having capacitance of two or more frames) and a clock synthesizer which multiplies the frequency of an input clock signal that is inputted from the external signal source (host computer) by twice (or twice and four times). For example, input video data (first n-frame data) inputted from the host computer is stored in one of the frame memories as first video data in response to a clock signal inputted from the host computer in the same manner; and, thereafter, the next inputted video data (the (n+1)th frame data) is stored in another frame memory as second video data. The first video data is read out as the display signal of the first field in response to a clock (double-speed clock) signal having a frequency twice as large as the frequency of the input clock signal, and it is supplied to respective drain drivers. Outputting to the respective drain drivers also makes use of the double-speed clock signal.
Next, the second video data which is stored in the frame memory is compared with the first video data in accordance with each pixel display unit; wherein, when the second video data is brighter than the first video data, the first display data is supplied to respective drain drivers as the display data of the second field, while, when the second video data is darker than the first video data, the second display data is supplied to respective drain drivers as the display data of the second field. When the second video data and the first video data have the same luminance, or there is no noticeable change between both video data, either one of the first display data or the second display data is selected in accordance with the contents (bright or dark) of the second video data and is supplied to the respective drain drivers as the display data of the second field. Here, one example of a turning point of the selection of the first black display data or the second white display data is that the luminance of the second video data is ½ the luminance of the black display and the white display.
Here, in place of the clock synthesizer, means which generates a clock signal which multiplies the frequency four times (or twice and four times) or more (eight times) may be provided separately. Further, after comparing the first video data (n frame) and the second video data ((n+1) frame), in place of setting the above-mentioned black display data or the white display data as the display data of the second field, the second video data is compared with a given value (a reference value). Then, it is possible that, when the second video data is brighter (the luminance is higher or the gray scale is higher) than the reference value, the first display data is used as the display data of the second field, and, when the second video data is darker (the luminance is lower or the gray scale is lower) than the reference value, the second display data is used as the display data of the second field. The given value can be arbitrarily set.
Further, it may be possible to adopt a method in which gray scale data amounting to ±α (α being an arbitrary number) is added to the above-mentioned comparison result of the first video data and the second video data. The determination to set the gray scale data amounting to α to “+” or “−” is made in accordance with the degree of comparison with the first video data. This operation is a so-called overdrive operation.
Further, it also may be possible to provide a constitution which determines whether the display data of the second field should be the first display data or the second display data based on only the value of the second video data, without depending on the above-mentioned comparison result of the second video data and the first video data. Further, the above-mentioned respective processing may be performed for respective pixels or respective colors of red(R), green (G) and blue (B) individually. That is, when one pixel which is constituted of a dot displaying red, a dot displaying green and a dot displaying blue is set as a display unit, the above-mentioned first display data constitute data displaying white and the above-mentioned second display data constitute data displaying black. Further, when the respective three dots which constitute one pixel are set as single display units, respectively, with respect to the dot displaying red, the above-mentioned first display data constitute data displaying red. In the same manner, with respect to the dot displaying green, the above-mentioned first display data constitute data displaying green, and, with respect to the dot displaying blue, the above-mentioned first display data constitute data displaying blue. Here, in the above-mentioned respective dots, the second display data is data displaying black.
In this manner, by adopting the method in which one frame which is displayed on the display device is constituted of two fields, wherein, in the first field, video signals constitute the display data and, in the second field, the first display data or the second display data corresponding to contents of the next-input video signal constitute the display data, or either one of the first display data or the second display data constitute the display data as a result of comparison between the next-input video signal and the given value, or an arbitrary gray scale value is added to or is subtracted from a result of comparison between the next-input video signal and a given value so as to form the display data of the second field, it is possible to realize a video display of high luminance and high quality, in which it is possible to prevent the generation of motion picture profile deterioration, that is, so-called “motion picture blurring”, without degrading the luminance of the display screen.
Here, the present invention is not limited to the above-mentioned constitution and the constitution disclosed in the embodiment described later, and various modifications can be made without departing from the technical concept of the present invention.
Preferred embodiments of a liquid crystal display device according to the present invention will be explained hereinafter in detail in conjunction with the drawings.
In
Respective gate drivers are connected with the gate lines GL for supplying scanning signals, and respective drain drivers are connected with the drain lines DL for supplying display signals. On respective crossing portions-of the drain lines DL and the gate lines GL of the liquid crystal display panel PNL, pixels PX, which are constituted of a thin film transistor circuit, are formed. Although the constitution is not illustrated in detail in the drawing, each pixel PX is constituted of a dot which displays red, a dot which displays green and a dot which displays blue. Here, a pixel is shown as being connected to one drain line in the drawing, the above-mentioned three dots are arranged close to each other along one gate line and respective dots are connected with respective drain lines. However, the arrangement of the respective dots is arbitrary, and there arises no problem even when the arrangement of the respective dots adopts a constitution in which respective dots are arranged at respective peaks of a triangle, thus constituting a so-called delta arrangement.
The display control circuit CRL is connected to the liquid crystal display panel PNL (TFT-LCD). The display control circuit CRL includes a timing controller Tcon which generates various timing signals for display, such as the above-mentioned clock signals. Further, the timing controller Tcon includes an input data processing circuit IDP and an output data processing circuit DOP, and these circuits generate input display data DATAin and data for display (output data DATAout) based on various timing signals. In this embodiment, the timing controller Tcon is provided with three line buffers Lb1, Lb2, Lb3.
The display control circuit CRL includes a double-speed clock synthesizer DSN, which generates a double-speed clock 2×DCLK by multiplying the frequency of a clock signal DCLK inputted from a host computer, and three frame memories fm1, fm2, fm3. The line buffers Lb1, Lb2, Lb3 temporarily hold display data for one line (display data for one scanning line), which is processed by the input data processing circuit IDP, and the display data are respectively transmitted to the frame memories fm1, fm2, fm3 through frame memory buses fm1Bus, fm2Bus, fm3Bus. A memory clock MCLK (=2×DCLK) is supplied to the line buffers Lb1, Lb2, Lb3 and the frame memories fm1, fm2, fm3 from the input data processing circuit IDP.
To the display control circuit CRL, the input display data DATAin (R, G, B), the dot clock signal DCLK, the vertical synchronizing signal VSYNC, the horizontal synchronizing signal HSYNC, and the display timing signal DTMG are inputted from the host computer. Further, clock signals CL1, CL2, CL3, a frame start signal FLM and a line start signal STH are outputted to the liquid crystal display panel TFT-LCD from the display control circuit CRL. Then, the display data is transferred to the liquid crystal display panel in accordance with a frame unit. Hereinafter, an explanation will be made with respect to a case in which one frame amount is constituted of two fields (a first field and a second field).
Further,
The (INPUT) signals shown in
In
In the same manner, in the vertical-direction operation, the timing controller Tcon outputs the vertical synchronizing signal VSYNC, the horizontal synchronizing signal HSYNC, the display timing signal DTMG, the input display data DATAin, the frame pulse FLM, and the clock signal CL3 to the liquid crystal display panel. Here, one frame is 60 Hz, and, hence, one field becomes 120 Hz.
In this embodiment, as shown in
Simultaneously with the above-mentioned timing, the display data stored in the frame memory fm3 (display data of the nth frame) is read out using the clock signal (double-speed clock signal) 2×DCLK having a frequency twice as large as the frequency of the clock signal DCLK of the input display data generated by the double-speed clock synthesizer DSN as the reference (for one pixel) read-out timing. The read-out display data of the nth frame becomes the display data of the first field. Since the display data is read out using the double-speed clock signal, all of the display data for the first field (120 Hz) stored in the frame memory fm3 is read out, given processing is applied to the display data in the output data processing circuit DPO, and the display data is outputted (transferred) to the drain driver DR of the liquid crystal display panel TFT-LCD, and video information is displayed on the screen. Subsequently, the display operation on the second field is performed.
In the display operation for the second field, the display data (the display data of the nth frame and the display data of the (n+1)th frame) which is stored in the frame memory fm3 and the frame memory fm2 are simultaneously read out in response to the double-speed clock signal 2×DCLK. Here, the display data stored in the frame memory fm2 is set as the comparison reference data, and the display data stored in the frame memory fm3 is set as the comparison data. The contents of the display data (one pixel unit) stored in the frame memory fm2, which constitute the comparison reference data, is compared with the display data stored in the frame memory fm3.
When the display data stored in the frame memory fm2 is display data which is darker than the display data stored in the frame memory fm3, the black display data is, as the display data of the pixel address corresponding to the black display data, is transmitted to the drain driver of the liquid crystal display panel through the output data processing circuit DOP. Further, when the display data stored in the frame memory fm2 is display data which is brighter than the display data stored in the frame memory fm3, the white display data are, as the display data of the pixel address corresponding to the white display data, is transmitted to the drain driver of the liquid crystal display panel. This processing is executed with respect to all display pixels (for one screen) of the liquid crystal display panel. Since the operations (reading out of display data from the frame memories and display data transfer processing to respective drain drivers) on the second field are also executed using the double-speed clock signal as a reference, the processing of the black display/white display is completed within the second field.
In inputting the next video frame ((n+3) frame), the input display data is stored in the frame memory fm3, wherein the frame memory fm2 provides the display data of the first field and the comparison data in the second field, while the display data stored in the frame memory fm1 becomes the comparison reference data in the second field. In the same manner as the above-mentioned operations, the video data is displayed on the first field, and the black display data or the white display data is displayed in the second field. This processing is repeated.
In the actual circuit constitution, a SDRAM or a DRAM capable of responding to a DDR can be adopted as the frame memories fm1 to fm3. In this case, the reference clock signal (also referred to as the memory clock signal) is also transmitted to the SDRAM. Accordingly, the double-speed frequency clock signal is used also in the writing (storing) processing. It is not usually conceivable to change the frequency of the memory clock signal for every processing. Accordingly, in the writing processing, the display data is temporarily held in the line buffers Lb1, Lb2, Lb3 in the inside of the timing controller Tcon; and, thereafter, the access (the writing processing, the storage processing) to the frame memories is performed. The reading processing may be performed through the line buffers Lb1, Lb2, Lb3.
Accordingly to this embodiment, the motion picture profile deterioration which is generated at the time of displaying the motion picture on the typical holding-type liquid crystal display device can be eliminated, whereby it is possible to provide a motion picture display of high luminance and the high quality.
The fourfold speed clock synthesizer QSN generates a fourfold speed clock signal 4×DCLK and a double speed clock signal 2×DCLK from the clock signals DCLK. Further, a DRAM capable of responding to a DDR is used at frame memories fm1, fm2, thus providing a constitution which enables rapid access using the fourfold clock signal. Here, the double speed clock signal 2×DCLK becomes an output reference clock for the drain drivers. Since this embodiment is equal to the first embodiment shown in
Simultaneously with this timing, the data stored in the frame memory fm2 IS read out using the fourfold speed clock signal 4×DCLK, and the data is temporarily held in the line buffer Lb2. The data which is temporarily held in the line buffer Lb2 becomes display data of the first field. The data which is temporarily held in the line buffer Lb2 is read out using the double speed clock signal 2×DCLK and is transferred to drain drivers of the liquid crystal display panel through an output processing circuit DOP. All display data for the first field (corresponding to 120 Hz) that is stored in the frame memory fm2 is read out and displayed on a liquid crystal display panel. Subsequently, the operation of the second field is executed.
In the operation of the second field, the data stored in the frame memories fm2, fm1 are simultaneously read out using the fourfold speed clock signal 4×DCLK. Here, the display data stored in the frame memory fm1 becomes the comparison reference data and the display data stored in the frame memory fm2 becomes the comparison data. The contents (one pixel unit) of the display data stored in the frame memory fm1 and the contents (one pixel unit, same in-screen display address) of the display data stored in the frame memory fm2 are compared with each other. When the display data stored in the frame memory fm1 is darker than the display data stored in the frame memory fm2, black display data is transferred to the drain drivers through the output processing circuit DOP as display data of an address corresponding to the black display data. On the other hand, when the display data stored in the frame memory fm1 is brighter than the display data stored in the frame memory fm2, white display data is transferred to the drain drivers through the output processing circuit DOP as display data of an address corresponding to the white display data.
This processing is executed with respect to all display pixels (for one screen) of the liquid crystal display panel. Since the operations (reading out of display data from frame memories and display data transfer processing to respective drain drivers) on the second field are also executed using the double-speed clock signal as a reference, the processing of the black display/white display is completed within the second field. In the next video frame ((n+2) frame) inputting, the display data of the (n+2) frame is stored in the frame memory fm2, wherein the data stored in the frame memory fm1 provides the display data of the first field and the comparison data in the second field, while the display data stored in the frame memory fm2 becomes the comparison reference data in the second field. Hereinafter, this processing is repeated.
Also, in this embodiment, the motion picture profile deterioration, which is generated at the time of displaying a motion picture on the typical holding-type liquid crystal display device, can be eliminated, whereby it is possible to provide a motion picture display of high luminance and high quality.
Here, in the above-mentioned respective embodiments, the storage capacitance of one frame memory is set to correspond to one frame. However, with the use of a high speed memory, such as a DDR, it is possible to constitute a memory corresponding to a plurality of frames using a single large-capacity, memory and it is also possible to execute processing using a high speed clock signal frequency, for example, an eightfold speed clock signal frequency. In this case, a constitution is provided which replaces the frame memories fm1 to fm3 shown in
Further, as a fourth embodiment of the present invention, a given gray scale value may be added to or subtracted from a gray scale value of the pixel of the (n+1)th frame in response to the comparison result of the comparison circuit COMP shown in
Further, the embodiment shown in
The backlight BL is of a so-called side edge type which is constituted of a light guide body GLB and a cold cathode fluorescent lamp CFL. On a back surface of the backlight BL, an interface printed circuit board PCB is mounted. On the interface printed circuit board PCB, the timing controller Tcon, the double speed clock synthesizer DSN (or fourfold speed clock synthesizer QSN), the frame memories fm (fm1 to fm3 or fm1 and fm2), have been discussed which in connection with the previously-described embodiments, are mounted, and these parts are connected with the drain driver DR and the gate driver GR (the gate driver GR not shown in the drawing) using a flexible printed circuit board FPC.
An explanation of the overdrive driving will be made hereinafter. The overdrive driving is driving in which the display data signal of one preceding frame and the present display data signal are compared to each other with respect to respective colors R, G, B, and the luminance data which exceeds a gray scale change quantity is inputted to a signal line driving circuit so as to increase the change quantity, whereby the response speed of the liquid crystal is enhanced.
As the above-mentioned frame memory, a memory such as a DRAM having 32 bits has been generally used. Here, although the details of the inner structure of the above-mentioned comparator and the arithmetic operation part, the timing and the like are not described here, they are not specifically limited. The display data may be supplied from the image signal output device, such as a personal computer, for every one dot in series or for every two dots in parallel. Further, the display data may be supplied using differential signals for narrowing the width of the bus used for supplying the display data.
Along with the above-mentioned operations, the YUV data relating to the one preceding frame, which is already stored in the frame memory, is read out. Two YUV 16-bit signals are read out in parallel from the frame memory and are supplied to a YUV-RGB conversion circuit YTR. In the YUV-RGB conversion circuit YTR, opposite to the previously-mentioned RGB-YUV conversion circuit RTY, two input YUV 16-bit data are converted into two RGB 24-bit data. Two converted RGB 24-bit data are inputted to a parallel/serial conversion circuit P/S and are converted into serial RGB 24-bit data for one dot; and, thereafter, serial RGB 24-bit data is inputted to the comparator CP. In the comparator CP, the inputted display data of the present frame and the display data of one preceding frame, which is read out from the frame memory, are compared. Then, the overdrive arithmetic operation is performed by an arithmetic operation part OD, and a result of the arithmetic operation is outputted as RGB 24-bit data. The outputted RGB 24-bit data is inputted to the display control circuit CRL shown in
In the constitution shown in
Further, when the image signal output device outputs the RGB data for two dots, by transferring the serial/parallel conversion circuit shown in
Here, although not shown in the drawing, it is possible to apply the constitution shown in
By driving the liquid crystal display device using the method explained in connection with each embodiment, it is possible to realize a motion picture display of high luminance and high quality at a low cost without generating the motion picture profile deterioration.
Although an explanation has been made with respect to the example in which the above-mentioned liquid crystal display device adopts a side-edge type backlight, the present invention is not limited to such a liquid crystal display device, and the present invention is applicable to a liquid crystal display device with a so-called direct backlight in which a plurality of linear light sources are arranged on a back surface of the liquid crystal display panel. Further, the present invention is not limited to a liquid crystal display device, but is applicable to any display device provided that the display device is a hold-type display device.
As has been explained heretofore, according to the present invention, it is possible to enhance the motion picture display characteristics by obviating the generation of the motion picture profile deterioration particularly in a motion picture display in which a video moves, whereby it is possible to provide a display device of high quality and high luminance.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2003-183862 | Jun 2003 | JP | national |
| 2004-149575 | May 2004 | JP | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 6771243 | Hirohata | Aug 2004 | B2 |
| 20010048432 | Taniai et al. | Dec 2001 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 20040263462 A1 | Dec 2004 | US |
