Patent Grant
11024244
This application is the national phase entry of International Application No. PCT/CN2018/120582, filed on Dec. 12, 2018, which is based upon and claims priority to Chinese Patent Application No. 201810266840.0, filed on Mar. 28, 2018, the entire contents of which are incorporated herein by reference.
The present application relates to the technical field of display technology, and more particularly to a display device and a driving method thereof.
The statements provided herein are merely background information related to the present application, and do not necessarily constitute any prior arts. When a thin film transistor-liquid crystal display (TFT-LCD) displays normally, it requires a gate driver, a source driver, with a combination of criss-crossing scanning lines (Gate line) and data lines on the substrate to control each pixel thereby achieving a display of images.
A mode for driving a display includes: a color (for example: R/G/B) compression signal, a control signal and a power supply are transmitted to the control board via a system mainboard. After being processed by a timing controller (TCON) on the control board, the signals are transmitted to the source circuit and the gate circuit of the printed circuit board, and with the scanning lines, the data lines, the power supply and the other lines on the substrate, necessary data and power are transmitted to the display area, such that the display can obtain the power and signals required for displaying the images.
With the continuous improvement of requirements for resolution of display, 4K2K resolution of display can no longer meet people's pursuit of ultra-high definition images, and the subsequent 8K4K resolution of display gradually enters people's vision. There are two main methods to realize 8K4K display technology: (1) using a 8K4K timing control circuit to directly achieve 8K4K display effects. However, the development cost of related chips and integrated circuits (IC) is relatively high; (2) Using two 4K2K timing control circuits, the 4K2K image control signal is converted into 4K4K image control signal through a data processing, and then being input to the left and right half of the screen display area to complete the 8K4K display. However, this requires the timing control circuit to possess a function of data expansion, that is, to limit specifications and components of the timing control circuit.
An object of the present application is to provide a display device, including but not limited to solving a technical problem that 4K2K resolution of display can no longer satisfy people's pursuit of ultra-high-definition images.
In order to solve the aforesaid technical problem, a technical solution to be used by the embodiments of the present application is as follows:
A display device, which includes:
a display panel having a display area and a peripheral wiring area, where the display area is provided with a plurality of scanning lines, a plurality of data lines, a plurality of active switches, and a plurality of pixels, where the plurality of pixels are coupled to the plurality of active switches, respectively, and the plurality of active switches are electrically coupled between the plurality of scanning lines and the plurality of data lines, respectively;
a first drive circuit connected with the plurality of data lines, and the plurality of data lines defining a first data line group and a second data line group;
a second drive circuit connected with the plurality of scanning lines, and the plurality of scanning lines defining a plurality of scanning line groups;
a plurality of timing control circuits connected with the first drive circuit, and the plurality of timing control circuits includes a first timing control circuit and a second timing control circuit;
a signal transmission circuit configured to divide screen data into a plurality of display data according to display positions, and transmit the plurality of display data to the corresponding plurality of timing control circuits, respectively;
among them, the first timing control circuit is connected with the second drive circuit, and the first timing control circuit is configured to provide a plurality of gate activation signals, where the plurality of gate activation signals are corresponding to the plurality of scanning line groups, the second drive circuit is configured to control scans of the plurality of scanning line groups according to the plurality of gate activation signals;
the first timing control circuit and the second timing control circuit are configured to convert the plurality of display data into corresponding plurality of data signals, and send the plurality of data signals to the first drive circuit, where the first drive circuit is configured to adjust potentials of the first data line group and the second data line group according to the plurality of data signals.
Another object of the present application is to provide a driving method of a display device, which includes:
providing a first gate activation signal to a first scan circuit and a second scan circuit in the same period through a first timing control circuit and a second timing control circuit, respectively;
controlling a first line segment of a first scanning line group through the first scan circuit according to the first gate activation signal, and controlling a second line segment of the first scanning line group through the second scan circuit according to the first gate activation signal;
providing a second gate activation signal to the first scan circuit and the second scan circuit in the same period through the first timing control circuit and the second timing control circuit, respectively;
controlling a first line segment of a second scanning line group through the second scan circuit according to the second gate activation signal, and controlling a second line segment of the second scanning line group according to the second gate activation signal;
among them, the first timing control circuit is configured to sequentially provide the first gate activation signal and the second gate activation signal to the first scan circuit, and the second timing control circuit is configured to sequentially provide the first gate activation signal and the second gate activation signal to the second scan circuit.
The display device and the driving method thereof in accordance with the embodiments of the present application, through the division of labor for screen data transmission and the alternate switching control of scanning lines through the plurality of timing control circuits can better achieve the benefits of low-spec timing components controlling high-spec display panels. Since there is no need to adjust the manufacturing process significantly, the original process requirements and product cost can be maintained.
In order to explain the technical solution of embodiments of the present application more clearly, a brief introduction regarding the accompanying drawings that need to be used for describing the embodiments is given below; Obviously, the drawings in the following description are merely some embodiments of the present application, and for ordinarily skilled one in the art, other drawings can also be obtained according to the current drawings on the premise of paying no creative labor.
In order to make the objectives, technical solutions and advantages of the present application more comprehensible, the following further describes the present application in detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely used to explain the present application, and are not intended to limit the present application.
It should be noted that when a component is referred to as being “fixed to” or “arranged/provided on” another component, it can be directly or indirectly on the other component. When a component is referred to as being “connected to/with” another component, it can be directly or indirectly connected to the other component. The terms “upper”, “lower”, “left”, “right”, etc. indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are merely for ease of description, and do not indicate or imply the device or the element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limitations of the present application. For those of ordinary skill in the art, the specific meaning of the above terms can be understood according to specific conditions. The terms “first” and “second” are merely used for ease of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features. The meaning of “a plurality” means two or more than two, unless otherwise specifically defined.
Referring to
In an embodiment, the second drive circuit 105 and the first drive circuit 104 include but are not limited to a form of a chip-on-film.
A mode for driving a display device 200 includes: a system mainboard provides color (for example: R/G/B) compression signals, control signals and power transmission to the control board 100. After being processed by a timing controller (TCON) 101 on the control board 100, these signals together with the power source processed by the drive circuit, are transmitted to the second drive circuit 105 and the first drive circuit 104 of the printed circuit board 103 through a flexible flat cable (FFC) 102, the necessary data and power are transmitted to the display area 106 via the second drive circuit 105 and the first drive circuit 104, so that the display device 200 can obtain the power and signals required for displaying images.
To facilitate understanding please also refer to
Please refer to
a display panel having a display area 106 and a peripheral wiring area 109, where the display area is provided with a plurality of scanning lines 108, a plurality of data lines 107, a plurality of active switches T and a plurality of pixels P, where the plurality of pixels P are coupled to the plurality of active switches T, respectively, and the plurality of active switches T are electrically coupled between the plurality of scanning lines 108 and the plurality of data lines 107, respectively;
the first drive circuit 104 which is configured to be connected with a plurality of data lines 107, where the plurality of data lines 107 are divided into a plurality of data line groups, and the plurality of data line groups include a first data line group 107a and a second data line group 107b;
the second drive circuit 105 which is configured to be connected with a plurality of scanning lines 108, and the plurality of scanning lines 108 are divided into a plurality of scanning line groups;
the plurality of timing control circuits 101 which is configured to be connected with the first drive circuit 104, and the plurality of timing control circuits 101 include a first timing control circuit 101a and a second timing control circuit 101b;
a signal transmission circuit 300 which divides screen data into a plurality of display data according to the display position, and transmits the plurality of display data to the corresponding plurality of timing control circuits, respectively;
in which, the first timing control circuit 101a is connected with the second drive circuit 105, the first timing control circuit 101 is configured to provides a plurality of gate activation signals which is corresponding to a plurality of scanning line groups, and the second drive circuit 105 controls scans of the plurality of scanning line groups according to the plurality of gate activation signals;
the first timing control circuit 101a and the second timing control circuit 101b convert the plurality of display data into a plurality of data signals corresponded thereto, and send the plurality of data signals to the first drive circuit 104, there is one-to-one correspondence between the plurality of data signals and the plurality of data lines groups, and the first drive circuit 104 adjusts the potentials of the first data line group 107a and the second data line group 107b according to a plurality of data signals.
The display positions of the screen data corresponding to the plurality of display data are in one-to-one correspondence with the plurality of gate activation signals.
In an embodiment, the first drive circuit 104 may be, but is not limited to, a source drive circuit.
In an embodiment, the second drive circuit 105 may be, but is not limited to, a gate drive circuit.
In an embodiment, the plurality of display data includes a first display data and a second display data;
The signal transmission circuit transmits the first display data to the first timing control circuit 101a in segments according to the number of signal transmissions of the plurality of gate activation signals in one frame. For example, but not limited to, a total of two gate activation signal transmissions are performed in one frame, that is, the first display data is transmitted to the first timing control circuit 101a in two times. The signal transmission circuit transmits the second display data to the second timing control circuit 101b in segments according to the number of signal transmissions of the plurality of gate activation signals in one frame, for example, but not limited to, a total of two gate activation signal transmissions are performed in one frame, that is, the second display data is transmitted to the second timing control circuit 101b in two times.
In an embodiment, the first timing control circuit 101a generates the first data signal according to the first display data. The second timing control circuit generates a second data signal according to the second display data. The first drive circuit 104 controls the first data line group 107a according to the first data signal. The first drive circuit 104 controls the second data line group 107b according to the second data signal.
In an embodiment, the plurality of scanning line groups include a first scanning line group 108a and a second scanning line group 108b. The first timing control circuit 101a sequentially provides a first gate activation signal STV1 and a second gate activation signal STV2. The second drive circuit 105 controls the first scanning line group 108a according to the first gate activation signal STV1. The second drive circuit 105 controls the second scanning line group 108b according to the second gate activation signal STV.
In an embodiment, when the plurality of timing control circuits 101 send the first gate activation signal STV1, the screen data corresponding to the first scanning line group 108a at an image position is provided; and when the plurality of timing control circuits 101 send the second gate activation signal STV2, the screen data corresponding to the second scanning line group 108b at the image position is provided.
In an embodiment, the second drive circuit 105 includes a first scan circuit 105a and a second scan circuit 105b. The first scan circuit 105a is configured to obtain the first gate activation signal STV1 to control the first scanning line group 108a. The second scan circuit 105b is configured to obtain the second gate activation signal STV2 to control the second scanning line group 108b.
In an embodiment, each scanning line 108 of the plurality of scanning lines is divided into a first line segment 1081 and a second line segment 1082;
the first line segment 1081 is connected with the first scan circuit 105a; the second line segment 1082 is connected with the second scan circuit 105b;
the second drive circuit 105 includes a first scan circuit 105a and a second scan circuit 105b;
the first scan circuit 105a is connected with the first line segment 1081 of the plurality of scanning lines 108;
the second scan circuit 105b is connected with the second line segment 1082 of the plurality of scanning lines 108;
the first timing control circuit 101a sequentially provides the first gate activation signal STV1 and the second gate activation signal STV2 to the first scan circuit 105a, where the first scan circuit 105a controls the first line segment 1081 of the first scanning line group 108a according to the first gate activation signal STV1, and controls the first line segment 1081 of the second scanning line group 108b according to the second gate activation signal STV2;
the second timing control circuit 101b sequentially provides the first gate activation signal STV1 and the second gate activation signal STV2 to the second scan circuit 105b, where the second scan circuit 105b controls the second line segment 1082 of the first scanning line group 108a according to the first gate activation signal STV1, and controls the second line segment 1082 of the second scanning line group 108b according to the second gate activation signal STV2.
As shown in
The plurality of display data includes a first display data and a second display data. The signal transmission circuit transmits the first display data to the first timing control circuit 101a in segments according to the number of signal transmissions of the plurality of gate activation signals in one frame. The signal transmission circuit transmits the second display data to the second timing control circuit 101b in segments according to the number of signal transmissions of the plurality of gate activation signals in one frame. The first timing control circuit 101a generates a first data signal according to the first display data, and the second timing control circuit 101b generates a second data signal according to the second display data. The first data signal is transmitted to the first data circuit 104a, so that the first data circuit 104a controls the first data line group 107a; the second data signal is transmitted to the second data circuit 104b, so that the second data circuit 104b controls the second data line group 107b.
In an embodiment, the number of columns of the screen resolution of the display area is n times the number of columns of the screen resolution of the screen data processed by each timing control circuit, and the number of the plurality of timing control circuits is n.
The number of rows of the screen resolution of the display area is m times the number of rows of the screen resolution of the screen data processed by each timing control circuit, and the number of the plurality of gate activation signals is m; where n and m are positive integers.
In an embodiment, a display device includes:
the display panel having a display area 106 and a peripheral wiring area 109, where the display area is provided with a plurality of scanning lines 108, a plurality of data lines 107, a plurality of active switches T and a plurality of pixels P, where the plurality of pixels P are coupled to the plurality of active switches T, respectively, and the plurality of active switches T are electrically coupled between the plurality of scanning lines 108 and the plurality of data lines 107, respectively, where the plurality of scanning lines are divided into a first scanning line group and a second scanning line group, and the plurality of data lines are divided into a first data line group 107a and a second data line group 107b;
the first drive circuit 104 which includes a first data circuit and a second data circuit, the first data circuit is connected with the first scanning line group, and the second data circuit is connected with the second scanning line group;
the second drive circuit 105 which includes a first scan circuit and a second scan circuit, each scanning line is divided into a first line segment and a second line segment, where the first scan circuit is connected with the first line segment of the plurality of scanning lines, and the second scan circuit is connected with the second line segment of the plurality of scanning lines;
the first timing control circuit 101a is connected with the first data circuit and the first scan circuit;
the second timing control circuit 101b is connected with the second data circuit and the second scan circuit;
the signal transmission circuit 300 divides the screen data into a plurality of display data according to the display position, and transmits the corresponding first timing control circuit and the second timing control circuit respectively;
in which, the first timing control circuit 101a and the second timing control circuit 101b convert the received plurality of display data into a plurality of data signals corresponded thereto, and send the plurality of data signals to the first drive circuit 104, and the plurality of data signals are in one-to-one correspondence with the plurality of data line groups, and the first drive circuit 104 controls the potentials of the plurality of data line groups respectively according to the plurality of data signals;
the first timing control circuit sequentially provides the first gate activation signal and the second gate activation signal to the first scan circuit, where the first scan circuit controls the first line segment of the first scanning line group according to the first gate activation signal, and controls the first line segment of the second scanning line group according to the second gate activation signal;
the second timing control circuit sequentially provides the first gate activation signal and the second gate activation signal to the second scan circuit, where the second scan circuit controls the second line segment of the first scanning line group according to the first gate activation signal, and controls the second line segment of the second scanning line group according to the second gate activation signal;
the signal frequency of the first gate activation signal and the second gate activation signal is 60 Hz;
the plurality of display data includes a first display data and a second display data;
the signal transmission circuit transmits the first display data to the first timing control circuit in segments according to the number of signal transmission of the plurality of gate activation signals in one frame;
the signal transmission circuit transmits the second display data to the second timing control circuit in segments according to the number of signal transmission of the plurality of gate activation signals in one frame;
the display positions of the screen data corresponding to the plurality of display data are in one-to-one correspondence with the plurality of gate activation signals.
As shown in
Step S310, the first gate activation signal is provided to the first scan circuit 105a and the second scan circuit 105b in the same period through the first timing control circuit 101a and the second timing control circuit 101b, respectively.
Step S320, the first line segment 1081 of the first scanning line group 108a is controlled by the first scan circuit 105a according to the first gate activation signal, and the second line segment 1082 of the first scanning line group 108a is controlled by the second scan circuit 105b according to the first gate activation signal.
Step S330, the second gate activation signal is provided to the first scan circuit 105a and the second scan circuit 105b in the same period through the first timing control circuit 101a and the second timing control circuit 101b, respectively.
Step S340, the first line segment 1081 of the second scanning line group 108b is controlled by the first scan circuit 105a according to the second gate activation signal, and the second line segment 1082 of the second scanning line group 108b is controlled by the second scan circuit 105b according to the second gate activation signal.
In which, the first timing control circuit 101a sequentially provides the first gate activation signal and the second gate activation signal to the first scan circuit 105a, and the second timing control circuit 101b sequentially provides the first gate activation signal and the second gate activation signal to the second scan circuit 105b.
Please refer to
the display panel having a display area 106 and a peripheral wiring area 109, where the display area is provided with a plurality of scanning lines 108, a plurality of data lines 107, a plurality of active switches T and a plurality of pixels P, where the plurality of pixels P are coupled to the plurality of active switches T, respectively, and the plurality of active switches T are electrically coupled between the plurality of scanning lines 108 and the plurality of data lines 107, respectively;
the first drive circuit 104 which is connected with the plurality of data lines 107, the plurality of data lines 107 are divided into a plurality of data line groups, and the plurality of data line groups include a first data line group 107a and a second data line group 107b;
the second drive circuit 105 which is connected to the plurality of scanning lines 108, and the plurality of scanning lines 108 are divided into a plurality of scanning line groups;
the plurality of timing control circuits 101 which are connected with the first drive circuit 104, and the plurality of timing control circuits 101 include a first timing control circuit 101a and a second timing control circuit 101b;
the signal transmission circuit 300 which divides the screen data into a plurality of display data according to the display position, and transmits the plurality of display data to the corresponding plurality of timing control circuits respectively;
in which, the first timing control circuit 101a is connected with the second drive circuit 105, the first timing control circuit 101 sequentially provides a plurality of gate activation signals (STV), the plurality of gate activation signals correspond to a plurality of scanning line groups, and the second drive circuit 105 controls the scans of the plurality of scanning line groups according to plurality of gate activation signals;
the first timing control circuit 101a and the second timing control circuit 101b convert the plurality of display data into the corresponding plurality of data signals, and send the plurality of data signals to the first drive circuit 104, the plurality of data signals are in one-to-one correspondence with the plurality of data lines groups, where the first drive circuit 104 adjusts the potentials of the first data line group 107a and the second data line group 107b according to the plurality of data signals.
The display positions of the screen data corresponding to the plurality of display data are in one-to-one correspondence with the plurality of gate activation signals.
In an embodiment, the first drive circuit 104 may be, but is not limited to, a source drive circuit.
In an embodiment, the second drive circuit 105 may be, but is not limited to, a gate drive circuit.
In an embodiment, the plurality of display data includes a first display data and a second display data;
The signal transmission circuit transmits the first display data to the first timing control circuit 101a in segments according to the number of signal transmissions of the plurality of gate activation signals in one frame. For example, but not limited to, a total of two gate activation signal transmissions are performed in one frame, that is, the first display data is transmitted to the first timing control circuit 101a in two times; the signal transmission circuit transmits the second display data to the second timing control circuit 101b in segments according to the number of signal transmissions of the plurality of gate activation signals in one frame. For example, but not limited to, a total of two gate activation signal transmissions are performed in one frame, that is, transmits the second display data to the second timing control circuit 101b in two times.
In an embodiment, the first timing control circuit 101a generates a first data signal according to the first display data; the second timing control circuit generates a second data signal according to the second display data; the first drive circuit 104 controls the first data line group 107a according to the first data signal; the first drive circuit 104 controls the second data line group 107b according to the second data signal.
In an embodiment, the plurality of scanning line groups include a first scanning line group 108a and a second scanning line group 108b; the first timing control circuit 101a sequentially provides a first gate activation signal STV1 and a second gate activation signal STV2; the second drive circuit 105 controls the first scanning line group 108a according to the first gate activation signal STV1; the second drive circuit 105 controls the second scanning line group 108b according to the second gate activation signal STV2.
In an embodiment, when the plurality of timing control circuits 101 send the first gate activation signal STV1, the screen data corresponding to the first scanning line group 108a at am image position is provided; when the plurality of timing control circuits 101 send the second gate activation signal STV2, the screen data corresponding to the second scanning line group 108b at the image position is provided.
In an embodiment, the first timing control circuit 101a and/or the second timing control circuit 101b periodically and sequentially provide the plurality of gate activation signals STV.
In an embodiment, the first gate activation signal and the second gate activation signal have the same signal frequency. For example, but not limited to, the signal frequency of the first gate activation signal STV1 and the second gate activation signal STV2 is 60 Hz.
In an embodiment, the alternate signal frequency of the first gate activation signal STV1 and the second gate activation signal STV2 is 120 Hz.
In an embodiment, the number of columns of the screen resolution of the display area 106 is n times the number of columns of the screen resolution of the screen data processed by each timing control circuit 101, and the number of the plurality of timing control circuits 101 is n; the number of rows of the screen resolution of the display area 106 is m times the number of rows of the screen resolution of the screen data processed by each timing control circuit 101, and the number of the plurality of gate activation signals STV is m; where n and m are positive integers. For example, but not limited to, the number of columns of the screen resolution of the display area 106 is 8k, and the number of columns of the screen resolution of the screen data processed by each timing control circuit 101 is 4k, and the umber of the plurality of timing control circuits 101 is 2; the number of rows of the screen resolution of the display area 106 is 4k, the number of rows of the screen resolution of the screen data processed by each timing control circuit 101 is 2k for, and the umber of the plurality of gate activation signals STV is 2.
In an embodiment of the present application, the signal transmission circuit 300 divides a screen data into left-screen data and right-screen data, and transmits them to the first timing control circuit 101a and the second timing control circuit 101b, respectively. The signal transmission circuit 300 transmits the left-screen data to the first timing control circuit 101a in two times, one for the upper left-screen data and the other for the lower left-screen data. The first timing control circuit 101a, upon obtaining the upper left-screen data, sends the first gate activation signal STV1 to the first scan circuit 105a, and provides the upper left-screen data to the first data circuit 104a to perform a screen rendering of the upper left screen 106a. The first timing control circuit 101a, upon obtaining the bottom left-screen data, sends the second gate activation signal STV2 to the first scan circuit 105a, and provides the bottom left-screen data to the first data circuit 104a to perform the screen rendering of the bottom left screen 106b. Similarly, the signal transmission circuit 300 transmits the right-screen data to the second timing control circuit 101b in two times, one for the upper right-screen data, and the other for the lower right-screen data. The second timing control circuit 101b upon obtaining the upper right-screen data, sends the first gate activation signal STV1 to the second scan circuit 105b, and provides the upper right-screen data to the second data circuit 104b to perform the screen rendering of the upper right screen 106c.
The second timing control circuit 101b upon obtaining the bottom right-screen data, sends a second gate activation signal STV2 to the second scan circuit 105b, and provides the bottom right-screen data to the second data circuit 104b to perform the screen rendering of the bottom right screen screen 106d.
The first timing control circuit 101a and the second timing control circuit 101b synchronously transmit the first gate activation signal STV1 and the second gate activation signal STV2; and the first timing control circuit 101a and the second timing control circuit 101b in response to the previous frame (after STV1 trigger) synchronously processes the upper screen data of the same screen, and synchronously processes the lower screen data of the same screen at the next frame (after STV2 trigger).
In an embodiment, the first gate activation signal and the second gate activation signal have the same signal frequency.
In an embodiment, the driving method also includes dividing the screen data into a plurality of display data according to the display position through the signal transmission circuit, and the plurality of display data are respectively transmitted to the corresponding first timing control circuit or the second timing control circuit, where the first timing control circuit is connected with the second drive circuit, and the second drive circuit is configured to be connected with the scanning line.
In an embodiment, the driving method also includes: transmitting a plurality of data signals to a first drive circuit through the first timing control circuit and the second timing control circuit according to the obtained display data, respectively, where the first drive circuit is configured to be connected with data lines. The data lines is divided into a first data line group and a second data line group, and the first drive circuit controls the potentials of the first data line group and the second data line group respectively according to the plurality of data signals.
In an embodiment, the screen data includes a first display data and a second display data; the signal transmission circuit transmits the first display data to the first timing control circuit in segments according to the number of signal transmissions of the first gate activation signal in one frame; and the signal transmission circuit transmits the second display data to the second timing control circuit in segments according to the number of signal transmissions of the second gate activation signal in one frame.
In an embodiment, the first timing control circuit generates a first data signal according to the first display data; the second timing control circuit generates a second data signal according to the second display data; the first drive circuit controls the first data line group according to the first data signal; and the first drive circuit controls the second data line group according to the second data signal.
In an embodiment, when the first timing control circuit and/or the second timing control circuit send/sends the first gate activation signal, providing the screen data corresponds to the first scanning line group at an image position; and when the first timing control circuit and/or the second timing control circuit upon send/sends the second gate activation signal, providing the screen data corresponding to the second scanning line group at the image position.
In the present application, the division of labor for screen data transmission and the alternate switching control of scanning lines through the plurality of timing control circuits can better achieve the benefits of low-spec timing components controlling high-spec display panels. Since there is no need to adjust the manufacturing process significantly, the original process requirements and product cost can be maintained.
In some embodiments, the display panel described in the present application may be, for example, but not limited to, a liquid crystal display panel, and it may also be an organic light-emitting diode (OLED) display panel, and a white light-emitting diode (W-OLED) display panel, a Quantum Dot Light Emitting Diodes (QLED) display panels, a plasma display panel, a curved display panel or other types of display panels.
The above disclosures are merely optional embodiments of the present application, and are not intended to limit the present application. Any modification, equivalent replacement and improvement made within the spirit and principle of the present application shall be included by the protection scope of the present application.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201810266840.0 | Mar 2018 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2018/120582 | 12/12/2018 | WO | 00 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO2019/184453 | 10/3/2019 | WO | A |
| Number | Name | Date | Kind |
|---|---|---|---|
| 20160055801 | Kim et al. | Feb 2016 | A1 |
| 20170098431 | Oh | Apr 2017 | A1 |
| 20180182278 | Kim | Jun 2018 | A1 |
| Number | Date | Country |
|---|---|---|
| 101447156 | Jun 2009 | CN |
| 203351179 | Dec 2013 | CN |
| 105554423 | May 2016 | CN |
| 107742504 | Feb 2018 | CN |
| 108320694 | Jul 2018 | CN |
| 20140123625 | Oct 2014 | KR |
| Number | Date | Country | |
|---|---|---|---|
| 20210020133 A1 | Jan 2021 | US |
