Patent Grant
9972260
The present disclosure relates to a display device, particularly to a display device applied to a display system having a PSR (Panel Self Refresh) function.
The display system includes a system unit that receives a video signal output from an external signal source (host) and a display device that receives the video signal, output from the system unit, to display an image. The display device includes a display panel that displays the image, a drive circuit that drives the display panel, and a control circuit that controls the drive of the drive circuit. In recent years, a PSR technology is proposed as a technology of reducing power consumption of the whole display system (See Japanese unexamined published patent application No. 2013-190777).
In the PSR technology, in a case where image data (frame image data) in units of frames in the video signal output from the host is a still image, frame image data output operation of the system unit is stopped, and the display is performed using the frame image data stored in a storage unit of the control circuit. In the display system having the PSR function, the output operation of the system unit can be stopped while the still image is displayed, so that power consumption of the display system can be reduced as a whole.
However, in the display device applied to the display system, there is a problem in that display quality is degraded by a flicker. A principle of generation of the flicker will be described below.
In the PSR technology, in order to reduce the power consumption, a drive frequency at which the still image is displayed is set lower than a drive frequency at which a moving image is displayed. While the system unit is in a stopped state, the control circuit outputs the frame image data from the storage unit in asynchronization with the system unit. Therefore, timing at which the frame image data in the video signal output from the host is switched from a still image to a moving image deviates from timing at which a frame period of a still image output from the storage unit is ended. When the deviation is generated, a vertical retrace period (blanking period BR1) is lengthened in the frame image data (the image data of a frame 3 in
The present disclosure has been made in view of the above circumstances and an object of the present disclosure is to improve the display quality in the display device to which the PSR function is applied.
In one general aspect, the instant application describes a display device including a processor that performs processing on each frame of image data that includes plural frames, the display device displaying an image on a display screen based on the image data processed by the processor, the processor receiving the image data, a first control signal indicating a command to stop output of the image data, and a second control signal indicating a command to perform the output of the image data, and a memory in which the image data received immediately before stop of transmission of the image data is stored as internal image data. The processor includes a first display mode in which the processor displays the image on the display screen from the internal image data after the processor receives the first control signal; and a second display mode in which the processor displays the image on the display screen from the image data received by the processor after the processor receives the second control signal. The display device further includes a calculator that calculates a blanking period between a writing end time point of the internal image data corresponding to a final frame immediately before switching from the first display mode to the second display mode and a writing start time point of the image data corresponding to an initial frame immediately after switching from the first display mode to the second display mode, and an adjuster that adjusts at least one of a vertical retrace period, a horizontal retrace period, and a clock frequency, which correspond to the internal image data, depending on the blanking period.
The above general aspect may include one or more of the following features. The adjuster may keep a writing time duration corresponding to the internal image data constant, and may adjust the vertical retrace period corresponding to the internal image data.
The adjuster may adjust at least one of the vertical retrace period, the horizontal retrace period, and the clock frequency such that the vertical retrace period corresponding to the internal image data corresponding to the final frame is shorter than the blanking period.
In one general aspect, the instant application describes a display device including a processor that performs processing on each frame of image data that includes plural frames, the display device displaying an image on a display screen based on the image data processed by the processor, the processor receiving the image data, a first control signal indicating a command to stop output of the image data, and a second control signal indicating a command to perform the output of the image data, and a memory in which the image data received immediately before stop of transmission of the image data is stored as internal image data. The processor includes a first display mode in which the processor displays the image on the display screen from the internal image data after the processor receives the first control signal, and a second display mode in which the processor displays the image on the display screen from the image data received by the processor after the processor receives the second control signal. The display device further includes a calculator that calculates a blanking period between a writing end time point of the internal image data corresponding to a final frame immediately before switching from the first display mode to the second display mode and a writing start time point of the image data corresponding to an initial frame immediately after switching from the first display mode to the second display mode, and an interpolator that interpolates interpolation image data based on the internal image data in the blanking period when the blanking period is larger than a predetermined period.
The interpolator may further adjust at least one of the vertical retrace period, the horizontal retrace period, and the clock frequency, which correspond to the interpolation image data, depending on the blanking period.
The interpolator may interpolate the interpolation image data when the blanking period becomes equal to or larger than a half of one frame period of the internal image data.
The interpolator may adjust at least one of the vertical retrace period, the horizontal retrace period, and the clock frequency such that the vertical retrace period corresponding to the internal image data corresponding to the final frame is shorter than the blanking period.
In one general aspect, the instant application describes a method for driving a display device including a processor that performs processing on each frame of image data that includes plural frames, the display device displaying an image on a display screen based on the image data processed by the processor. The method includes receiving, with the processor, the image data, a first control signal indicating a command to stop output of the image data, and a second control signal indicating a command to perform the output of the image data, and storing as internal image data in a memory the image data received immediately before stop of transmission of the image data. The processor includes a first display mode in which the processor displays the image on the display screen from the internal image data after the processor receives the first control signal; and a second display mode in which the processor displays the image on the display screen from the image data received by the processor after the processor receives the second control signal. The processor calculates a blanking period between a writing end time point of the internal image data corresponding to a final frame immediately before switching from the first display mode to the second display mode and a writing start time point of the image data corresponding to an initial frame immediately after switching from the first display mode to the second display mode, and adjusts at least one of a vertical retrace period, a horizontal retrace period, and a clock frequency, which correspond to the internal image data, depending on the blanking period.
In the display device of the present disclosure and driving method thereof, the display luminance difference can be reduced when the PSR mode is switched to the normal mode. Therefore, the display quality can be improved in the display device to which the PSR function is applied.
Hereinafter, an exemplary embodiment of the present disclosure will be described with reference to the drawings. A liquid crystal display device is described below by way of example. However, a display device according to the present disclosure is not limited to the liquid crystal display device, but may be an organic EL display device and the like.
The receiving unit 101 receives a video signal output from the host. The receiving unit 101 transfers the received video signal to the storage unit 102 and the image determination unit 103 in each frame. Hereinafter, the video signal in one frame unit is referred to as frame image data (also referred to as image data).
The frame image data transferred from the receiving unit 101 is temporarily stored in the storage unit 102. For example, the storage unit 102 is configured as a frame memory.
The image determination unit 103 determines whether an image (frame image) indicated by the frame image data transferred from the receiving unit 101 is a moving image or a still image. Specifically, the image determination unit 103 determines whether a frame image of a current frame is the moving image or the still image based on the frame image data of the current frame transferred from the receiving unit 101 and the frame image data of a last frame or pieces of frame image data of a plurality of precedent frames, the frame image data and the pieces of frame image data being stored in the storage unit 102. For example, the image determination unit 103 detects a difference between the frame image data of the current frame and the frame image data of the last frame, determines that the current frame image is the moving image when the detected difference is larger than or equal to a threshold, and determines that the current frame image is the still image when the detected difference is less than the threshold. There is no limitation to the moving image and still image determination method, but any known method can be used. The image determination unit 103 transfers the frame image data of the current frame acquired from the receiving unit 101 to the operation controller 104 together with the determination result.
The operation controller 104 controls the operation of the system unit 100 based on the frame image data and the determination result, which are acquired from the image determination unit 103. Specifically, when the frame image is the moving image, the operation controller 104 causes the output unit 105 to output the frame image data. On the other hand, when the frame image is the still image, the operation controller 104 stops the frame image data output operation of the output unit 105.
Hereinafter, a case that the system unit 100 outputs the frame image data (moving image) is referred to as a normal mode, and a case that the system unit 100 does not output the frame image data (still image) is referred to as a PSR mode (low power consumption mode).
In a case where the frame image is switched from the moving image to the still image, the operation controller 104 transfers the frame image data corresponding to the still image to the output unit 105 while a control signal for putting the PSR mode into an on state, namely, a first control signal PSR_ON indicating a command to stop the output of the frame image data is provided to the frame image data.
In a case where the frame image is switched from the still image to the moving image, the operation controller 104 transfers the frame image data corresponding to the moving image to the output unit 105 while a control signal for putting the PSR mode into an off state (normal mode), namely, a second control signal PSR_OFF indicating a command to execute the output of the frame image data is provided to the frame image data.
After the frame image is switched from the still image to the moving image, the operation controller 104 transfers only the frame image data to the output unit 105 while the frame image data indicating the moving image is input to the system unit 100 (normal mode period).
The operation controller 104 is not limited to the above configuration. For example, the operation controller 104 may provide a flag (for example, flag “0”) indicating the moving image or a flag (for example, flag “1”) indicating the still image to each piece of frame image data based on the determination result. Specifically, the operation controller 104 may generate a packet including the flag and the frame image data, and sequentially output the generated packet from the output unit 105.
The output unit 105 outputs the frame image data, the frame image data to which the first control signal PSR_ON is provided, and the frame image data to which the second control signal PSR_OFF is provided, all the pieces of frame image data being acquired from the operation controller 104, to the liquid crystal display device 200.
In the PSR mode period, the operation controller 104 may stop the operation to transfer the frame image data to the output unit 105, or the operation controller 104 may stop the frame image data output operation of the output unit 105. Because the video signal is continuously input in the PSR mode period, the determination processing of the image determination unit 103 and the control processing of the operation controller 104 are continued.
In the above configuration of the system unit 100, the image data output operation of the system unit 100 is stopped while the host supplies the video signal (image data) corresponding to the still image. Therefore, the power consumption of the system unit 100 can be reduced.
The system unit 100 outputs various timing signals (such as a vertically synchronous signal, a horizontally synchronous signal, and a clock signal) to the liquid crystal display device 200.
The specific configuration of the liquid crystal display device 200 will be described with reference to
The image processing controller 10 performs processing of reducing the display luminance difference based on a characteristic (the moving image or still image) of the frame image. The display luminance means apparent brightness when the frame image is displayed on the display screen of the display panel 40.
Based on various timing signals supplied from the system unit 100, the image processing controller 10 generates various control signals (such as a data start pulse DSP, a data clock DCK, a gate start pulse GSP, and a gate clock GCK) in order to control the operations of the data line driving circuit 20 and gate line driving circuit 30. The image processing controller 10 outputs the generated data start pulse DSP and data clock DCK to the data line driving circuit 20. The image processing controller 10 outputs the generated gate start pulse GSP and gate clock GCK to the gate line driving circuit 30. As a detail will be described later, the image processing controller 10 performs processing of adjusting a timing of outputting each of the above various control signals.
The image processing controller 10 includes a receiving unit 11, a transfer controller 12, a storage unit 13, a data acquisition unit 14, a calculator 15, and a luminance adjuster 16.
The receiving unit 11 receives the frame image data, the frame image data to which the first control signal PSR_ON is provided, and the frame image data to which the second control signal PSR_OFF is provided, all the pieces of frame image data being output from the system unit 100. In
When the frame image indicated by the frame image data acquired from the receiving unit 11 is the still image, the transfer controller 12 transfers the frame image data to the storage unit 13 and the data acquisition unit 14. On the other hand, when the frame image indicated by the frame image data acquired from the receiving unit 11 is the moving image, the transfer controller 12 transfers the frame image data to the data acquisition unit 14.
Specifically, in a case where the first control signal PSR_ON is provided to the frame image data acquired from the receiving unit 11, the transfer controller 12 transfers the frame image data to the storage unit 13 and the data acquisition unit 14. On the other hand, in a case where the second control signal PSR_OFF is provided to the frame image data acquired from the receiving unit 11, the transfer controller 12 transfers the frame image data to the data acquisition unit 14. The transfer controller 12 transfers the frame image data acquired from the receiving unit 11 to the data acquisition unit 14 until the frame image data to which the first control signal PSR_ON is provided is input to the image processing controller 10 since the frame image data to which the second control signal PSR_OFF is provided is input to the image processing controller 10. In the configuration in which the flag (“0” or “1”) is provided to the frame image data, the transfer controller 12 performs frame image data transfer processing based on the flag.
In the example of
The frame image data, which is transferred from the transfer controller 12 and indicates the still image, is stored in the storage unit 13. For example, the storage unit 13 is configured as a frame memory. The pieces of image data of the frames 1, 2, and 3 in
According to predetermined timing, the data acquisition unit 14 acquires the frame image data transferred from the transfer controller 12 or the frame image data stored in the storage unit 13. The data acquisition unit 14 outputs the acquired frame image data to the data line driving circuit 20.
In the example of
Thus, the data acquisition unit 14 acquires the image data from the transfer controller 12 or the storage unit 13 based on the timing to receive the second control signal PSR_OFF and the timing to start and end the image data frame period. A display mode, in which the data acquisition unit 14 acquires the frame image data indicating the moving image and the display operation is performed based on the frame image data, corresponds to the normal mode (second display mode). In
The calculator 15 calculates a vertical retrace period (blanking period) in the frame image data indicating the still image at the time immediately before the display mode is switched from the PSR mode to the normal mode. Specifically, the calculator 15 calculates the period (blanking period) from a writing end time point of the frame image data (corresponding to the still image), which is acquired by the data acquisition unit 14 and stored in the storage unit 13, to a writing start time point of the frame image data (corresponding to the moving image) that is acquired next from the transfer controller 12 by the data acquisition unit 14m, when the receiving unit 11 receives the second control signal PSR_OFF.
In the example of
At this point, when the blanking period BR1 becomes longer, as illustrated in
The determination processor 16 performs processing of reducing the display luminance difference. Specifically, based on the blanking period BR1 acquired from the calculator 15, the determination processor 16 generates a control signal in order to adjust at least one of a vertical retrace period of the frame image data, a horizontal retrace period of the frame image data, and a clock frequency, and outputs the generated control signal (for example, a data start pulse DSP, a data clock DCK, a gate start pulse GSP, and a gate clock GCK) to the data line driving circuit 20 and the gate line driving circuit 30. For example, the determination processor 16 generates the control signal in which operating timing of the data start pulse DSP, data clock DCK, gate start pulse GSP, and gate clock GCK, which are generated in the image processing controller 10, is adjusted according to the blanking period BR1. And the determination processor 16 outputs the determination result to the data acquisition unit 14. A specific configuration example of the determination processor 16 will be described later.
The data line driving circuit 20 supplies a grayscale voltage to a plurality of data lines DL based on the control signal (data start pulse DSP, data clock DCK and the like) output from the determination processor 16 and the frame image data (digital data) output from the luminance adjuster 14. Because a known configuration can be applied to the configuration of the data line driving circuit 20, the description is omitted.
The gate line driving circuit 30 sequentially supplies a gate signal to a plurality of gate lines GL based on the control signal (the gate start pulse GSP, gate clock GCK and the like) output from the image processing controller 16. Because a known configuration can be applied to the configuration of the gate line driving circuit 30, the description is omitted.
A specific configuration example of the determination processor 16 will be described below.
In a liquid crystal display device 200 according to a first exemplary embodiment, the determination processor 16 adjusts the vertical retrace period of the frame image data, and inserts (interpolates) the frame image data (the image data of the frame 3) (interpolation image data) indicating a still image in the blanking period BR1 of
The determination processor 16 determines whether the frame image data can be inserted in the blanking period BR1 of
The determination processor 16 outputs a determination result to the data acquisition unit 14. When the image data of the frame 3 can be inserted in the blanking period BR1, the determination processor 16 outputs the control signal (for example, the gate start pulse GSP) controlling the vertical retrace period to the gate line driving circuit 30 at a desired timing, and sets the vertical retrace periods of the frames 2 and 3 to a desired period (for example, vertical retrace period BR2 (BRx≤BR2<BR1)).
Based on the determination result, the data acquisition unit 14 acquires the frame image data, and outputs the acquired frame image data to the data line driving circuit 20. When the image data of the frame 3 can be inserted in the blanking period BR1, the data acquisition unit 14 acquires the image data of the frame 3 after acquiring the image data of the frame 2. On the other hand, when the image data of the frame 3 cannot be inserted in the blanking period BR1, the data acquisition unit 14 acquires the image data of the frame D after acquiring the image data of the frame 2.
In the example of
As illustrated in
In a liquid crystal display device 200 according to a second exemplary embodiment, the determination processor 16 adjusts the horizontal retrace period of the frame image data, and inserts the frame image data (the image data of the frame 3) indicating the still image in the blanking period BR1 of
The determination processor 16 determines whether the frame image data can be inserted in the blanking period BR1 of
The determination processor 16 outputs a determination result to the data acquisition unit 14. When the image data of the frame 3 can be inserted in the blanking period BR1, the determination processor 16 outputs the control signal (for example, the data start pulse DSP) controlling the horizontal retrace period to the data line driving circuit 20 at a desired timing, and sets the horizontal retrace period of the frame 3 to a desired period (for example, at least the horizontal retrace period of the threshold).
Based on the determination result, the data acquisition unit 14 acquires the frame image data, and outputs the acquired frame image data to the data line driving circuit 20. When the image data of the frame 3 can be inserted in the blanking period BR1, the data acquisition unit 14 acquires the image data of the frame 3 after acquiring the image data of the frame 2. On the other hand, when the image data of the frame 3 cannot be inserted in the blanking period BR1, the data acquisition unit 14 acquires the image data of the frame D after acquiring the image data of the frame 2.
In the example of
In a liquid crystal display device 200 according to a third exemplary embodiment, the determination processor 16 adjusts the clock frequency of the frame image data, and inserts the frame image data (the image data of the frame 3) indicating a still image in the blanking period BR1 of
The determination processor 16 determines whether the frame image data can be inserted in the blanking period BR1 of
The determination processor 16 outputs a determination result to the data acquisition unit 14. When the image data of the frame 3 can be inserted in the blanking period BR1, the determination processor 16 outputs the control signal (for example, the data clock DCK and the gate clock GCK) controlling the clock frequency to the data line driving circuit 20 and the gate line driving circuit 30 at a desired timing, and sets the clock frequency of the image data of the frame 3 to a desired frequency (for example, at least the clock frequency of the threshold).
Based on the determination result, the data acquisition unit 14 acquires the frame image data, and outputs the acquired frame image data to the data line driving circuit 20. When the image data of the frame 3 can be inserted in the blanking period BR1, the data acquisition unit 14 acquires the image data of the frame 3 after acquiring the image data of the frame 2. On the other hand, when the image data of the frame 3 cannot be inserted in the blanking period BR1, the data acquisition unit 14 acquires the image data of the frame D after acquiring the image data of the frame 2.
In the example of
A liquid crystal display device 200 according to a fourth exemplary embodiment may include at least one of the configurations of the first to third exemplary embodiments. That is, the liquid crystal display device 200 of the fourth exemplary embodiment may be configured by a proper combination of the first to third exemplary embodiments. For example, in the liquid crystal display device 200 according to the fourth exemplary embodiment, the vertical retrace period and clock frequency of the frame image data are adjusted to insert the frame image data (the image data of the frame 3) indicating a still image in the blanking period BR1 of
The determination processor 16 determines whether the frame image data can be inserted in the blanking period BR1 of
Then the determination processor 16 outputs the determination result of the second determination processing to the data acquisition unit 14. When the image data of the frame 3 can be inserted in the blanking period BR1 with respect to the second determination processing, the determination processor 16 outputs the control signal (for example, the gate start pulse GSP) controlling the vertical retrace period to the gate line driving circuit 30 at a desired timing, and outputs the control signal (for example, the data clock DCK and the gate clock GCK) controlling the clock frequency to the data line driving circuit 20 and the gate line driving circuit 30 at a desired timing. Therefore, the vertical retrace periods of the frames 2 and 3 are set to the vertical retrace period BRx, and the clock frequency of the image data of the frame 3 is set to a desired frequency (for example, at least the clock frequency of the threshold).
Based on the determination result of the second determination processing, the data acquisition unit 14 acquires the frame image data, and outputs the acquired frame image data to the data line driving circuit 20. When the image data of the frame 3 can be inserted in the blanking period BR1 with respect to the second determination processing, the data acquisition unit 14 acquires the image data of the frame 3 after acquiring the image data of the frame 2. On the other hand, when the image data of the frame 3 cannot be inserted in the blanking period BR1 with respect to the second determination processing, the data acquisition unit 14 acquires the image data of the frame D after acquiring the image data of the frame 2.
In the example of
In the configurations of the first to fourth exemplary embodiments, the image data (the image data of the frame 3) for one frame indicating a still image is inserted in the blanking period BR1 of
In the example of
The liquid crystal display device 200 according to the fifth exemplary embodiment is not limited to the above configuration.
For example, in the case where the blanking period BR1 in
In the first to fifth exemplary embodiments, when the image data (for example, the image data of the frame 3 in
In the case where the blanking period longer than a predetermined period is generated, the determination processor 16 may adjust at least one of the vertical retrace period, the horizontal retrace period, and the clock frequency such that the blanking period is dispersed into the plurality of frames. The configuration in
The liquid crystal display device 200 of the fifth exemplary embodiment may select one of the above configurations according to the determination result of the determination processor 16, and implement the selected configuration. For example, in the case where the blanking period in
The configuration in which the vertical retrace period and the horizontal retrace period are adjusted is not limited to the above configuration. For example, the vertical retrace period may be adjusted by adjusting a high-level period of a vertical synchronous signal (VSYNC). For example, the horizontal retrace period may be adjusted by adjusting a high-level period of a horizontal synchronous signal (HSYNC).
In each of the configurations, by way of an example, the image data indicating a still image is inserted in the blanking period BR1 of
As described above, the determination processor 16 acts as an adjuster that adjusts at least one of the vertical retrace period, the horizontal retrace period, and the clock frequency. The data acquisition unit 14 acts as an interpolator that inserts (interpolates) the frame image data in the blanking period.
Although the exemplary embodiments of the present disclosure are described above, the display device of the present disclosure is not limited to the exemplary embodiments. It is noted that an exemplary embodiment properly changed from the exemplary embodiments by those skilled in the art without departing from the scope of the present disclosure is included in the present disclosure.
This application is a bypass continuation of international patent application PCT/JP2014/001386, filed: Mar. 11, 2014 designating the United States of America, the entire disclosure of which is incorporated herein by reference.
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| Number | Date | Country |
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| Entry |
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| International Search Report dated May 27, 2014 in International (PCT) Application No. PCT/JP2014/001386. |
| Number | Date | Country | |
|---|---|---|---|
| 20160379580 A1 | Dec 2016 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2014/001386 | Mar 2014 | US |
| Child | 15261255 | US |
