Patent Application
20120127215
This Application claims priority of Japanese Patent Application No. 2010-238669, filed on Oct. 25, 2010, the entirety of which is incorporated by reference herein.
1. Field of the Invention
The present invention relates to a display device wherein a memory circuit is installed in each pixel, and an electronic device using the same.
2. Description of the Related Art
For a conventional display device having a plurality of pixels arranged in a matrix formed by rows and columns, when an image is displayed, data is written to the pixels by a driver under an image display mode or dynamic image display mode. Especially, when a static image is displayed, the same data is continuously written to the pixels. Therefore, a technique is provided, wherein a memory is installed in each pixel so that when a static image is displayed, the data stored in the memory is written to the pixel. In this regard, driving of the driver can be stopped to reduce power consumption. This technique is usually called an MIP (Memory in Pixel) technique.
Generally, in the MIP technique, a memory circuit for storing data is adopted with a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory). The SRAM is constituted by a transistor sequential circuit. On the other hand, the DRAM is constituted by a transistor and a capacitor. Therefore, in view of minification of the circuit area and narrowing of the pixel gap, the DRAM is preferred. However, a DRAM needs a refresh operation to hold tiny electric charges stored in the capacitor. An example for a pixel circuit using DRAM is described in International publication no. 2004/090854(A1) pamphlet (Patent document 2).
However, in a normally black type liquid crystal display device, which displays black color when no voltage is applied to the liquid crystal cell, if a DRAM is used to construct the MIP circuit, flicker would occur while white color is displayed.
The invention provides a display device wherein a memory circuit is installed in each pixel but flicker does not occur, and an electronic device using the same.
A detailed description is given in the following embodiments with reference to the accompanying drawings.
To achieve the above purpose, the invention provides a display device, comprising: a plurality of pixels arranged in a matrix, wherein each pixel has a first electrode, a second electrode, a light-transmittive element controlling the amount of transmissive light in response to a voltage difference between the first electrode and the second electrode, and a memory circuit storing the voltage level of the first electrode; and a controller refreshing the memory circuit periodically. In the case where the first electrode has a positive voltage level with respect to the second electrode at a refresh timing, the controller makes the memory circuit store the voltage level of the first electrode, applies a first predetermined voltage to the second electrode to increase the voltage level of the first electrode by the first predetermined voltage, and discharges the first electrode, so that the first electrode has a negative voltage level with respect to the second electrode.
In an embodiment, in the case where the first electrode has a negative voltage level with respect to the second electrode at a refresh timing, the controller makes the memory circuit store the voltage level of the first electrode, applies a second predetermined voltage which is lower than the first predetermined voltage to the second electrode and the first predetermined voltage to the first electrode to precharge the light-transmittive element, so that the first electrode has a positive voltage level with respect to the second electrode.
In an embodiment, the memory circuit has a DRAM.
In an embodiment, the display device further comprises: a plurality of source lines disposed respectively for each column of the plurality of pixels to apply data signals to the plurality of pixels; and a plurality of gate lines disposed respectively for each row of the plurality of pixels to apply control signals to the plurality of pixels to control the application of the data signals. Each pixel has a first switch element disposed between a corresponding source line and the first electrode, wherein the first switch element connects the first electrode to the corresponding source line in response to the control signal from a corresponding gate electrode line. The memory circuit of each pixel comprises: a capacitor storing the voltage level of the first electrode; a second switch element disposed between the first electrode and the capacitor, wherein the second switch element is controlled by the controller to connect the first electrode to the capacitor; a third switch element disposed between the first electrode and the corresponding source line, wherein the third switch element is controlled by the controller to connect the first electrode to the corresponding source line to discharge the first electrode; and a fourth switch element disposed between the first electrode and the third electrode, wherein the fourth switch element has a control terminal connected to a node between the capacitor and the second switch element, and the fourth switch element is conducted in response to a voltage difference between the corresponding source line, which is connected to the fourth switch element via the third switch element, and the control terminal
In a modification of the display device, the first switch is not located between the corresponding source line and the first electrode. The first switch is included in the memory circuit of each pixel and arranged parallel with the fourth switch element. In this case, the third switch element is controlled by the controller to connect the first electrode to the corresponding source line via the first switch element, so that the voltage on the corresponding source line is applied to the first electrode.
In another modification of the display device, the parallel arrangement of the first switch element and the fourth switch element is substituted for the third switch element to be directly connected to the source line. Specifically, the fourth switch element is disposed between the third electrode and the corresponding source line and has a control terminal connected to a node between the capacitor and the second switch element, and the fourth switch element is conducted in response to a voltage difference between the corresponding source line and the control terminal to connect the third switch element to the corresponding source line.
In an embodiment, the first, second, third, and fourth switch elements are thin film transistors.
In an embodiment, the light-transmissive element is a liquid crystal cell and light is not allowed to pass through the liquid crystal cell when the voltage difference between the first electrode and the second electrode is zero.
In an embodiment, the display device can be embedded in an electronic device. The electronic device can be a battery-driven portable device which has limited power, such as a cell phone, a PDA, a portable player, or a portable game device, or a monitor showing an advertisement like a poster.
The invention provides a display device wherein a memory circuit is installed in each pixel but flicker does not occur, and an electronic device using the same
The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:
The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
The display panel 11 comprises a plurality of pixels P11˜Pnm (m and n are integers) arranged in a matrix formed by rows and columns. The display panel 11 further comprises a plurality of signal lines (also called source lines) S1, S2, . . . , and Sm arranged corresponding to the columns, and a plurality of scan lines (also called gate lines) G1, G2, . . . , and Gn arranged corresponding to the rows and orthogonal to the source lines S1, S2, . . . , and Sm.
The source driver 12 is a signal driving circuit which drives the source lines S1˜Sm according to data signals. The source driver 12 applies signal voltages to the pixels P11˜Pnm via the source lines S1˜Sm. The gate driver 13 is a gate line driving circuit which drives the gate lines in sequence. The gate driver 13 controls signal voltage applications for the pixels P11˜Pnm via the gate lines 17-1˜17-n. Specifically, the gate driver 13 drives pixel rows with an interlaced scan or progressive scan procedure so that the pixels on that pixel row are applied with signal voltages through the source lines. The common electrode driver 14 is a common electrode driving circuit which reverses a bias voltage applied to a common electrode of all pixels P11˜Pnm every frame via common electrode lines CE1, CE2, . . . , and CEn. The controller 15 synchronizes the source driver 12, the gate driver 13, and the common driver 14 together, and controls the above devices.
Each of the pixels P11˜Pnm comprises a light-transmissive element sandwiched between the pixel electrode and the common electrode. The light-transmissive element could be a liquid crystal cell which varies the amount of transmissive light in response to the voltage of two ends of the liquid crystal cell. The signal voltages are applied to the pixel electrodes in response to the scan signal, such that, a voltage difference is generated between the two ends of the liquid crystal cell (a two-end voltage of the liquid crystal cell is called in the following). The alignment of liquid crystal molecules is changed as a two-end voltage of the liquid crystal cell changes, so that the amount of transmissive light or reflective light can be varied by the liquid crystal cell. The pixels P11˜Pnm can utilize the characteristic of the light-transmissive element to perform displaying. Each of the pixels P11˜Pnm further comprises a memory circuit which stores a signal voltage applied to the pixel electrode. Under the static image displaying mode, each of the pixels P11˜Pnm performs displaying according to the voltage stored in an embedded memory rather than signal voltage applied by the source lines S1˜Sm. Therefore, under the static image displaying mode, the source driver 12 can be stopped. On the other hand, the display panel 11 still displays a static image.
The pixel Pji (i and j are integers, wherein 1≦i≦m and 1≦j≦n) is arranged at the cross region of the i-th source line Si and the j-th gate line Gj. Furthermore, a capacity storage line CSj is arranged for a pixel row in a manner parallel to the gate line Gj.
The pixel Pji comprises a pixel electrode 20, a first switch element 21, a liquid crystal cell 22, a charge storage capacitor 23, and a common electrode 24. Briefly, the liquid crystal cell 22 is represented by a capacitor connected between the pixel electrode 20 and the common electrode 24 in
The first switch element 21 is disposed between the pixel electrode 20 and the source line Si. The control terminal of the first switch element 21 is connected to the gate line Gj. The first switch element 21 is conducted in response to the scan signal from the scan line Gj, and the pixel electrode 20 is connected to the source line Si. Thus, the pixel electrode 20 is applied with a signal voltage from the source line Si. Generally, a thin film transistor (TFT) is adopted as the first switch element 21. In the embodiment, the first switch element 21 is represented by an N-type TFT, which is conducted when the scan signal is at a high level.
The charge storage capacitor 23 is disposed between the pixel electrode 20 and the capacity storage line CSj. The charge storage capacitor 23 holds the voltage difference between the pixel electrode 20 and the common electrode 24 during the period from the beginning of the non-conductive state (OFF) of the switch element 21 through the beginning of the next conductive state (ON) of the switch element 21. In some case, the charge storage capacitor 23 could be connected to the common electrode 24 rather than the capacity storage line CSj.
In addition to the pixel electrode 20, the first switch element 21, the liquid crystal cell 22, the charge storage capacitor 23, and the common electrode 24, the pixel Pji further comprises a memory circuit 25. The memory circuit 25 comprises second, third, and fourth switch elements 26˜28, and a sampling capacitor 29. The second, third, and fourth switch elements 26˜28 can be TFTs. In the embodiments the second, third, and fourth switch elements 26˜28 are represented by N-type TFTs. A terminal of the sampling capacitor 29 is connected to the source line Si and the other terminal of the sampling capacitor 29 is connected to the pixel electrode 20 via the second switch element 26.
Furthermore, a sampling line SMj and a refresh line REj traverse the pixel Pj1. A sampling line and a refresh line are disposed for a pixel row or column. In the embodiment, because pixels are selected with a unit of a row, the sampling line and the refresh line are disposed for each pixel row.
The control terminal of the second switch element 26 is connected to the sampling line SMj. The third switch element 27 and the fourth switch element 28 are connected in series between the pixel electrode 20 and the source line Si. The control terminal of the third switch element 27 is connected to the refresh line REj. The control terminal of the fourth switch element 28 is connected to a point between the sampling capacitor 29 and the second switch element 26. The sampling capacitor 29, the second, and the fourth switch elements 26, and 28 form a DRAM.
Following, the assumption of the liquid crystal display device of an embodiment of the invention is that the liquid crystal display device has the pixel circuit shown in
Under an initial state (˜T11), the voltage level (called “pixel voltage” in the following) Vpix of the pixel electrode 20 is at a high voltage level (for example, 5V), and the voltage level (called “common voltage” in the following) VCE of the common electrode 24 (and the capacity storage line CSj) is at a low voltage level (for example, 0V). Therefore, the two-end voltage of the liquid crystal cell 22 is +5V. Meanwhile, the first, second, third, and fourth switch elements 21, 26˜28 are turned off.
At timing T11, to sample the present pixel voltage Vpix, the voltage level on the sampling line SMj is raised to a high voltage level by the controller 14 and the second switch element 26 is turned on. Therefore, the voltage level (called “sampling voltage” in the following) VS between the second switch element 26 and the sampling capacitor 29 becomes a voltage level equivalent to a high voltage level. Although the voltage level on the sampling line SMj is pulled down to a low voltage level later at the timing T12, the sampling voltage VS is still maintained at a high voltage level because of the effect of the capacitor 29.
During the period T13˜T14, to precharge the display element 22 and the charge storage capacitor 23, the voltage level on the gate line Gj is raised to a high voltage level by the gate driver 13. Meanwhile, the voltage level on the source line Si is raised to a high voltage level by the source driver 12. Thus, the first switch element 21 is turned on and the pixel electrode 20 is connected to the source line Si. At the beginning of the precharge period T13, the common voltage VCE is raised to a high voltage level by the common electrode driver 14.
At the end of the precharge period T14, the voltage level on the gate line Gj is pulled down to a low voltage level by the gate driver 13 and the first switch element 21 is turned off. Following, the voltage level on the source line Si is pulled down to a low voltage level by the source driver 12 and the common voltage VCE is maintained at a high voltage level.
Next, at timing T15, the voltage level on the refresh line REj is raised to a high voltage level by the controller 14 and the third switch element 27 is turned on. The conductive terminal (source) of the fourth switch element 28 is connected to the source line Si via the third switch element 27, such that the voltage level at the conductive terminal of the fourth switch element 28 becomes a low voltage level. At this time, the sampling voltage VS at the control terminal of the fourth switch element 28 is at a high voltage level such that the fourth switch element 28 is turned on. Accordingly, the pixel electrode 20 is connected to the source line Si via the third switch element 27 and the fourth switch element 28, and the pixel voltage Vpix is at a low voltage level. At timing T16, the voltage level on the refresh line REj is pulled down to a low voltage level and the third switch element 27 is turned off.
Finally, the pixel voltage Vpix and the common voltage VCE are reversed with respect to the initial states; namely, a high voltage level is changed to a low voltage level, and vice versa. Therefore, the two-end voltage of the liquid crystal cell 22 is −5V, wherein the polarity has been reversed.
Under this state, at the next sampling timing T21, to sample the present pixel voltage Vpix, the voltage level on the sampling line SMj is raised to high by the controller 14 and the second switch element 26 is turned on. Therefore, the sampling voltage VS becomes a voltage level equivalent to a low voltage level. After that, at timing T22, the voltage level on the sampling line SMj is pulled down to a low voltage level.
During the period T23˜T24, to precharge the liquid crystal cell 22 and the charge storage capacitor 23, the voltage level on the gate line Gj is raised to a high voltage level by the gate driver 13. Meanwhile, the voltage level on the source line Si is raised to a high voltage level by the source driver 12. Thus, the first switch element 21 is turned on and the pixel electrode 20 is connected to the source line Si. Therefore, the pixel voltage Vpix is raised to a high voltage level. At the beginning of the precharge period T23, the common voltage VCE is pulled down to a low voltage level by the common driver 14.
At the end of the precharge period T24, the voltage level on the gate line Gj is pulled down to a low voltage level by the gate driver 13 and the first switch element 21 is turned off. Following, the voltage level on the source line Si is pulled down to a low voltage level by the source driver 12.
Next, at timing T25, the voltage level on the refresh line REj is raised to a high voltage level by the controller 14 and the third switch element 28 is turned on. The conductive terminal (source) of the fourth switch element 28 is connected to the source line Si via the third switch element 27, such that the voltage level at the conductive terminal of the fourth switch element 28 becomes a low voltage level. However, at this time, the sampling voltage VS at the control terminal of the fourth switch element 28 is at a low voltage level such that the fourth switch element 28 is still turned off. Because the fourth switch element 28 is turned off, the pixel electrode 20 is not connected to the source line Si, and the pixel voltage Vpix is maintained at a high voltage level. At timing T26, the voltage level on the refresh line REj is pulled down to a low voltage level and the third switch element 27 is turned off.
Finally, the pixel voltage Vpix and the common voltage VCE are reversed again, wherein a high voltage level is changed to a low voltage level, and vice versa. The pixel voltage Vpix and the common voltage VCE return back to the initial states. Therefore, the two-end voltage of the liquid crystal cell 22 is +5V, wherein the polarity has been reversed again.
However, according to the conventional driving scheme, in the operation where the polarity of the two-end voltage of the liquid crystal cell 22 changes from + to −, a period where the two-end voltage of the liquid crystal cell 22 is zero exists (from the beginning of the precharge period T13 to the beginning of the refresh period T15). Therefore, the pixel to display white color displays black color in this period. Suppose that the duration of the period where the two-end voltage of the liquid crystal cell 22 is zero is 100 μsec in the operation where the polarity of the two-end voltage of the liquid crystal cell 22 changes from + to −, though the duration is extremely short, a flicker can still be identified by human eyes during this period. In this case, shortening the refresh period is a way to solve this problem, but power consumption is raised, so adopting the MIP circuit in the pixel loses its purpose.
In
Under an initial state (˜T11), the pixel voltage Vpix is at a high voltage level, and the common voltage VCE is at a low voltage level. Therefore, the two-end voltage of the liquid crystal cell 22 is +5V. Meanwhile, the first, second, third, and fourth switch elements 21, 26˜28 are turned off.
At timing T11, to sample the present pixel voltage Vpix, the voltage level on the sampling line SMj is raised to a high voltage level by the controller 14 and the second switch element 26 is turned on. Therefore, the sampling voltage VS existing between the second switch element 26 and the sampling capacitor 29 becomes a voltage level equivalent to a high voltage level. Although the voltage level on the sampling line SMj is pulled down to a low voltage level later at the timing T12, the sampling voltage VS is still maintained at a high voltage level because of the effect of the capacitor 29.
During the period T13˜T14, the voltage level on the source line Si is raised to a high voltage level by the source driver 12 and the common voltage VCE is raised to a high voltage level by the common driver 14. Thus, because of capacitive coupling, the pixel voltage Vpix of the pixel electrode 20 is increased by the amount of the common voltage VCE applied to the common electrode 24, such that pixel voltage Vpix becomes +10V. Therefore, the two-end voltage of the liquid crystal cell never becomes 0V which can be seen in the conventional driving scheme. The two-end voltage of the liquid crystal cell is maintained at Vpix−VCE=(+10V)−(+5V)=+5V.
At the end of the precharge period T14, the voltage level on the source line Si is pulled down to a low voltage level by the source driver 12 and the common voltage VCE is maintained at a high voltage level.
Next, at timing T15, the voltage level on the refresh line REj is raised to a high voltage level by the controller 14 and the third switch element 27 is turned on. The conductive terminal (source) of the fourth switch element 28 is connected to the source line Si via the third switch element 27, such that the voltage level at the conductive terminal of the fourth switch element 28 becomes a low voltage level. At this time, the sampling voltage VS at the control terminal of the fourth switch element 28 is at a high voltage level such that the fourth switch element 28 is turned on. Accordingly, the pixel electrode 20 is connected to the source line Si via the third switch element 27 and the fourth switch element 28, and the pixel voltage Vpix is at a low voltage level. At timing T16, the voltage level on the refresh line REj is pulled down to a low voltage level and the third switch element 27 is turned off.
Finally, the pixel voltage Vpix and the common voltage VCE are reversed with respect to the initial states. Namely, a high voltage level is changed to a low voltage level, and vice versa. Therefore, the two-end voltage of the liquid crystal cell 22 is −5V, wherein the polarity has been reversed.
The operation where the polarity of the two-end voltage of the liquid crystal cell 22 changes from − to + is the same as the conventional driving scheme described in
According to the driving scheme shown in
Following, assume that a liquid crystal display device is a normally black type liquid crystal display device. Accordingly, a reverse driving operation of the pixel circuit shown in
Under an initial state (˜T11), the pixel voltage Vpix is at a high voltage level, and the common voltage VCE is at a low voltage level. Therefore, the two-end voltage of the liquid crystal cell 22 is +5V. Meanwhile, the first, second, third, and fourth switch elements 21, 26˜28 are turned off.
At timing T11, to sample the present pixel voltage Vpix, the voltage level on the sampling line SMj is raised to a high voltage level by the controller 14 and the second switch element 26 is turned on. Therefore, the sampling voltage VS between the second switch element 26 and the sampling capacitor 29 becomes a voltage level equivalent to a high voltage level. Although the voltage level on the sampling line SMj is pulled down to a low voltage level later at timing T12, the sampling voltage VS is still maintained at a high voltage level because of the effect of the capacitor 29.
During the period T13˜T14, to precharge the display element 22 and the charge storage capacitor 23, the voltage level on the gate line Gj is raised to a high voltage level by the gate driver 13, and the voltage level on the refresh line REj is raised to a high voltage level by the controller 14. Meanwhile, the voltage level on the source line Si is raised to a high voltage level by the source driver 12. Thus, the first switch element 21 and the third switch 27 are turned on, and the pixel electrode 20 is connected to the source line Si. At the beginning of the precharge period T13, the common voltage VCE is raised to a high voltage level by the common driver 14.
At the end of the precharge period T14, the voltage levels on the gate line Gj and the refresh line REj are pulled down to a low voltage level. The first switch element 21 and the third switch 27 are turned off. Following, the voltage level on the source line Si is pulled down to a low voltage level by the source driver 12 and the common voltage VCE is maintained at a high voltage level.
Next, at timing T15, the voltage level on the refresh line REj is raised to a high voltage level again by the controller 14 and the third switch element 27 is turned on. The conductive terminal (source) of the fourth switch element 28 is connected to the source line Si via the third switch element 27, such that the voltage level at the conductive terminal of the fourth switch element 28 becomes a low voltage level. At this time, the sampling voltage VS at the control terminal of the fourth switch element 28 is at a high voltage level such that the fourth switch element 28 is turned on. Accordingly, the pixel electrode 20 is connected to the source line Si via the third switch element 27 and the fourth switch element 28, and the pixel voltage Vpix is at a low voltage level. At timing T16, the voltage level on the refresh line REj is pulled down to a low voltage level and the third switch element 27 is turned off.
Finally, the pixel voltage Vpix and the common voltage VCE are reversed with respect to the initial states. Therefore, the voltage difference between two ends of the liquid crystal cell 22 is −5V, wherein the polarity has been reversed.
Under this state, at the next sampling timing T21, to sample the present pixel voltage Vpix, the voltage level on the sampling line SMj is raised to a high voltage level by the controller 14 and the second switch element 26 is turned on. Therefore, the sampling voltage VS becomes a voltage level equivalent to a low voltage level. After that, at timing T22, the voltage level on the sampling line SMj is pulled down to a low voltage level.
During the period T23˜T24, to precharge the liquid crystal cell 22 and the charge storage capacitor 23, the voltage level on the gate line Gj is raised to a high voltage level by the gate driver 13, and the voltage level on the refresh line REj is raised to a high voltage level by the controller 14. Meanwhile, the voltage level on the source line Si is raised to a high voltage level by the source driver 12. Thus, the first switch element 21 and the third switch element 27 are turned on and the pixel electrode 20 is connected to the source line Si. Therefore, the pixel voltage Vpix is raised to a high voltage level. At the beginning of the precharge period T23, the common voltage VCE is pulled down to a low voltage level by the common electrode driver 14.
At the end of the precharge period T24, the voltage levels on the gate line Gj and the refresh line REj are pulled down to a low voltage level. The first switch element 21 and the third switch element 27 are turned off. Following, the voltage level on the source line Si is pulled down to a low voltage level by the source driver 12.
Next, at timing T25, the voltage level on the refresh line REj is raised to a high voltage level by the controller 14 and the third switch element 28 is turned on. The conductive terminal (source) of the fourth switch element 28 is connected to the source line Si via the third switch element 27, such that the voltage level at the conductive terminal of the fourth switch element 28 becomes a low voltage level. However, at this time, the sampling voltage VS at the control terminal of the fourth switch element 28 is at a low voltage level such that the fourth switch element 28 is still turned off. Because the fourth switch element 28 is turned off, the pixel electrode 20 is not connected to the source line Si, and the pixel voltage Vpix is maintained at a high voltage level. At timing T26, the voltage level on the refresh line REj is pulled down to a low voltage level and the third switch element 27 is turned off.
Finally, the pixel voltage Vpix and the common voltage VCE are reversed again. The pixel voltage Vpix and the common voltage VCE return back to the initial states. Therefore, the voltage difference between two ends of the liquid crystal cell 22 is +5V, wherein the polarity has been reversed again.
From
Under an initial state (˜T11), the pixel voltage Vpix is at a high voltage level, and the common voltage VCE is at a low voltage level. Therefore, the two-end voltage of the liquid crystal cell 22 is +5V. Meanwhile, the first, second, third, and fourth switch elements 21, 26˜28 are turned off.
At timing T11, to sample the present pixel voltage Vpix, the voltage level on the sampling line SMj is raised to a high voltage level by the controller 14 and the second switch element 26 is turned on. Therefore, the sampling voltage VS existing between the second switch element 26 and the sampling capacitor 29 becomes a voltage level equivalent to a high voltage level. Although the voltage level on the sampling line SMj is pulled down to a low voltage level later at timing T12, the sampling voltage VS is still maintained at a high voltage level because of the effect of the capacitor 29.
During the period T13˜T14, the voltage level on the source line Si is raised to a high voltage level by the source driver 12 and the common voltage VCE is raised to a high voltage level by the common driver 14. Thus, because of capacitive coupling, the pixel voltage Vpix of the pixel electrode 20 is increased by the amount of the common voltage VCE applied to the common electrode 24. The pixel voltage Vpix becomes +10V. Therefore, the two-end voltage of the liquid crystal cell never becomes 0V which can be seen in the conventional driving scheme. The two-end voltage of the liquid crystal cell is maintained at Vpix−VCE=10V)−(+5V)=+5V.
At the end of the precharge period T14, the voltage level on the source line Si is pulled down to a low voltage level by the source driver 12 and the common voltage VCE is maintained at a high voltage level.
Next, at timing T15, the voltage level on the refresh line REj is raised to a high voltage level by the controller 14 and the third switch element 27 is turned on. The conductive terminal (source) of the fourth switch element 28 is connected to the source line Si via the third switch element 27, such that the voltage level at the conductive terminal of the fourth switch element 28 becomes a low voltage level. At this time, the sampling voltage VS at the control terminal of the fourth switch element 28 is at a high voltage level such that the fourth switch element 28 is turned on. Accordingly, the pixel electrode 20 is connected to the source line Si via the third switch element 27 and the fourth switch element 28, and the pixel voltage Vpix is at a low voltage level. At timing T16, the voltage level on the refresh line REj is pulled down to a low voltage level and the third switch element 27 is turned off.
Finally, the pixel voltage Vpix and the common voltage VCE are reversed with respect to the initial states. Therefore, the voltage difference between two ends of the liquid crystal cell 22 is −5V, wherein the polarity has been reversed.
The operation where the polarity of the voltage difference between two ends of the liquid crystal cell 22 changes from − to + is the same as the conventional driving scheme described in
According to the driving scheme shown in
In the case of a normally black type liquid crystal display device, whether the conventional driving scheme or the driving scheme of the invention is utilized, the timing chart of the reverse driving operation of the pixel circuit shown in
As described above, according to the driving scheme of the invention, in the operation where the polarity of the voltage difference between two ends of a light-transmissive element (for example, a liquid crystal cell) changes from + to − under the white state, a display device wherein a memory circuit is installed in each pixel does not flicker by omitting the precharge period.
The electronic device 100 in
The display device 10 has a pixel circuit (any one of pixel circuits shown in
While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2010-238669 | Oct 2010 | JP | national |
