Patent Application
20240381696
Embodiments according to the present disclosure relate to a display device and an electronic device.
In recent years, in a field of a display device that performs image display, a planar display device in which pixels (pixel circuits) including light emitting elements are arranged in a matrix form has been rapidly spread. For the planar display device, as the light emitting element of a pixel, an organic EL display device using a so-called current drive type electro-optical element in which light emission luminance changes according to a current value flowing through the device, for example, an organic electro luminescence (EL) element utilizing a phenomenon in which light is emitted when an electric field is applied to an organic thin film has been developed and commercialized.
In the pixel circuit, for example, a plurality of capacitors used for correction of variations in characteristics of transistors, assistance of capacitance of organic EL elements, and the like may be provided (See Patent Document 1).
However, when the plurality of capacitors is arranged in a plurality of layers, the number of steps increases and the cost increases. Furthermore, it may be difficult to increase the electrostatic capacitance of the capacitor due to layout restrictions and the like. In this case, for example, correction of variations in characteristics of the transistor and the like cannot be appropriately performed, and there is a possibility that it becomes difficult to improve display characteristics such as image quality.
Therefore, the present disclosure provides a display device and an electronic device that can further reduce the number of manufacturing steps and improve display characteristics.
In order to solve the problems described above, according to the present disclosure, provided is a display device including: a light emitting element; a first capacitor including a first electrode and a second electrode; a second capacitor including a third electrode and a fourth electrode; and a drive transistor that supplies, to the light emitting element, a current corresponding to a voltage accumulated in the first capacitor and a voltage accumulated in the second capacitor, in which the second electrode is electrically connected to the third electrode, and the second electrode and the third electrode are disposed in different layers.
The display device may further include a metal layer that is disposed in a layer different from the first capacitor and the second capacitor so as to overlap with the first electrode and the second electrode when viewed from a lamination direction, and is electrically connected to the second electrode and the third electrode.
The metal layer may be disposed so as to cover the first electrode and the second electrode when viewed from the lamination direction.
The metal layer may be disposed so as to overlap with the first electrode disposed so as to cover the second electrode when viewed from the lamination direction.
The first electrode may be electrically connected to a gate of the drive transistor, and the second electrode, the third electrode, and the metal layer may be electrically connected to a source of the drive transistor.
The first electrode may be electrically connected to a voltage supply wiring that supplies a predetermined voltage, and the second electrode, the third electrode, and the metal layer may be electrically connected to a gate of the drive transistor.
The metal layer may be disposed so as to overlap with a voltage supply wiring that supplies a predetermined voltage when viewed from the lamination direction.
The fourth electrode may be electrically connected to the voltage supply wiring.
The metal layer may be disposed so as to overlap with the first electrode electrically connected to a gate of the drive transistor when viewed from the lamination direction.
The first electrode electrically connected to the gate may be disposed so as to overlap with a signal line when viewed from the lamination direction, and the metal layer may be disposed in a layer between a layer in which the first electrode is disposed and a layer in which the signal line is disposed.
The display device may further include a plurality of columnar electrode portions provided so as to extend in the lamination direction and electrically connecting each of the second electrode and the third electrode to the metal layer, in which the metal layer may be disposed so as to electrically connect the second electrode and the third electrode via a plurality of the columnar electrode portions.
The first capacitor may accumulate a first voltage related to an operation of the drive transistor, and the second capacitor may accumulate a second voltage different from the first voltage.
A plurality of the capacitors may be at least one or more capacitors of a metal-insulator-metal (MIM) capacitor, a metal-oxide-metal (MOM) capacitor, and a metal-oxide-semiconductor (MOS) capacitor.
According to the present disclosure, provided is an electronic device including: a light emitting element; a first capacitor including a first electrode and a second electrode; a second capacitor including a third electrode and a fourth electrode; and a drive transistor that supplies, to the light emitting element, a current corresponding to a voltage accumulated in the first capacitor and a voltage accumulated in the second capacitor, in which the second electrode is electrically connected to the third electrode, and the second electrode and the third electrode are disposed in different layers.
Hereinafter, embodiments of a display device and an electronic device will be described with reference to the drawings. Although main configuration parts of the display device and the electronic device will be mainly described below, the display device and the electronic device may have configuration parts and functions that are not illustrated or described. The following description does not exclude configuration parts and functions that are not illustrated or described.
The display device 1 of
The pixel array unit 2 includes a plurality of pixels 8 arranged in each of a row direction and a column direction. Each of the pixels 8 includes a plurality of subpixels 8a. The plurality of subpixels 8a includes, for example, three subpixels 8a of red, blue, and green. The plurality of subpixels 8a may include subpixels 8a of colors other than red, blue, and green (for example, white). In the present specification, the subpixel 8a may be collectively referred to as the pixel 8.
Each of the subpixel 8a in the pixel 8 includes a display element and a pixel circuit as described later. The display element is, for example, an OLED. Note that the display element may be a liquid crystal element or a self-light-emitting element other than the OLED.
The pixel array unit 2 includes a plurality of scanning lines WSL arranged for each pixel group in the row direction and a plurality of signal lines SIG arranged for each pixel group in the column direction. The pixel 8 is provided near each of intersections of the scanning lines WSL and the signal lines SIG. In the present specification, the row direction may be referred to as a horizontal line direction, and the column direction may be referred to as a vertical line direction.
The scanning line drive unit 3 sequentially drives the plurality of scanning lines WSL. The signal line drive unit 4 drives the plurality of signal lines SIG in the horizontal line direction at the same timing in synchronization with the timing at which each of the scanning lines WSL drives each horizontal line. Driving the signal lines SIG means supplying a gradation signal corresponding to each of the signal lines SIG.
The video signal processing unit 5 performs predetermined signal processing on a video signal supplied from the outside (for example, a processor) to generate the gradation signal. The predetermined signal processing is, for example, processing such as gamma correction and overdrive correction.
The timing generation unit 6 supplies a timing control signal to the scanning line drive unit 3 and the signal line drive unit 4 on the basis of a synchronization signal supplied from the outside, and operates the scanning line drive unit 3 and the signal line drive unit 4 in synchronization.
The number of pixels in the pixel array unit 2 in
In the pixel circuit 11 of
The DS transistor Q3 and the Drv transistor Q1 are cascode-connected between a power supply voltage node VCCP and an anode of the OLED 12. The WS transistor Q2 is connected between the signal line SIG and a gate of the Drv transistor Q1. In
The AZ transistor Q4 is connected between the anode of the OLED 12 and a ground voltage node VSSP. An AZ signal is supplied to a gate of the AZ transistor Q4. In a case where the AZ transistor Q4 is a P-type MOS transistor, when the AZ signal is low, a source-drain current of the Drv transistor Q1 passes through the AZ transistor Q4 and flows to the ground voltage node VSSP. Therefore, while the AZ transistor Q4 is on, an increase in an anode voltage of the OLED 12 is suppressed, and the current does not flow through the OLED 12.
The first capacitor Cs is connected between the gate and the source of the Drv transistor Q1. Furthermore, the second capacitor Csub is connected between the source and the drain of the DS transistor Q3. That is, the first capacitor Cs and the second capacitor Csub are connected in series between the power supply voltage node VCCP and the gate of the Drv transistor Q1. The first capacitor Cs may be referred to as a pixel capacitance, and the second capacitor Csub may be referred to as an auxiliary capacitance.
The first capacitor Cs and the second capacitor Csub are, for example, metal-insulator-metal (MIM) capacitors. In this case, for example, at least one electrode of the capacitor is disposed in a wiring layer.
A cathode of the OLED 12 is fixed to a predetermined voltage (for example, a ground voltage).
Next, an operation of the pixel circuit 11 illustrated in
The signal line drive unit 4 generates a drive voltage of all the signal lines SIG each time the scanning line drive unit 3 drives one scanning line WSL. The plurality of scanning lines WSL is provided in one frame, and the plurality of pixels connected to one scanning line WSL is referred to as one horizontal line (1H).
Hereinafter, the operation of the pixel circuit of
Thereafter, at time t2, the DS transistor Q3 is turned off. As a result, a part of charges accumulated in the first capacitor Cs moves to the second capacitor Csub, and the charges are distributed. Specifically, charges corresponding to a threshold voltage of the Drv transistor Q1 are accumulated in the first capacitor Cs.
Thereafter, at time t3, the WS transistor Q2 is turned off. Thereafter, at time t4, a signal line voltage Vsig is supplied onto the signal line SIG. Thereafter, at time t5, the WS transistor Q2 is turned on, and the signal line voltage Vsig is supplied to the gate of the Drv transistor Q1. Since the correction corresponding to the threshold voltage of the Drv transistor Q1 is performed by the first capacitor Cs, a voltage subjected to offset correction and threshold correction with respect to the signal line voltage Vsig is applied between the gate and the source of the Drv transistor Q1.
As described above, the first capacitor Cs and the second capacitor Csub are used for the offset correction and the threshold correction, for example. By performing the threshold correction, it is possible to correct the variation in the threshold voltage of the Drv transistor Q1, and it is possible to suppress deterioration of the image quality of the display image. For example, the surface roughness can be corrected by the threshold correction. Furthermore, the larger the capacitances of the first capacitor Cs and the second capacitor Csub, the more appropriately the correction can be performed.
Next, a configuration of the first capacitor Cs and the second capacitor Csub, and a peripheral configuration thereof will be described.
The pixel circuit 11 illustrated in
The first capacitor Cs has two electrode portions and holds a first voltage related to the operation of the OLED 12. More specifically, the first capacitor Cs includes a first electrode portion E1 and a second electrode portion E2. The first electrode portion E1 and the second electrode portion E2 are disposed so as to sandwich an insulating layer therebetween.
The second capacitor Csub is disposed in the same layer as the first capacitor Cs. The second capacitor Csub includes two electrode portions and holds a second voltage related to the operation of the OLED 12. The second voltage is different from the first voltage, for example. That is, the first capacitor Cs and the second capacitor Csub have different functions. However, the second voltage may be the same as the first voltage. Each of the two electrode portions of the second capacitor Csub is disposed in the same layer as each of the two electrode portions of the first capacitor Cs. More specifically, the second capacitor Csub includes a third electrode portion E3 and a fourth electrode portion E4. The third electrode portion E3 and the fourth electrode portion E4 are disposed so as to sandwich an insulating layer therebetween.
The first electrode portion E1 (first electrode) is disposed, for example, in the layer L1. The second electrode portion E2 (second electrode) is disposed in the layer L11, for example. In the example illustrated in
The third electrode portion E3 (third electrode) is disposed in the layer L1 that is the same layer as the first electrode portion E1. The fourth electrode portion E4 (fourth electrode) is disposed in the layer L11 that is the same layer as the second electrode portion E2. In the example illustrated in
Furthermore, one electrode portion of the first capacitor Cs and one electrode portion of the second capacitor Csub are common electrode portions. The common electrode portions include one electrode portion of a certain capacitor, and are electrode portions electrically connected between the plurality of capacitors. Furthermore, the common electrode portions are disposed in the two layers, respectively, in which the two electrode portions of the capacitor are disposed. In the example illustrated in
Furthermore, as illustrated in
Furthermore, as illustrated in
Furthermore, as illustrated in
The metal layer ML is disposed in a layer different from the first capacitor Cs and the second capacitor Csub. The metal layer ML is disposed in the layer L2, for example. The metal layer ML is electrically connected to the common electrode portions, that is, the second electrode portion E2 and the third electrode portion E3. Therefore, the metal layer ML is also electrically connected to the source DRs.
Furthermore, the metal layer ML is disposed so as to overlap with at least one electrode portion of at least one capacitor when viewed from the lamination direction. Here, “overlapping” indicates that an outer edge of the metal layer ML is not necessarily located outside an outer edge of the electrode portion in plan view. More specifically, the metal layer ML is disposed so as to cover at least one electrode portion of at least one capacitor when viewed from the lamination direction. Here, “cover” indicates that the outer edge of the metal layer ML is located outside the outer edge of the electrode portion in plan view. In the following description, it is assumed that the metal layer ML covers the first electrode portion E1 in plan view. The metal layer ML is more preferably disposed so as to cover the first electrode portion E1. However, the metal layer ML may not necessarily be disposed so as to cover the first electrode portion E1.
In the example illustrated in
The via V is provided so as to extend in the lamination direction. A plurality of the vias V electrically connects the common electrode portions and the metal layer ML. The metal layer ML is disposed so as to electrically connect the respective common electrode portions via the plurality of vias V. More specifically, each of the vias V electrically connects the second electrode portion E2 and the third electrode portion E3 disposed in mutually different layers via the metal layer ML.
Furthermore, the via V includes a via V1 and a via V2.
The via V1 electrically connects the second electrode portion E2 and the metal layer ML. The via V2 electrically connects the third electrode portion E3 and the metal layer ML.
Next, electrostatic capacitances of the first capacitor Cs and the second capacitor Csub will be described.
The capacitance of the first capacitor Cs is usually determined by an area in which the first electrode portion E1 and the second electrode portion E2 overlap each other when viewed from the lamination direction. However, widening the overlapping area is limited by layout arrangement and area restrictions. Here, by utilizing a parasitic capacitance in the circuit, the electrostatic capacitance of the first capacitor Cs can be improved.
As described above, the first electrode portion E1 is larger than the second electrode portion E2, and the metal layer ML is larger than the first electrode portion E1. Therefore, as illustrated in
Furthermore, the signal line SIG is disposed in the layer L3 above the layers L1 and L2. In a case where the signal line SIG and the first electrode portion E1 overlap each other when viewed from the lamination direction, a parasitic capacitance occurs between the first electrode portion E1 and the signal line SIG. As described above, the first electrode portion E1 is electrically connected to the gate DRg. Therefore, the operation of the Drv transistor Q1 may be adversely affected by the parasitic capacitance, and noise may increase. However, as illustrated in
The electrostatic capacitance of the second capacitor Csub is usually determined by an area in which the third electrode portion E3 and the fourth electrode portion E4 overlap each other when viewed from the lamination direction. However, widening the overlapping area is limited by layout arrangement and area restrictions. Here, by utilizing a parasitic capacitance in the circuit, the effective electrostatic capacitance of the second capacitor Csub can be improved.
In the layer L3 above the layers L1 and L2, voltage supply wiring for supplying a predetermined voltage (power supply voltage VCCP) is disposed. When the metal layer ML overlaps the voltage supply wiring as viewed from the lamination direction, a parasitic capacitance Cp2 is generated between the power supply wiring and the metal layer ML as illustrated in
As described above, according to the first embodiment, the first capacitor Cs and the second capacitor Csub are disposed in the same layer. As a result, since the two capacitors can be formed at a time, the number of steps and cost can be reduced.
In the example illustrated in
On the other hand, in the first embodiment, as described above, the first capacitor Cs and the second capacitor Csub can be formed at a time, and the number of steps and the cost can be reduced.
Furthermore, in the first embodiment, the second electrode portion E2 and the third electrode portion E3 that are common electrode portions are disposed in two different layers. As a result, the electrostatic capacitances of the first capacitor Cs and the second capacitor Csub can be increased by the parasitic capacitances in the circuit. By increasing the electrostatic capacitance, it is possible to improve the resistance to luminance variation associated with leakage during light emission, and to improve image quality. Furthermore, by increasing the electrostatic capacitance, correction such as threshold correction can be made more advantageous, and for example, surface roughness and the like can be suppressed to improve image quality. Furthermore, the first electrode portion E1 electrically connected to the gate DRg can be shielded. As a result, the influence of noise due to the parasitic capacitance from the signal line SIG to the gate DRg can be suppressed, and image quality can be improved.
In the example illustrated in
On the other hand, in the first embodiment, the first electrode portion E1 electrically connected to the gate DRg is disposed in the lower layer L1. Furthermore, the common electrode portion (metal layer ML) is disposed so as to cover the first electrode portion E11 when viewed from the lamination direction. Therefore, the first electrode portion E1 can be shielded, and generation of the parasitic capacitance and noise can be suppressed. As a result, image quality can be improved. Furthermore, the parasitic capacitance in the circuit can improve the effective electrostatic capacitances of the first capacitor Cs and the second capacitor Csub. As a result, the threshold correction and the like can be more appropriately performed, and image quality can be improved.
Note that, in the first embodiment, the two capacitors, the first capacitor Cs and the second capacitor Csub, have been described. However, three or more capacitors may be provided. In this case, the plurality of capacitors is disposed in the same layer. Each of the plurality of capacitors holds a voltage (charge) related to the operation of the OLED 12. Furthermore, a plurality of sets of the first capacitor Cs and the second capacitor Csub may be provided. In this case, the layers disposed between the sets may be different.
Furthermore, in the first embodiment, the first capacitor Cs and the second capacitor Csub are electrically connected to the Drv transistor Q1 for the threshold correction of the Drv transistor Q1. The Drv transistor Q1 is a transistor that drives the OLED 12 on the basis of the signal voltage held in the first capacitor Cs. However, depending on the purpose of providing the capacitor, the present disclosure is not necessarily limited to the Drv transistor Q1. The first capacitor Cs and the second capacitor Csub may be electrically connected to another transistor related to the operation of the OLED 12, such as the WS transistor Q2, the DS transistor Q3, or the AZ transistor Q4, for example.
Furthermore, in the first embodiment, the common electrode portions of the two capacitors, the first capacitor Cs and the second capacitor Csub, are electrically connected to the source of the transistor (Drv transistor Q1). However, as will be described later with reference to a third embodiment, a terminal other than the source of the transistor may be electrically connected to the common electrode portions.
Furthermore, in the first embodiment, the first capacitor Cs and the second capacitor Csub are MIM capacitors. However, as will be described later with reference to the third embodiment and a fourth embodiment, another capacitor may be used.
Furthermore, the embodiment of the present disclosure is not limited to the first embodiment, and can be applied in a case where a plurality of capacitors including common electrodes is provided.
The pixel circuit 11 in
As in the modification example of the first embodiment, the conductivity types of the transistors may be different. Also in this case, effects equivalent to those of the first embodiment can be obtained.
In the pixel circuit 11b of
As in the second embodiment, the capacitor Coled may be provided. Also in this case, effects equivalent to those of the first embodiment can be obtained.
A capacitor C1 and a capacitor C2 are provided instead of the first capacitor Cs and the second capacitor Csub. Note that, although only one capacitor is illustrated in the circuit diagram illustrated in
The capacitor C1 and the capacitor C2 are connected between a gate DRg and a ground voltage node VSSP. The capacitor C1 and the capacitor C2 are connected in parallel to each other. Therefore, the capacitor C1 and the capacitor C2 include common electrodes. Furthermore, the common electrodes of the capacitor C1 and the capacitor C2 are electrically connected to a gate DRg of a Drv transistor Q1.
The capacitor C1 and the capacitor C2 are, for example, a MIM capacitor and a metal-oxide-metal (MOM) capacitor, respectively.
Next, configurations other than the capacitor will be described.
In
Next, a configuration of the capacitor C1 and the capacitor C2, and a peripheral configuration thereof will be described.
In the example illustrated in
As in the first embodiment, the first electrode portion E1 is larger than the second electrode portion E2, and a metal layer ML is larger than the first electrode portion E1. Therefore, as illustrated in
Furthermore, the second electrode portion E2, the third electrode portion E3, and the metal layer ML are electrically connected to the gate DRg. The first electrode portion E1 covered with the metal layer ML and different from the common electrode portion (second electrode portion E2) is electrically connected to the voltage supply wiring. In the example illustrated in
As in the third embodiment, the common electrode portions of the two capacitors C1 and C2 may be electrically connected to the gate DRg of the transistor (Drv transistor Q1). Also in this case, effects equivalent to those of the first embodiment can be obtained.
In the example illustrated in
Furthermore, a capacitor C1 and a capacitor C2 are, for example, an MOM capacitor and a MOS capacitor, respectively.
In the fourth embodiment, as in the third embodiment, common electrode portions of the two capacitors C1 and C2 are electrically connected to a gate DRg of a Drv transistor Q1. Therefore, the fourth embodiment can obtain effects equivalent to those of the third embodiment.
In the example illustrated in
Furthermore, the capacitor C1 and the capacitor C2 are, for example, an MIM capacitor and an MOM capacitor, respectively.
Furthermore, a signal relay line relay line is disposed between a signal line SIG and the gate DRg (WS transistor Q2) of the Drv transistor Q1. Furthermore, AZ transistors Q41, Q42, and Q43 and a capacitor Ca are provided. An AZ1 signal, an AZ2 signal, and an AZ3 signal are input to gates of the AZ transistors Q41, Q42, and Q43 that are P-type MOS transistors, respectively.
In the fifth embodiment, as in the third embodiment, common electrode portions of the two capacitors C1 and C2 are electrically connected to the gate DRg of the Drv transistor Q1. Therefore, the fifth embodiment can obtain effects equivalent to those of the third embodiment.
In the example illustrated in
In the sixth embodiment, as in the third embodiment, common electrode portions of the two capacitors C1 and C2 are electrically connected to the gate DRg of the Drv transistor Q1. Therefore, the sixth embodiment can obtain effects equivalent to those of the third embodiment.
The display device 1 according to the present disclosure can be mounted on various electronic devices.
The vehicle 100 of
The center display 101 is disposed on a dashboard 107 at a position facing a driver seat 108 and a passenger seat 109.
The safety-related information is information such as doze detection, looking-away detection, mischief detection of a child riding together, presence or absence of wearing of a seat belt, and detection of leaving of an occupant, and is, for example, information detected by a sensor superimposed on a back side of the center display 101. The operation-related information detects a gesture related to the operation of the occupant using the sensor. The sensed gestures may include an operation of various types of equipment in the vehicle 100. For example, operations of air conditioning equipment, a navigation device, an AV device, a lighting device, and the like are sensed. The life log includes a life log of all the occupants. For example, the life log includes an action record of each occupant in the conveyance. By acquiring and storing the life log, it is possible to check a state of the occupant at a time of an accident. The health-related information detects a body temperature of the occupant using a temperature sensor, and estimates the health state of the occupant on the basis of the detected body temperature. Alternatively, the face of the occupant may be imaged by using an image sensor, and the health condition of the occupant may be estimated from the imaged facial expression. Moreover, a conversation may be made with the occupant in automatic voice, and the health condition of the occupant may be estimated on the basis of an answer content of the occupant. The authentication/identification-related information includes a keyless entry function of performing face authentication using a sensor, an automatic adjustment function of a sheet height and position in face identification, and the like. The entertainment-related information includes a function of detecting operation information of the AV device by the occupant using the sensor, a function of recognizing the face of the occupant by the sensor and providing content suitable for the occupant by the AV device, and the like.
The console display 102 can be used to display the life log information, for example. The console display 102 is arranged near a shift lever 111 of a center console 110 between the driver seat 108 and the passenger seat 109. The console display 102 can also display information detected by various sensors. Furthermore, the console display 102 may display an image of a periphery of the vehicle captured by the image sensor, or may display an image of a distance to an obstacle in the periphery of the vehicle.
The head-up display 103 is virtually displayed behind a windshield 112 in front of the driver seat 108. The head-up display 103 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication/identification-related information, or entertainment-related information. Since the head-up display 103 is virtually arranged in front of the driver seat 108 in many cases, the head-up display 103 is suitable for displaying information directly related to an operation of the vehicle 100 such as a speed of the vehicle 100 and a remaining amount of fuel (a battery).
The digital rear mirror 104 can not only display the rear of the vehicle 100 but also display the state of the occupant in the rear seat, and thus can be used to display the life log information, for example, by disposing the sensor to be superimposed on a back surface side of the digital rear mirror 104.
The steering wheel display 105 is arranged near a center of a steering wheel 113 of the vehicle 100. The steering wheel display 105 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication/identification-related information, or entertainment-related information. In particular, since the steering wheel display 105 is close to the driver's hand, the steering wheel display 105 is suitable for displaying the life log information such as a body temperature of the driver, or for displaying information regarding an operation of the AV device, air conditioning equipment, or the like.
The rear entertainment display 106 is attached to a back side of the driver seat 108 and the passenger seat 109, and is for viewing by an occupant in the rear seat. The rear entertainment display 106 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication/identification-related information, or entertainment-related information. In particular, since the rear entertainment display 106 is in front of the occupant in the rear seat, information related to the occupant in the rear seat is displayed. For example, information regarding the operation of the AV device or the air conditioning facility may be displayed, or a result of measuring the body temperature or the like of the occupant in the back seat by the temperature sensor may be displayed.
The display device 1 according to the present disclosure can be applied to the center display 101, the console display 102, the head-up display 103, the digital rear mirror 104, the steering wheel display 105, and the rear entertainment display 106.
The display device 1 according to the present disclosure is applicable not only to various displays used in vehicles but also to displays mounted on various electronic devices 50.
In the camera of
By applying the display device 1 according to the present disclosure to the monitor screen 126, the electronic viewfinder 124, the sub screen, and the like used for the camera, it is possible to reduce the cost and improve the display quality.
The display device 1 according to the present disclosure is also applicable to a head mounted display (Hereinafter, referred to as an HMD.). The HMD can be used for virtual reality (VR), augmented reality (AR), mixed reality (MR), substitutional reality (SR), and the like.
Furthermore, a camera may be provided in the HMD 130 to capture an image around the wearer, and an image obtained by combining the captured image of the camera and an image generated by a computer may be displayed on the display device 132. For example, arranging a camera to overlap with a back surface side of the display device 132 visually recognized by the wearer of the HMD 130, capturing an image of a periphery of an eye of the wearer with the camera, and displaying the captured image on another display provided on an outer surface of the HMD 130, a person around the wearer can grasp expression of the face and a movement of the eyes of the wearer in real time.
Note that various types of the HMD 130 are conceivable. For example, as illustrated in
The display device 1 according to the present disclosure is also applicable to a television device (Hereinafter, TV).
As described above, according to the display device 1 of the present disclosure, the TV 330 with low cost and excellent display quality can be realized.
The display device 1 according to the present disclosure is also applicable to a smartphone and a mobile phone.
Note that the present technology can have the following configurations.
(1) A display device including:
(2) The display device according to (1), further including a metal layer that is disposed in a layer different from the first capacitor and the second capacitor so as to overlap with the first electrode and the second electrode when viewed from a lamination direction, and is electrically connected to the second electrode and the third electrode.
(3) The display device according to (2), in which the metal layer is disposed so as to cover the first electrode and the second electrode when viewed from the lamination direction.
(4) The display device according to (2) or (3), in which the metal layer is disposed so as to overlap with the first electrode disposed so as to cover the second electrode when viewed from the lamination direction.
(5) The display device according to (4), in which
(6) The display device according to (4), in which
(7) The display device according to any one of (2) to (6), in which the metal layer is disposed so as to overlap with a voltage supply wiring that supplies a predetermined voltage when viewed from the lamination direction.
(8) The display device according to (7), in which the fourth electrode is electrically connected to the voltage supply wiring.
(9) The display device according to any one of (2) to (8), in which the metal layer is disposed so as to overlap with the first electrode electrically connected to a gate of the drive transistor when viewed from the lamination direction.
(10) The display device according to (9), in which
(11) The display device according to any one of (2) to (10), further including a plurality of columnar electrode portions provided so as to extend in the lamination direction and electrically connecting each of the second electrode and the third electrode to the metal layer,
(12) The display device according to (1) to (11), in which
(13) The display device according to any one of (1) to (12), in which each of the first capacitor and the second capacitor includes a metal-insulator-metal (MIM) capacitor, a metal-oxide-metal (MOM) capacitor, or a metal-oxide-semiconductor (MOS) capacitor.
(14) An electronic device including:
Aspects of the present disclosure are not limited to the above-described individual embodiments, but include various modifications that can be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. That is, various additions, modifications, and partial deletions are possible without departing from the conceptual idea and spirit of the present disclosure derived from the matters defined in the claims and equivalents thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2021-074288 | Apr 2021 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2022/015941 | 3/20/2022 | WO |
