Patent Application
20240242678
The present application is based on, and claims priority from JP Application Serial Number 2023-003591, filed Jan. 13, 2023, the disclosure of which is hereby incorporated by reference herein in its entirety.
The present disclosure relates to a display device and an electronic device.
Display devices such as liquid crystal display devices and organic electroluminescent display devices are known. An example of such a device is an organic EL display device described in JP-A-2016-75868.
In the organic EL display device of JP-A-2016-75868, one rectangular pixel is configured by combining a plurality of sub-pixels, and the pixels are arranged in a matrix. Each sub-pixel is provided to correspond to an intersection of a data line extending in a column direction and a scanning line extending in a row direction. In addition, an anode electrode of a light emitting element, a switching transistor, and a drive transistor are provided within a region of each sub-pixel.
In the display device of JP-A-2016-75868, when the number of sub-pixels is increased to achieve higher resolution, the number of sub-pixels corresponding to one scanning line increases. For this reason, one horizontal scanning period is reduced. As a result, there is a problem of deterioration in display quality. Further, as progress to a higher driving frame rate is made, the problem becomes more significant.
In order to solve the above problems, a display device according to a preferred aspect of the present disclosure includes a scanning line extending in a first direction, a first data line and a second data line that extend in a second direction intersecting the first direction and that are arranged in the first direction, a first transistor circuit, a second transistor circuit, a first light emitting element including a first pixel electrode, and a second light emitting element including a second pixel electrode, wherein the first transistor circuit includes a first drive transistor configured to supply the first pixel electrode with a first drive current based on a potential corresponding to a first video signal from the first data line, and a first selection transistor configured to electrically couple the first data line to the first drive transistor, the second transistor circuit includes a second drive transistor configured to supply the second pixel electrode with a second drive current based on a potential corresponding to a second video signal from the second data line, and a second selection transistor configured to electrically couple the second data line to the second drive transistor, the first pixel electrode and the second pixel electrode are arranged in the second direction, the first transistor circuit and the second transistor circuit are arranged in the first direction, and a gate included in the first selection transistor and a gate included in the second selection transistor are electrically coupled to the scanning line.
Preferred embodiments according to the present disclosure will be described below with reference to the accompanying drawings. In addition, in the drawings, dimensions and scales of each part are appropriately made different from actual ones, and some parts are shown schematically to make them easier to understand. Also, the scope of the present disclosure is not limited to these forms unless the present disclosure is specifically described as being limited in the following description.
The display device 1 includes a display panel 10 that displays images and is housed in a frame-shaped case 71 that opens at the display panel 10. One end of an FPC board 72 is coupled to the display device 1. FPC is an abbreviation for Flexible Printed Circuit. A plurality of terminals 73 for coupling a host device (not shown) are provided to the other end of the FPC board 72. When the plurality of terminals 73 are coupled to the host device, various signals are supplied to the display device 1 from the host device via the FPC board 72.
As shown in
The display panel 10 is provided with m scanning lines 11 extending in the X direction and n data lines 12 extending in the Y direction. A plurality of display pixels P0 are provided to correspond to intersections of a plurality of scanning lines 11 and a plurality of data lines 12. Also, for example, a pixel P representing one dot of a color image is configured for every three display pixels P0 arranged in the X direction. In this embodiment, an arrangement of pixels P is a so-called RGB stripe arrangement. In addition, each display pixel P0 is provided with a pixel electrode 151 included in a light emitting element 15, which will be described later.
The control circuit 130 controls image display. Digital video data Video output from a host device (not shown) is supplied to the control circuit 130 shown in
The control circuit 130 generates a control signal Ctr1 based on the synchronization signal Sync and supplies the control signal Ctr1 to the scanning line drive circuit 110, and generates a control signal Ctr2 based on the synchronization signal Sync and supplies the control signal Ctr2 to the data line drive circuit 120. Each of the control signals Ctr1 and Ctr2 includes a plurality of signals such as a pulse signal, a clock signal, and an enable signal.
Further, the control circuit 130 generates video data Vid based on the video data Video and supplies the video data Vid to the data line drive circuit 120. Brightness characteristics may not match between a gradation level indicated by the video data Vid and the light emitting element 15, which will be described later. Thus, in order to cause the light emitting element 15 to emit light at a brightness corresponding to the gradation level indicated by the video data Video, the control circuit 130 generates the video data Vid obtained by changing the 8 bits of the video data Video to 10 bits, for example.
In addition, the control circuit 130 is supplied with electric power from a power supply circuit (not shown) and supplies a power supply potential to the scanning line drive circuit 110, the data line drive circuit 120, and a plurality of transistor circuits 20, which will be described later, included in the display panel 10.
The scanning line drive circuit 110 generates a scanning signal Gwr based on the control signal Ctr1. The scanning signal Gwr is a signal for sequentially selecting and scanning m rows of the scanning lines 11 every predetermined number of rows in each frame period V. The scanning line drive circuit 110 sequentially and exclusively selects one or more scanning lines 11 from the m rows of the scanning lines 11 for each horizontal scanning period H included in each frame period V, and selects a display pixel P0 to which a video signal Vd is written from among the plurality of display pixels P0. Further, in
Also, the above-described frame period V indicates a period required for the display device 1 to display one cut of images. A length of the frame period V is, for example, 1/60 second when a driving frame rate is 60 Hz. One frame period V includes the horizontal scanning period H and a light emission period corresponding to each row. The light emission period is a period during which the light emitting element 15 emits light. One horizontal scanning period H is a period required for horizontal scanning of one row. One horizontal scanning period H includes a writing period in which the video signal Vd is written to the display pixel P0. Further, the number of scanning lines 11 selected in one horizontal scanning period H is not limited to one row and may be two or more rows.
The data line drive circuit 120 supplies video signals Vd to the transistor circuits 20, which will be described later, corresponding to the display pixels P0 provided in the row selected by the scanning line drive circuit 110. Also, in
Each of the first pixel P1 and the second pixel P2 has three display pixels P0. Specifically, the first pixel P1 has a first display pixel Pa, a third display pixel Pc, and a fifth display pixel Pe. The first display pixel Pa, the third display pixel Pc, and the fifth display pixel Pe are arranged in the X direction. Also, the second pixel P2 has a second display pixel Pb, a fourth display pixel Pd, and a sixth display pixel Pf. The second display pixel Pb, the fourth display pixel Pd, and the sixth display pixel Pf are arranged in the X direction. The first display pixel Pa and the second display pixel Pb emit light in a red wavelength band, for example. The third display pixel Pc and the fourth display pixel Pd emit light in a green wavelength band, for example. The fifth display pixel Pe and the sixth display pixel Pf emit light in a blue wavelength band, for example.
The pixel electrode 151 is provided in each display pixel P0. Similarly to the plurality of display pixels P0 being disposed in a matrix, a plurality of pixel electrodes 151 are disposed in a matrix. Also, although not shown, each of the display pixels P0 is provided with a light emitting region having substantially the same planar area and substantially the same planar shape as the pixel electrodes 151. Light is emitted from the light emitting region.
The first display pixel Pa is provided with a first pixel electrode 151a. The third display pixel Pc is provided with a third pixel electrode 151c. The fifth display pixel Pe is provided with a fifth pixel electrode 151e. In addition, the second display pixel Pb is provided with a second pixel electrode 151b. The fourth display pixel Pd is provided with a fourth pixel electrode 151d. The fifth display pixel Pe is provided with a fifth pixel electrode 151e. The sixth display pixel Pf is provided with a sixth pixel electrode 151f.
The third pixel electrode 151c is provided in the X direction with respect to the first pixel electrode 151a. The fifth pixel electrode 151e is provided in the X direction with respect to the third pixel electrode 151c. In addition, the second pixel electrode 151b is provided in the Y direction with respect to the first pixel electrode 151a. The fourth pixel electrode 151d is provided in the Y direction with respect to the third pixel electrode 151c and is provided in the X direction with respect to the second pixel electrode 151b. The sixth pixel electrode 151f is provided in the Y direction with respect to the fifth pixel electrode 151e and is provided in the X direction with respect to the fourth pixel electrode 151d.
The first transistor circuit 20a corresponds to the first display pixel Pa. The second transistor circuit 20b corresponds to the second display pixel Pb. The third transistor circuit 20c corresponds to the third display pixel Pc. The fourth transistor circuit 20d corresponds to the fourth display pixel Pd. The fifth transistor circuit 20e corresponds to the fifth display pixel Pe. The sixth transistor circuit 20f corresponds to the sixth display pixel Pf.
The first transistor circuit 20a, the second transistor circuit 20b, the third transistor circuit 20c, the fourth transistor circuit 20d, the fifth transistor circuit 20e, and the sixth transistor circuit 20f are arranged in order in the X direction.
Although not shown in detail, the first transistor circuit 20a and the second transistor circuit 20b overlap the first display pixel Pa and the second display pixel Pb in a plan view. With such an arrangement, the problem of an electrical coupling path between the first transistor circuit 20a and the first pixel electrode 151a becoming excessively long and excessively complicated is inhibited. Also, the same applies to the second transistor circuit 20b. In addition, the plan view indicates viewing in a direction orthogonal to both the X direction and the Y direction.
Similarly, although not shown in detail, the third transistor circuit 20c and the fourth transistor circuit 20d overlap the third display pixel Pc and the fourth display pixel Pd in a plan view. With such an arrangement, the problem of an electrical coupling path between the third transistor circuit 20c and the third pixel electrode 151c becoming excessively long and excessively complicated is inhibited. Also, the same applies to the fourth transistor circuit 20d. In addition, the fifth transistor circuit 20e and the sixth transistor circuit 20f overlap the fifth display pixel Pe and the sixth display pixel Pf in a plan view. With such an arrangement, the problem of an electrical coupling path between the fifth transistor circuit 20e and the fifth pixel electrode 151e becoming excessively long and excessively complicated is inhibited. Also, the same applies to the sixth transistor circuit 20f.
The first light emitting element 15a includes the first pixel electrode 151a, a common electrode 152, and a light emitting layer 153. Also, the common electrode 152 is common to first to sixth light emitting elements 15a to 15f. The light emitting layer 153 is common to the first to sixth light emitting elements 15a to 15f, but may be provided individually.
The first light emitting element 15a is disposed on a path that couples a first constant potential wiring 13p and a second constant potential wiring 14p. A higher potential Vel is supplied to the first constant potential wiring 13p from a power supply circuit (not shown). A lower potential Vct is supplied to the second constant potential wiring 14p from the power supply circuit. Also, the first light emitting element 15a is, for example, an OLED. The light emitting layer 153 includes a light emitting material and is interposed between the first pixel electrode 151a and the common electrode 152. The first pixel electrode 151a functions as an anode electrode, and the common electrode 152 functions as a cathode electrode. In such a first light emitting element 15a, holes supplied from the first pixel electrode 151a and electrons supplied from the common electrode 152 are recombined in the light emitting layer 153. Due to the recombination, the light emitting layer 153 emits light.
The first drive transistor 16a supplies the first pixel electrode 151a with a first drive current Ida based on a potential corresponding to a first video signal Vda supplied from a first data line 12a of the n data lines 12. The first drive transistor 16a is disposed in series with the first light emitting element 15a. One of a source and a drain of the first drive transistor 16a is electrically coupled to the first constant potential wiring 13p, and the other is electrically coupled to the first pixel electrode 151a.
The first selection transistor 17a electrically couples the first data line 12a to the first drive transistor 16a. Specifically, the first selection transistor 17a functions as a switch that controls conduction and non-conduction between the first data line 12a and a gate of the first drive transistor 16a. One of a source and a drain of the first selection transistor 17a is electrically coupled to the first data line 12a, and the other is electrically coupled to the gate of the first drive transistor 16a. A gate of the first selection transistor 17a is electrically coupled to one arbitrary scanning line 11p among the m scanning lines 11.
In the following, the second to sixth transistor circuit 20b to 20f will be described, but the description of items similar to those of the first transistor circuit 20a will be appropriately omitted.
The second transistor circuit 20b includes a second light emitting element 15b, a second drive transistor 16b, a second selection transistor 17b, and a second capacitive element 18b. The second light emitting element 15b includes the second pixel electrode 151b, the common electrode 152, and the light emitting layer 153. The second drive transistor 16b supplies the second pixel electrode 151b with a second drive current Idb based on a potential corresponding to a second video signal Vdb supplied from a second data line 12b. The second selection transistor 17b electrically couples the second data line 12b among the n data lines 12 to the second drive transistor 16b. A gate of the second selection transistor 17b is electrically coupled to the scanning line 11p.
The third transistor circuit 20c includes a third light emitting element 15c, a third drive transistor 16c, a third selection transistor 17c, and a third capacitive element 18c. The third light emitting element 15c includes the third pixel electrode 151c, the common electrode 152, and the light emitting layer 153. The third drive transistor 16c supplies the third pixel electrode 151c with a third drive current Idc based on a potential corresponding to a third video signal Vdc supplied from a third data line 12c. The third selection transistor 17c electrically couples the third data line 12c among the n data lines 12 to the third drive transistor 16c. A gate of the third selection transistor 17c is electrically coupled to the scanning line 11p.
The fourth transistor circuit 20d includes a fourth light emitting element 15d, a fourth drive transistor 16d, a fourth selection transistor 17d, and a fourth capacitive element 18d. The fourth light emitting element 15d includes the fourth pixel electrode 151d, the common electrode 152, and the light emitting layer 153. The fourth drive transistor 16d supplies the fourth pixel electrode 151d with a fourth drive current Idd based on a potential corresponding to a fourth video signal Vdd supplied from a fourth data line 12d. The fourth selection transistor 17d electrically couples the fourth data line 12d among the n data lines 12 to the fourth drive transistor 16d. A gate of the fourth selection transistor 17d is electrically coupled to the scanning line 11p.
The fifth transistor circuit 20e includes a fifth light emitting element 15e, a fifth drive transistor 16e, a fifth selection transistor 17e, and a fifth capacitive element 18e. The fifth light emitting element 15e includes the fifth pixel electrode 151e, the common electrode 152, and the light emitting layer 153. The fifth drive transistor 16e supplies the fifth pixel electrode 151e with a fifth drive current Ide based on a potential corresponding to a fifth video signal Vde supplied from a fifth data line 12e. The fifth selection transistor 17e electrically couples the fifth data line 12e among the n data lines 12 to the fifth drive transistor 16e. A gate of the fifth selection transistor 17e is electrically coupled to the scanning line 11p.
The sixth transistor circuit 20f includes a sixth light emitting element 15f, a sixth drive transistor 16f, a sixth selection transistor 17f, and a sixth capacitive element 18f. The sixth light emitting element 15f includes the sixth pixel electrode 151f, the common electrode 152, and the light emitting layer 153. The sixth drive transistor 16f supplies the sixth pixel electrode 151f with a sixth drive current Idf based on a potential corresponding to a sixth video signal Vdf supplied from a sixth data line 12f. The sixth selection transistor 17f electrically couples the sixth data line 12f among the n data lines 12 to the sixth drive transistor 16f. A gate of the sixth selection transistor 17f is electrically coupled to the scanning line 11p.
Also, the configuration of the transistor circuits 20 shown in
As described above, the first pixel electrode 151a and the second pixel electrode 151b shown in
In known art, the transistor circuits 20 are disposed in a matrix, similarly to the arrangement of the pixel electrodes 151. For this reason, in known art, when the first pixel electrode 151a and the second pixel electrode 151b are arranged in the Y direction, the first transistor circuit 20a and the second transistor circuit 20b are arranged in the Y direction. Thus, the first transistor circuit 20a and the second transistor circuit 20b are electrically coupled to different scanning lines 11. Accordingly, in known art, two scanning lines 11 are required to control ON/OFF of the first selection transistor 17a and the second selection transistor 17b.
On the other hand, in this embodiment, the first pixel electrode 151a and the second pixel electrode 151b are arranged in the Y direction, whereas the first transistor circuit 20a and the second transistor circuit 20b are arranged in the X direction. For this reason, the gate of the first selection transistor 17a and the gate of the second selection transistor 17b are electrically coupled to the same scanning line 11p. Accordingly, the scanning line 11p for controlling ON/OFF of the first selection transistor 17b and the second selection transistor 17b is common. Thus, in known art, two scanning lines 11 are required, but in this embodiment, only one scanning line 11p is required. That is, the number of scanning lines 11 can be reduced to ½ as compared with the known configuration. For this reason, it is possible to make one horizontal scanning period H twice longer than one horizontal scanning period H in known art. Thus, deterioration in display quality due to shortening of one horizontal scanning period H can be inhibited. In particular, even when progress to a higher driving frame rate is made, one horizontal scanning period H sufficient for maintaining the display quality can be secured.
Also, as shown in
Also, as shown in
According to this embodiment, while the six display pixels P0 are arranged in two rows and three columns, the six transistor circuits 20 are arranged in one row and six columns. Accordingly, the number of transistor circuits 20 arranged in the column direction can be halved as compared to the number of pixel electrodes 151 arranged in the column direction. That is, the number of transistor circuits 20 arranged can be halved as compared to the number of display pixels P0 arranged. Accordingly, as described above, one horizontal scanning period H can be secured to be twice longer than one horizontal scanning period H in known art. Thus, deterioration in display quality can be inhibited.
Also, the first pixel electrode 151a, the third pixel electrode 151c, and the fifth pixel electrode 151e form the first pixel P1 that forms one dot in color display. The second pixel electrode 151b, the fourth pixel electrode 151d, and the sixth pixel electrode 151f form the second pixel P2 that forms another dot in the color display. Thus, the transistor circuits 20 of the two pixels P arranged in the column direction are arranged in the row direction. In addition, the gates of the transistor circuits 20 included in the two pixels P arranged in the column direction are electrically coupled to the one scanning line 11p. According to such a configuration, regardless of the arrangement direction of the pixels P, as described above, the number of transistor circuits 20 arranged in the column direction can be halved as compared to the number of pixel electrodes 151 arranged in the column direction. Accordingly, as described above, one horizontal scanning period H can be secured to be twice longer than one horizontal scanning period H in known art. Thus, deterioration in display quality can be inhibited.
A second Embodiment will be described. Also, in each of the following examples, the reference numerals used in the description of the first embodiment will be used for elements whose functions are similar to those in the first embodiment, and each detailed description thereof will be appropriately omitted.
This embodiment is different from the first embodiment in the combination of the display pixels P0 included in one pixel P. The arrangement of the display pixels P0 in this embodiment is a so-called Bayer array.
As shown in
The first pixel electrode 151a is provided in the first display pixel PaA. The second pixel electrode 151b is provided in the second display pixel PbA. The third pixel electrode 151c is provided in the third display pixel PcA. The fourth pixel electrode 151d is provided in the fourth display pixel PdA.
The second pixel electrode 151b is provided in the Y direction with respect to the first pixel electrode 151a. The third display pixel PcA is provided in the X direction with respect to the first pixel electrode 151a. The fourth pixel electrode 151d is provided in the Y direction with respect to the third display pixel PcA and is provided in the X direction with respect to the second pixel electrode 151b.
In
The first transistor circuit 20a, the second transistor circuit 20b, the third transistor circuit 20c, and the fourth transistor circuit 20d are arranged in order in the X direction.
Although not shown in detail, the first transistor circuit 20a and the second transistor circuit 20b overlap the first display pixel PaA and the second display pixel PbA in a plan view. With such an arrangement, the problem of an electrical coupling path between the first transistor circuit 20a and the first pixel electrode 151a becoming excessively long and excessively complicated is inhibited. Also, the same applies to the second transistor circuit 20b. In addition, although not shown in detail, the third transistor circuit 20c and the fourth transistor circuit 20d overlap the third display pixel PcA and the fourth display pixel PdA in a plan view. With such an arrangement, the problem of an electrical coupling path between the third transistor circuit 20c and the third pixel electrode 151c becoming excessively long and excessively complicated is inhibited. Also, the same applies to the fourth transistor circuit 20d.
In this embodiment, the four display pixels P0 are arranged in two rows and two columns, whereas the four transistor circuits 20 are arranged in one row and four columns. Further, the gate of the first selection transistor 17a, the gate of the second selection transistor 17b, the gate of the third selection transistor 17c, and the gate of the fourth selection transistor 17d are electrically coupled to the same scanning line 11p.
According to this embodiment, similarly to the first embodiment, the number of transistor circuits 20 arranged in the column direction can be halved as compared to the number of pixel electrodes 151 arranged in the column direction. That is, the number of transistor circuits 20 arranged can be halved as compared to the number of display pixels P0 arranged. Specifically, the number of transistor circuits 20 arranged in the row direction is twice larger than the number of display pixels P0 arranged. According to the configuration of this embodiment, one horizontal scanning period H can be secured to be twice longer than one horizontal scanning period H in known art. Thus, deterioration in display quality due to shortening of one horizontal scanning period H can be inhibited.
In addition, in this embodiment, the first pixel electrode 151a, the second pixel electrode 151b, the third pixel electrode 151c, and the fourth pixel electrode 151d form one pixel P that forms one dot in color display. Thus, the first to fourth transistor circuit 20a to 20d corresponding to one pixel P are arranged in one row, and each gate of the first to fourth transistor circuit 20a to 20d is electrically coupled to the scanning line 11p. Even when four display pixels P0 of one pixel P are arranged in two rows and two columns as in this embodiment, the number of transistor circuits 20 arranged in the column direction can be halved as compared to the number of pixel electrodes 151 arranged in the column direction. Accordingly, as described above, one horizontal scanning period H can be secured to be twice longer than one horizontal scanning period H in known art. Thus, deterioration in display quality can be inhibited.
A third embodiment will be described. Also, in each of the following examples, the reference numerals used in the description of the first embodiment will be used for elements whose functions are similar to those in the first embodiment, and each detailed description thereof will be appropriately omitted.
This embodiment is different from the first embodiment in the combination of the display pixels P0 included in one pixel P. In this embodiment, for example, monochrome display is performed.
The first pixel electrode 151a is provided in the first display pixel PaB. The second pixel electrode 151b is provided in the second display pixel PbB. The second pixel electrode 151b is provided in the Y direction with respect to the first pixel electrode 151a.
The first transistor circuit 20a and the second transistor circuit 20b are arranged in order in the X direction. Although not shown in detail, the first transistor circuit 20a and the second transistor circuit 20b overlap the first display pixel PaB and the second display pixel PbB in a plan view. With such an arrangement, the problem of an electrical coupling path between the first transistor circuit 20a and the first pixel electrode 151a becoming excessively long and excessively complicated is inhibited. Similarly, the problem of an electrical coupling path between the second transistor circuit 20b and the second pixel electrode 151b becoming excessively long and excessively complicated is inhibited.
In this embodiment, similarly to the first embodiment, the arrangement direction of the first transistor circuit 20a and the second transistor circuit 20b intersects the arrangement direction of the first pixel electrode 151a and the second pixel electrode 151b. Further, in this embodiment, the two display pixels P0 are arranged in two rows and one column, whereas the two transistor circuits 20 are arranged in one row and two columns. In addition, the gate included in the first selection transistor 17a and the gate included in the second selection transistor 17b are electrically coupled to the same scanning line 11p.
According to this embodiment, similarly to the first embodiment, the number of transistor circuits 20 arranged in the column direction can be halved as compared to the number of pixel electrodes 151 arranged in the column direction. That is, the number of transistor circuits 20 arranged can be halved as compared to the number of display pixels P0 arranged. According to the configuration of this embodiment, one horizontal scanning period H can be secured to be twice longer than one horizontal scanning period H in known art. Thus, deterioration in display quality due to shortening of one horizontal scanning period H can be inhibited.
In addition, in this embodiment, the first pixel electrode 151a and the second pixel electrode 151b form one pixel P that forms one dot in color display. Even when two display pixels P0 included in one pixel P are arranged in two rows and one column, gates of the two transistor circuits 20 corresponding to the two display pixels P0 are electrically coupled to one scanning line 11p. According to such a configuration, as described above, the number arranged in the row direction can be halved. Accordingly, as described above, one horizontal scanning period H can be secured to be twice longer than one horizontal scanning period H in known art. Thus, deterioration in display quality can be inhibited.
The embodiments exemplified above may be modified in various ways. Specific modified aspects that may be applied to the above-described embodiments will be exemplified below. Two or more aspects arbitrarily selected from the following examples may be combined as appropriate within a range in which they do not contradict each other.
The arrangements of the display pixels P0 in the above-described embodiments are examples, and other arrangements may be used. For example, a so-called PenTile arrangement or the like may be used.
In the above-described embodiment, the two transistor circuits 20 overlap the two display pixels P0 in a plan view. However, three or more transistor circuits 20 may overlap three or more display pixels P0 in a plan view. In this case, three or more transistor circuits 20 corresponding to three or more display pixels P0 arranged in the Y direction are arranged in the X direction. In addition, gates of the selection transistors 17 included in the three transistor circuits 20 are electrically coupled to the same scanning line 11p. According to this configuration, the number of transistor circuits 20 arranged can be reduced to ⅓ or less of the number of display pixels P0 arranged. According to such a configuration, one horizontal scanning period H can be secured to be three times or more of one horizontal scanning period H in known art.
However, a configuration in which two transistor circuits 20 overlap two display pixels P0 in a plan view and gates of selection transistors 17 included in the two transistor circuits 20 corresponding to the two display pixels P0 are electrically coupled to the same scanning line 11p is optimal. The number of wirings of the data lines 12 does not become excessively dense, and deterioration in display quality due to shortening of one horizontal scanning period H can be inhibited.
In the above-described embodiments, the light emitting element 15 is an OLED. However, for example, the light emitting element 15 may be an LED, a mini LED, a micro LED, or the like. LED is an abbreviation for Light emitting Diode.
The display device 1 of each of the above-described embodiments or modified examples can be applied to various electronic devices. The display device 1 according to the above-described embodiments is particularly suitable for electronic devices that are required to display high-definition images of 2K2K or higher and are required to be compact.
As shown in
Image light LL formed by the display device 1L is radiated to the projection optical system 301L. The projection optical system 301L includes an optical lens 302L and a half mirror 303L. The image light LL is radiated toward the half mirror 303L via the optical lens 302L. Some of the image light LL is reflected by the half mirror 303L and is projected to a pupil EY of a wearer of the head-mounted display 300. Also, some of the image light LL is transmitted through the half mirror 303L. Similarly, image light LR formed by the display device 1R is radiated to the projection optical system 301R. The projection optical system 301R includes an optical lens 302R and a half mirror 303R. The image light LR is radiated toward the half mirror 303L via the optical lens 302R. Some of the image light LR is reflected by the half mirror 303R and is projected to a pupil EY of the wearer of the head-mounted display 300. Also, some of the image light LR is transmitted through the half mirror 303R.
The wearer of the head-mounted display 300 can visually recognize an image formed by the image light LL and the image light LR while visually recognizing an external world image.
The head-mounted display 300 includes the above-described display devices 1 and the control unit 350. According to the display devices 1, deterioration in display quality can be inhibited. Accordingly, the head-mounted display 300 includes the display devices 1, and thus deterioration in display quality of the head-mounted display 300 can be inhibited.
Also, examples of the electronic device to which the above-described display device is applied include, in addition to the head-mounted display 300, an electronic device disposed close to the eyes, such as a digital scope, digital binoculars, a digital still camera, and a video camera. Further, it can be applied as a display unit provided in an electronic device such as a displayer or the like of a mobile phone, a smartphone, a smart watch, a personal digital assistant (PDA), a car navigation device, and an in-vehicle instrument panel. In addition, the display device 1 is applicable to a light bulb of a projection type projector.
Although the present disclosure has been described above based on the illustrated embodiments and modified examples, the present disclosure is not limited thereto. In addition, the configuration of each part of the present disclosure may be replaced with any configuration that exhibits the same function as in the embodiments described above, or any configuration can be added.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-003591 | Jan 2023 | JP | national |
