Patent Grant
12027528
The present invention relates to an object, a method, or a manufacturing method. In addition, the present invention relates to a process, a machine, manufacture, or a composition of matter. One embodiment of the present invention particularly relates to a semiconductor device, a light-emitting device, a display device, an electronic device, a lighting device, a driving method thereof, or a manufacturing method thereof. In particular, one embodiment of the present invention relates to a display device (display panel). Another embodiment of the present invention relates to an electronic device, a light-emitting device, or a lighting device which includes a display device, or a manufacturing method thereof.
In this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A transistor, a semiconductor circuit, an arithmetic device, a memory device, and the like are each one embodiment of the semiconductor device. A light-emitting device, a display device, an electronic device, a lighting device, and an electronic device may each include a semiconductor device.
A display device mounted on a head-mounted display or the like is required to have an extremely high resolution. For example, Patent Document 1 discloses an electroluminescent (EL) display device in which a transistor included in a pixel is formed on a silicon on insulator (SOI) substrate in order to increase the resolution of a display portion.
The leakage current in an off state (off-state current) of the transistor formed on the SOI substrate is several picoamperes (pico: 1×10−12); therefore, when the transistor is used for a pixel, it is difficult to reduce the frame frequency.
Considering the signal/noise (S/N) ratio or variation in electrical characteristics of the transistor, several volts of signal voltage (video voltage) needs to be supplied from a source line to the pixel. Therefore, the transistor to which the video voltage is applied is required to have a high withstand voltage. To obtain a transistor with a high withstand voltage, the channel length (L) of the transistor needs to be increased to approximately 1 μm, which has greatly restricted the circuit layout.
In the case where the resolution of the display portion is increased, a current flowing into a display element decreases with a decrease in area of the display element in one pixel. However, the transistor formed on the SOI substrate has such high field-effect mobility that its current supply capability is excessively high, leading to difficulty in driving the display element with a proper amount of current. As an effective countermeasure against this problem, the channel length (L) of the transistor may be increased to approximately 1 μm, which, however, has greatly restricted the circuit layout as described above.
An object of one embodiment of the present invention is to provide a display device in which the resolution of a display portion can be increased. Another object is to provide a display device whose bezel can be narrowed. Another object is to provide a display device which can have an uncomplicated circuit design. Another object is to provide a low-power display device. Another object is to provide a novel display device. Another object is to provide an electronic device including the display device (display panel). Another object is to provide a novel electronic device.
Note that the description of these objects does not preclude the existence of other objects. One embodiment of the present invention does not need to achieve all the objects. Other objects will be apparent from and can be derived from the description of the specification and the like.
One embodiment of the present invention is a display device including a pixel circuit and a light-emitting element. The pixel circuit includes a first element layer including a first transistor and a second element layer including a second transistor. A channel formation region of the first transistor includes silicon. The first transistor has a function of driving the light-emitting element. The second transistor functions as a switch. A channel formation region of the second transistor includes a metal oxide. The metal oxide functions as a semiconductor. The second element layer is provided over the first element layer.
One embodiment of the present invention is a display device including a pixel circuit and a light-emitting element. The pixel circuit includes a first element layer including a first transistor and a second element layer including a second transistor. A channel formation region of the first transistor includes silicon. The first transistor has a function of driving the light-emitting element. The second transistor functions as a switch. A channel formation region of the second transistor includes a metal oxide. The metal oxide functions as a semiconductor. The second element layer is provided over the first element layer. A layer including the light-emitting element is provided over the second element layer.
One embodiment of the present invention is a display device including a pixel circuit, a light-emitting element, and a driver circuit. The pixel circuit includes a first element layer including a first transistor and a second element layer including a second transistor. The driver circuit includes a third transistor and a fourth transistor. The driver circuit is electrically connected to a source line or a gate line. A channel formation region of the first transistor includes silicon. The first transistor has a function of driving the light-emitting element. The second transistor functions as a switch. A channel formation region of the second transistor includes a metal oxide. The metal oxide functions as a semiconductor. The third transistor and the fourth transistor are provided in the first element layer. The second element layer is provided over the first element layer.
One embodiment of the present invention is a display device including a pixel circuit, a light-emitting element, and a driver circuit. The pixel circuit includes a first element layer including a first transistor and a second element layer including a second transistor. The driver circuit includes a third transistor and a fourth transistor. The driver circuit is electrically connected to a source line or a gate line. A channel formation region of the first transistor includes silicon. The first transistor has a function of driving the light-emitting element. The second transistor functions as a switch. A channel formation region of the second transistor includes a metal oxide. The metal oxide functions as a semiconductor. The third transistor and the fourth transistor are provided in the first element layer. The second element layer is provided over the first element layer. A layer including the light-emitting element is provided over the second element layer.
The display device of one embodiment of the present invention preferably has the following configuration: the pixel circuit further includes a fifth transistor; the fifth transistor functions as a switch; and the fifth transistor is provided in the second element layer.
In this specification, a display device may include any of the following modules: a module in which a connector such as a flexible printed circuit (FPC) or a tape carrier package (TCP) is attached to a display element; a module having a TCP provided with a printed wiring board at the end thereof; and a module having an integrated circuit (IC) directly mounted by a chip on glass (COG) method over a substrate over which a display element is formed.
According to one embodiment of the present invention, a display device in which the resolution of a display portion can be increased can be provided. A display device whose bezel can be narrowed can be provided. A display device which can have an uncomplicated circuit design can be provided. A low-power display device can be provided. A novel display device can be provided. An electronic device including the display device (display panel) can be provided. A novel electronic device can be provided.
Note that the description of these effects does not preclude the existence of other effects. One embodiment of the present invention does not necessarily have all the effects. Other effects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like.
Embodiments will be described in detail with reference to the drawings. Note that the present invention is not limited to the following description, and it will be readily appreciated by those skilled in the art that modes and details can be modified in various ways without departing from the spirit and the scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments below.
In the structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description of such portions is not repeated. Furthermore, the same hatching pattern is applied to portions having similar functions, and the portions are not especially denoted by reference numerals in some cases.
In each drawing described in this specification, the size, the layer thickness, or the region of each component is exaggeratedly illustrated for clarity in some cases. Therefore, embodiments of the present invention are not limited to such a scale.
In this specification and the like, ordinal numbers such as “first” and “second” are used to avoid confusion among components and do not limit the components numerically.
In a display device of one embodiment of the present invention, a transistor for driving a light-emitting element (driver transistor) is provided in a first element layer, and a transistor functioning as a switch (selection transistor) for supplying a video voltage of a source line to a gate of the driver transistor is provided in a second element layer over the first element layer. The driver transistor includes silicon in a channel formation region, like a transistor formed using a silicon on insulator (SOI) substrate. A channel formation region of the selection transistor includes a metal oxide functioning as a semiconductor (hereinafter also referred to as an oxide semiconductor or an OS).
By arranging the driver transistor and the selection transistor in different layers, the layout area of the driver transistor can be increased. With the channel formation region including an oxide semiconductor, the selection transistor can have a higher withstand voltage than a transistor including silicon in a channel formation region. By arranging the selection transistor and the driver transistor in different element layers, restrictions on the circuit layout can be eased, so that the driver transistor can be designed to have a large channel length. This enables not only a circuit layout with a driver transistor having adjusted current supply capability but also an increase in withstand voltage of the driver transistor. Moreover, when an impurity element is added to the channel formation region, for example, the driver transistor can have less variation in electrical characteristics such as threshold voltage.
A display device 10 illustrated in
The driver circuit 11 functions as a gate line driver circuit. The driver circuit 11 outputs a scan signal to a gate line GL.
The driver circuit 12 functions as a source line driver circuit. The driver circuit 12 outputs a video voltage to each source line SL.
The display portion 13 includes a plurality of pixel circuits 20. The pixel circuit 20 has a function of driving a light-emitting element (not illustrated), i.e. a display element, in accordance with signals such as a scan signal and a video voltage.
The pixel circuit 20 includes an element layer 21 and an element layer 22. For example, the pixel circuit 20 includes two transistors: a selection transistor and a driver transistor.
As illustrated in
In the element layer 21, a transistor including silicon in a channel formation region (Si transistor) is provided as the driver transistor.
The Si transistor is preferably formed using single-crystal silicon such as a silicon on insulator (SOI) substrate or a separation by implanted oxygen (SIMOX) substrate. Alternatively, a Si transistor in which an impurity region and an element isolation region are directly formed in a single-crystal silicon wafer may also be used.
Note that the term “SOI substrate” in this specification refers not only to a substrate in which a silicon semiconductor layer is provided over an insulating surface but also to a substrate in which a semiconductor layer including a material other than silicon is provided over an insulating surface. That is, the semiconductor layer included in the “SOT substrate” is not limited to a silicon semiconductor layer. A substrate in the “SOT substrate” is not limited to a semiconductor substrate such as a silicon wafer and may be a non-semiconductor substrate such as a glass substrate, a quartz substrate, a sapphire substrate, or a metal substrate. That is, the term “SOT substrate” also includes a conductive substrate having an insulating surface and an insulating substrate over which a layer including a semiconductor material is provided.
The threshold voltage of a Si transistor can be easily controlled by channel doping. A Si transistor including single-crystal silicon in a channel formation region can have high field-effect mobility. Therefore, when the Si transistor in the element layer 21 is used as the driver transistor, variation in threshold voltage can be reduced and the amount of current flowing therethrough can be increased.
The driver transistor, i.e. the Si transistor in the element layer 21, and the selection transistor in the element layer 22 are vertically stacked in separate layers; thus, the layout area of the driver transistor can be increased. In this case, even when the area of one pixel is small, the Si transistor functioning as the driver transistor can surely have a large area. For example, in a display device with a pixel density of 3000 ppi, the area of one pixel, which corresponds to the area of one of striped subpixels, can be estimated to be approximately 2.75 μm×8.75 μm. In the case where the selection transistor and the driver transistor each have a channel length of 1 μm, this area imposes strict restrictions on the circuit layout including two transistors; in contrast, this area is large enough for one Si transistor having a channel length of 1 μm. Therefore, the channel length of the Si transistor can be increased, whereby the withstand voltage can be increased and excessive current supply capability can be adjusted. Note that ppi is a unit indicating the number of pixels per inch.
A Si transistor can be microfabricated. When formed using a Si transistor, a logic circuit or the like which needs to operate at high speed can be stacked over the same substrate as the pixel circuit. Accordingly, the weight of the display device 10 can be reduced, leading to a reduction in weight of an electronic device including the display device 10.
Although the driver transistor used for the element layer 21 is preferably a p-channel transistor, an n-channel may also be used. The transistor in the element layer 21 is a transistor including silicon in a channel formation region; as such a transistor, either a p-channel transistor or an n-channel transistor can be formed just by changing the conductivity type of an impurity element added.
As the light-emitting element whose light emission is controlled by the pixel circuit 20, for example, an organic EL element, an inorganic EL element, or a light-emitting diode (LED) element can be used.
In the element layer 22, a transistor including an oxide semiconductor in a channel formation region (OS transistor) is provided as the selection transistor.
An oxide semiconductor which can be used for the element layer 22 is resistant to avalanche breakdown and has a high withstand voltage. For example, in the case of silicon, which has a small band gap of 1.12 eV, avalanche-like generation of electrons, called avalanche breakdown, is likely to occur; this phenomenon increases the number of electrons which are so accelerated that they can go over a barrier to a gate insulating layer. In contrast, since the oxide semiconductor has a wide band gap of 2 eV or more, avalanche breakdown is less likely to occur and its resistance to hot-carrier degradation is higher than that of silicon; this is why the oxide semiconductor has a high withstand voltage.
The band gap of silicon carbide, which is one of materials having high withstand voltages, is substantially equal to the band gap of the oxide semiconductor used for an oxide semiconductor layer; however, the field-effect mobility of the oxide semiconductor is lower than that of silicon carbide by approximately two orders of magnitude. Thus, in the oxide semiconductor, electrons are less likely to be accelerated, and a barrier to a gate insulating layer is higher than that in silicon carbide, gallium nitride, or silicon; therefore, the number of electrons injected into the gate insulating layer is extremely small. Accordingly, the oxide semiconductor is less likely to cause hot-carrier degradation and has a higher withstand voltage than silicon carbide, gallium nitride, or silicon.
Therefore, even a miniaturized OS transistor has a low off-state current. Furthermore, an OS transistor has a higher withstand voltage than a Si transistor. A miniaturized OS transistor can operate even at a low frame frequency. Furthermore, a miniaturized OS transistor can be resistant to dielectric breakdown due to application of a video voltage.
Note that
In
As illustrated in
As illustrated in
By arranging the transistor M1 and the transistor M2 included in the pixel circuit 20 in different layers, the layout area of the transistor M2 can be increased. With the channel formation region including an oxide semiconductor, the transistor M1 can have a higher withstand voltage than a transistor including silicon in a channel formation region. By arranging the transistor M1 and the transistor M2 in different element layers, restrictions on the circuit layout can be eased, so that the transistor M2 can be designed to have a large channel length. This enables not only a circuit layout with the transistor M2 having adjusted current supply capability but also an increase in withstand voltage of the transistor M2. Moreover, when an impurity element is added to the channel formation region, for example, the transistor M2 can have less variation in electrical characteristics such as threshold voltage.
As the transistor M2, either an n-channel transistor or a p-channel transistor can be formed just by changing an impurity element which imparts a conductivity type and is added to the impurity region 36A and the impurity region 36B.
In
Examples of conductive materials that can be used for the gate electrode layer 39, the gate electrode layer 43C, the electrode layer 43A, the electrode layer 43B, the source electrode 46A, the drain electrode 46B, the electrode 46C, the conductive layer 50, and the conductive layer 53 will be given in the description of the conductive layers in Embodiment 2.
Examples of insulating materials that can be used for the insulating layer 33, the gate insulating layer 38, the insulating layer 40, the insulating layer 41, the insulating layer 42, the gate insulating layer 44, the insulating layer 47, the insulating layer 48, the insulating layer 49, and the insulating layer 51 will be given in the description of the insulating layers in Embodiment 2.
Examples of materials that can be used for the base substrate 31, the semiconductor layer 35, the EL layer 52, the impurity region 36A, the impurity region 36B, and the channel formation region 37 will be given in the description in Embodiment 2.
The oxide semiconductor layer 45 contains In, M (M is Al, Ga, Y, or Sn), and Zn. The oxide semiconductor layer 45 preferably includes a region in which the atomic proportion of In is higher than the atomic proportion of M, for example. Note that the semiconductor device of one embodiment of the present invention is not limited thereto; the oxide semiconductor layer 45 may include a region in which the atomic proportion of In is lower than the atomic proportion of M or a region in which the atomic proportion of In is equal to the atomic proportion of M.
When the oxide semiconductor layer 45 includes a region in which the atomic proportion of In is higher than the atomic proportion of M, the transistor M1 can have high field-effect mobility. Specifically, the field-effect mobility of the transistor M1 can exceed 10 cm2/Vs, preferably 30 cm2/Vs.
Note that it is preferable that the semiconductor layer 35 of the transistor M2 and the oxide semiconductor layer 45 of the transistor M1 not overlap with each other as illustrated in
If the semiconductor layer 35 of the transistor M2 and the oxide semiconductor layer 45 of the transistor M1 overlap with each other, operation of one of the transistors might affect the other. To avoid this influence, a structure in which the distance between the transistor M1 and the transistor M2 is increased, a structure in which a conductive layer is provided between the transistor M1 and the transistor M2, or the like can be used. However, the thickness of the display device is increased in the former structure. Thus, for example, when formed over a flexible substrate, the display device 10 may have a problem with bendability. When the latter structure is used, there may arise problems in that an additional step for forming the conductive layer is needed and the thickness of the display device is increased as in the former structure.
In contrast, in the display device 10 of one embodiment of the present invention, the transistor M1 and the transistor M2 are stacked such that the semiconductor layers of the transistors do not overlap with each other. By stacking the transistor M1 and the transistor M2, the layout flexibility of the transistors in one pixel can be increased.
The transistor M1 has a channel-etched structure in which part of the oxide semiconductor layer 45 is exposed between the source electrode 46A and the drain electrode 46B. The transistor M1 may have, instead of the channel-etched structure, a channel-protective structure. The transistor M2 has a top-gate structure in which the gate electrode layer 39 is provided over the channel formation region 37 of the semiconductor layer 35 with the gate insulating layer 38 positioned therebetween. The transistor M2 may have, instead of the top-gate structure, a double-gate structure or a multi-gate structure.
In the display device 10 of one embodiment of the present invention, as illustrated in
In
The buffer circuit 62 can be formed using transistors having the same conductivity type; however, as illustrated in
As illustrated in
In
In the above-described display device of one embodiment of the present invention, a transistor for driving a light-emitting element (driver transistor) is provided in a first element layer, and a transistor functioning as a switch (selection transistor) for supplying a video voltage of a source line to a gate of the driver transistor is provided in a second element layer over the first element layer. The driver transistor includes silicon in a channel formation region, like a transistor formed using a silicon on insulator (SOI) substrate. A channel formation region of the selection transistor includes a metal oxide functioning as a semiconductor (also referred to as an oxide semiconductor or an OS).
By arranging the driver transistor and the selection transistor in different layers, the layout area of the driver transistor can be increased. With the channel formation region including an oxide semiconductor, the selection transistor can have a higher withstand voltage than a transistor including silicon in a channel formation region. By arranging the selection transistor and the driver transistor in different element layers, restrictions on the circuit layout can be eased, so that the driver transistor can be designed to have a large channel length. This enables not only a circuit layout with a driver transistor having adjusted current supply capability but also an increase in withstand voltage of the driver transistor. Moreover, when an impurity element is added to the channel formation region, for example, the driver transistor can have less variation in electrical characteristics such as threshold voltage.
At least part of this embodiment can be implemented in combination with any of the other embodiments described in this specification as appropriate.
The display device of one embodiment of the present invention includes a transistor including silicon (Si transistor) and a transistor including an oxide semiconductor (OS transistor). The Si transistor can be formed using a silicon wafer, a silicon on insulator (SOI) substrate, a silicon thin film over an insulating surface, or the like. In this embodiment, a method for manufacturing the display device will be described with reference to
In this embodiment, the following example will be described: the Si transistor is formed using an SOI substrate, and then, the OS transistor is formed.
First, a method for manufacturing the SOI substrate will be described.
As illustrated in
As the bond substrate 80, a single-crystal silicon semiconductor substrate can be used. Alternatively, the bond substrate 80 may be a semiconductor substrate of silicon having crystal lattice distortion, silicon germanium obtained by adding germanium to silicon, or the like.
In a single-crystal semiconductor substrate used as the bond substrate 80, the directions of crystal axes are preferably uniform; however, perfect crystal without any lattice defect such as a point defect, a line defect, or a plane defect is unnecessary.
The bond substrate 80 does not necessarily have a circular shape and may be processed into a shape other than a circular shape. For example, in consideration of the facts that the shape of the base substrate 31 attached later is generally a rectangle and that an exposure region of an exposure apparatus such as a reduced projection exposure apparatus is rectangular, the bond substrate 80 may be processed into a rectangular shape. The bond substrate 80 can be processed by cutting a commercially available circular single-crystal semiconductor substrate.
The insulating layer 33 may be a single insulating layer or a stack of a plurality of insulating layers. Considering that a region containing impurities is removed later, the thickness of the insulating layer 33 is preferably greater than or equal to 15 nm and less than or equal to 500 nm.
An insulating layer containing silicon or germanium as its component, such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, a germanium oxide film, a germanium nitride film, a germanium oxynitride film, or a germanium nitride oxide film, can be used as a film included in the insulating layer 33. Alternatively, an insulating layer containing a metal oxide such as aluminum oxide, tantalum oxide, or hafnium oxide, an insulating layer containing a metal nitride such as aluminum nitride, an insulating layer containing a metal oxynitride such as aluminum oxynitride, or an insulating layer containing a metal nitride oxide such as aluminum nitride oxide can also be used.
In this embodiment, an example in which silicon oxide formed by thermal oxidation of the bond substrate 80 is used as the insulating layer 33 will be described. In
The insulating layer 33 is a film for forming a smooth hydrophilic bonding plane on the surface of the bond substrate 80. Therefore, the average surface roughness Ra of the insulating layer 33 is preferably 0.7 nm or less, further preferably 0.4 nm or less. The thickness of the insulating layer 33 is greater than or equal to 5 nm and less than or equal to 500 nm, preferably greater than or equal to 10 nm and less than or equal to 200 nm.
Next, as illustrated in
The depth of the region in which the embrittlement layer 82 is formed can be adjusted by the acceleration energy and the incident angle of the ion beam. The embrittlement layer 82 is formed in a region at a depth substantially the same as the average penetration depth of the ions. The thickness of a semiconductor layer 84 which is separated from the bond substrate 80 later is determined by the depth at which the ions are implanted. The depth at which the embrittlement layer 82 is formed can be, for example, greater than or equal to 50 nm and less than or equal to 500 nm, preferably greater than or equal to 50 nm and less than or equal to 200 nm from the surface of the bond substrate 80.
The ions are desirably implanted into the bond substrate 80 by an ion doping method in which mass separation is not performed because the cycle time can be shortened; however, one embodiment of the present invention may employ an ion implantation method in which mass separation is performed.
Next, as illustrated in
The attachment is performed as follows. The base substrate 31 and the insulating layer 33 on the bond substrate 80 are disposed in close contact with each other. Then, a pressure of approximately higher than or equal to 1 N/cm2 and lower than or equal to 500 N/cm2, preferably higher than or equal to 11 N/cm2 and lower than or equal to 20 N/cm2 is applied to part of the base substrate 31 and part of the bond substrate 80 stacked thereover. Bonding between the base substrate 31 and the insulating layer 33 starts from the portion to which the pressure is applied, which results in bonding of the entire surface on which the base substrate 31 and the insulating layer 33 are in close contact with each other.
The bonding is caused by Van der Waals force or a hydrogen bond; therefore, the bonding is firm even at room temperature. Since the above-described bonding can be performed at a low temperature, a variety of substrates can be used as the base substrate 31. For example, a variety of glass substrates used in the electronics industry, such as an aluminosilicate glass substrate, a barium borosilicate glass substrate, or an aluminoborosilicate glass substrate, a quartz substrate, a ceramic substrate, or a sapphire substrate, can be used as the base substrate 31. Alternatively, as the base substrate 31, a semiconductor substrate or the like of silicon, gallium arsenide, indium phosphide, or the like can be used. Further alternatively, the base substrate 31 may be a metal substrate including a stainless steel substrate. Note that a glass substrate used as the base substrate 31 preferably has a thermal expansion coefficient of greater than or equal to 25×10−7/° C. and less than or equal to 50×10−7/° C. (further preferably greater than or equal to 30×10−7/° C. and less than or equal to 40×10−7/° C.) and a strain point of higher than or equal to 580° C. and lower than or equal to 680° C. (further preferably higher than or equal to 600° C. and lower than or equal to 680° C.). When an alkali-free glass substrate is used as the glass substrate, impurity contamination of the display device can be suppressed.
As the glass substrate, a mother glass substrate developed for production of liquid crystal panels can be used. As the mother glass substrate, for example, substrates having the following sizes are known: the third generation (550 mm×650 mm), the 3.5-th generation (600 mm×720 mm), the fourth generation (680 mm×880 mm or 730 mm×920 mm), the fifth generation (1100 mm×1300 mm), the sixth generation (1500 mm×1850 mm), the seventh generation (1870 mm×2200 mm), and the eighth generation (2200 mm×2400 mm). When an SOI substrate is manufactured using a large-area mother glass substrate as the base substrate 31, the SOI substrate can have a large area.
Next, heat treatment is performed, whereby microvoids adjacent to each other in the embrittlement layer 82 are combined and increase in volume. As a result, as illustrated in
For this heat treatment, a rapid thermal annealing (RTA) apparatus, a resistance heating furnace, or a microwave heating apparatus can be used. As the RTA apparatus, a gas rapid thermal annealing (GRTA) apparatus or a lamp rapid thermal annealing (LRTA) apparatus can be used. When a GRTA apparatus is used, the heating temperature can be higher than or equal to 550° C. and lower than or equal to 650° C., and the treatment time can be longer than or equal to 0.5 minutes and shorter than or equal to 60 minutes. When a resistance heating furnace is used, the heating temperature can be higher than or equal to 200° C. and lower than or equal to 650° C., and the treatment time can be longer than or equal to 2 hours and shorter than or equal to 4 hours.
Owing to the formation of the embrittlement layer 82 and the split along the embrittlement layer 82, crystal defects are formed in the semiconductor layer 84 which is in close contact with the base substrate 31, or the planarity of the surface of the semiconductor layer 84 is impaired. Thus, in one embodiment of the present invention, in order to reduce crystal defects and improve the planarity, the semiconductor layer 84 is irradiated with a laser beam after treatment for removing an oxide film such as a native oxide film which is formed on the surface of the semiconductor layer 84.
In this embodiment, the semiconductor layer 84 is immersed in DHF having a hydrogen fluoride concentration of 0.5 wt % for 110 seconds, whereby the oxide film is removed.
The semiconductor layer 84 is preferably irradiated with a laser beam having such an energy density that the semiconductor layer 84 can be partly melted. The reason for this is as follows: if the semiconductor layer 84 is completely melted, disordered nucleation occurs in the liquid-phase semiconductor layer 84; in this case, microcrystals are generated when the semiconductor layer 84 is recrystallized, so that the crystallinity decreases. By partly melting the semiconductor layer 84, crystal growth called longitudinal growth occurs from an unmelted solid portion. Due to the recrystallization by the longitudinal growth, crystal defects in the semiconductor layer 84 are reduced and the crystallinity is recovered. Note that the state in which the semiconductor layer 84 is completely melted refers to the state in which the semiconductor layer 84 is melted to the interface with the insulating layer 33 and is in a liquid phase. In contrast, the state in which the semiconductor layer 84 is partly melted refers to the state in which an upper part is melted and is in a liquid phase and a lower part is in a solid phase.
In this embodiment, in the case where the thickness of the semiconductor layer 84 is approximately 146 nm, the laser beam irradiation can be performed in the following manner. As a laser, a XeCl excimer laser (wavelength: 308 nm; pulse width: 20 nanoseconds; repetition rate: 30 Hz) is used. The cross section of the laser beam is shaped into a linear form with a size of 0.4 mm×120 mm through an optical system. The semiconductor layer 84 is irradiated with the laser beam at a scanning speed of 0.5 mm/s. Through the laser beam irradiation, a semiconductor layer 85 in which crystal defects have been repaired is formed as illustrated in
Next, after the laser beam irradiation, a surface of the semiconductor layer 85 may be etched. In the case where the surface of the semiconductor layer 85 is etched after the laser beam irradiation, the surface of the semiconductor layer 84 is not necessarily etched before the laser beam irradiation. In the case where the surface of the semiconductor layer 84 is etched before the laser beam irradiation, the surface of the semiconductor layer 85 is not necessarily etched after the laser beam irradiation. Alternatively, the surface of the semiconductor layer may be etched before and after the laser beam irradiation.
The above etching enables not only a reduction in thickness of the semiconductor layer 85 to an optimal thickness for a semiconductor element completed later but also planarization of the surface of the semiconductor layer 85.
After the laser beam irradiation, the semiconductor layer 85 is preferably subjected to heat treatment at a temperature of higher than or equal to 500° C. and lower than or equal to 650° C. This heat treatment can eliminate defects in the semiconductor layer 85, which have not been repaired by the laser beam irradiation, and can relieve distortion of the semiconductor layer 85, which has not been repaired by the laser beam irradiation. For this heat treatment, a rapid thermal annealing (RTA) apparatus, a resistance heating furnace, or a microwave heating apparatus can be used. As the RTA apparatus, a gas rapid thermal annealing (GRTA) apparatus or a lamp rapid thermal annealing (LRTA) apparatus can be used. For example, when a resistance heating furnace is used, the heat treatment may be performed at 600° C. for 4 hours.
Next, as illustrated in
To control the threshold voltage, a p-type impurity such as boron, aluminum, or gallium or an n-type impurity such as phosphorus or arsenic may be added to the semiconductor layer 35.
Next, the gate insulating layer 38 is formed so as to cover the semiconductor layer 35 as illustrated in
Since the oxidation or nitridation of the semiconductor film by the high-density plasma treatment proceeds by a solid-phase reaction, the interface state density between the gate insulating layer 38 and the semiconductor layer 35 can be significantly reduced. Furthermore, since the semiconductor layer 35 is directly oxidized or nitrided by the high-density plasma treatment, variation in thickness of the formed insulating layer can be suppressed. In the case where the semiconductor film has crystallinity, by oxidation of the surface of the semiconductor film by a solid-phase reaction in the high-density plasma treatment, crystal grain boundaries can be prevented from being locally oxidized at high speed; thus, a uniform gate insulating layer with low interface state density can be formed. A transistor whose gate insulating layer partly or entirely includes the insulating layer formed by the high-density plasma treatment can have less variation in characteristics.
Alternatively, the gate insulating layer 38 may also be formed by thermal oxidation of the semiconductor layer 35. Further alternatively, as the gate insulating layer 38, a single layer or a stack including a film containing silicon oxide, silicon nitride oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, or tantalum oxide may be formed by a plasma CVD method, a sputtering method, or the like.
A conductive layer is formed over the gate insulating layer 38 and then processed into a predetermined shape, so that the gate electrode layer 39 is formed over the semiconductor layer 35. The gate electrode layer 39 can be formed by a CVD method, a sputtering method, or the like. For the gate electrode layer 39, tantalum (Ta), tungsten (W), titanium (Ti), molybdenum (Mo), aluminum (Al), copper (Cu), chromium (Cr), niobium (Nb), or the like can be used. Moreover, an alloy containing the above metal as a main component or a compound containing the above metal may be used. Alternatively, the gate electrode layer 39 may be formed using a semiconductor such as polycrystalline silicon doped with an impurity element such as phosphorus, which imparts conductivity to the semiconductor film.
Although the gate electrode layer 39 is formed of a single-layer conductive layer in this embodiment, this embodiment is not limited to this structure. The gate electrode layer 39 may be formed of stacked conductive layers.
In the case where two conductive layers are combined, tantalum nitride or tantalum can be used for a first layer, and tungsten can be used for a second layer. Besides, the following combinations can be given: tungsten nitride and tungsten, molybdenum nitride and molybdenum, aluminum and tantalum, aluminum and titanium, and the like. Since tungsten and tantalum nitride have high heat resistance, heat treatment for thermal activation can be performed after the two conductive layers are formed. As another example of a combination of two conductive layers, silicon doped with an impurity which imparts n-type conductivity and nickel silicide or silicon doped with an impurity which imparts n-type conductivity and tungsten silicide can be used. In the case of a three-layer structure in which three conductive layers are stacked, a stacked structure of a molybdenum film, an aluminum film, and a molybdenum film is preferably employed.
Next, as illustrated in
Next, as illustrated in
Note that the insulating layer 41 and the insulating layer 42 are stacked over the insulating layer 40 in this embodiment; however, the insulating layer formed over the insulating layer 40 may be a single-layer insulating layer or a stack of three or more insulating layers.
A surface of the insulating layer 42 may be planarized by chemical mechanical polishing (CMP) or the like.
Next, as illustrated in
As the gate electrode layer 43C, the electrode layer 43A, and the electrode layer 43B, a single layer or a stack including a conductive layer containing a metal material such as molybdenum, titanium, chromium, tantalum, tungsten, neodymium, or scandium, an alloy material which contains any of these metal materials as a main component, or a nitride of any of these metals can be used. Note that aluminum or copper can also be used as such a metal material if aluminum or copper can withstand a temperature of heat treatment performed in a later step. Aluminum or copper is preferably combined with a high-melting-point metal material to avoid problems of heat resistance and corrosion. As the high-melting-point metal material, molybdenum, titanium, chromium, tantalum, tungsten, neodymium, scandium, or the like can be used.
For example, as a two-layer structure of the gate electrode layer 43C, the electrode layer 43A, and the electrode layer 43B, the following structures are preferable: a two-layer structure in which a molybdenum film is stacked over an aluminum film, a two-layer structure in which a molybdenum film is stacked over a copper film, a two-layer structure in which a titanium nitride film or a tantalum nitride film is stacked over a copper film, and a two-layer structure in which a titanium nitride film and a molybdenum film are stacked. As a three-layer structure of the gate electrode layer 43C, the electrode layer 43A, and the electrode layer 43B, the following structure is preferable: a stacked structure in which an aluminum film, an aluminum-silicon alloy film, an aluminum-titanium alloy film, or an aluminum-neodymium alloy film is used as a middle layer and any of a tungsten film, a tungsten nitride film, a titanium nitride film, and a titanium film is used as a top layer and a bottom layer.
Furthermore, a light-transmitting conductive oxide layer of indium oxide, indium tin oxide, indium oxide-zinc oxide, zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, zinc gallium oxide, or the like can be used as the gate electrode layer 43C, the electrode layer 43A, and the electrode layer 43B.
The gate electrode layer 43C, the electrode layer 43A, and the electrode layer 43B each have a thickness of 10 nm to 400 nm, preferably 100 nm to 200 nm. In this embodiment, a conductive layer for the gate electrode is formed to a thickness of 150 nm by a sputtering method using a tungsten target, and then, the conductive layer is processed into a desired shape by etching; thus, the gate electrode layer 43C, the electrode layer 43A, and the electrode layer 43B are formed. Note that end portions of the formed gate electrode are preferably tapered, in which case coverage with a gate insulating layer stacked thereover is improved. Note that a resist mask may be formed by an inkjet method. Formation of the resist mask by an inkjet method needs no photomask; thus, manufacturing cost can be reduced.
Next, as illustrated in
An i-type or substantially i-type oxide semiconductor (highly purified oxide semiconductor) obtained by removal of impurities is very sensitive to an interface state and interface charge; thus, an interface between the highly purified oxide semiconductor and the gate insulating layer 44 is important. Therefore, the gate insulating layer (GI) which is in contact with the highly purified oxide semiconductor needs high quality.
For example, high-density plasma CVD using microwaves (2.45 GHz) is preferable because a dense high-quality insulating layer having a high withstand voltage can be formed. When the highly purified oxide semiconductor and the high-quality gate insulating layer are in close contact with each other, interface states can be reduced and interface characteristics can be improved.
Needless to say, another deposition method such as a sputtering method or a plasma CVD method can be used as long as a high-quality insulating layer can be formed as the gate insulating layer. Alternatively, an insulating layer whose film quality as a gate insulating layer and characteristics of the interface between the gate insulating layer and the oxide semiconductor are improved by heat treatment after deposition may be used. In any case, an insulating layer which has favorable film quality as a gate insulating layer and can form a favorable interface with low state density between the gate insulating layer and the oxide semiconductor is used.
The gate insulating layer 44 may have a structure in which an insulating layer formed using a material having a high barrier property and an insulating layer having a low nitrogen content, such as a silicon oxide film or a silicon oxynitride film, are stacked. In this case, the insulating layer such as a silicon oxide film or a silicon oxynitride film is formed between the insulating layer having a high barrier property and the oxide semiconductor layer. As the insulating layer having a high barrier property, a silicon nitride film, a silicon nitride oxide film, an aluminum nitride film, or an aluminum nitride oxide film can be used, for example. The insulating layer having a high barrier property is used, so that an impurity in an atmosphere, such as moisture or hydrogen, or an impurity contained in the substrate, such as an alkali metal or a heavy metal, can be prevented from entering the oxide semiconductor layer, the gate insulating layer 44, the interface between the oxide semiconductor layer and another insulating layer, or the vicinity thereof. In addition, the insulating layer having a low nitrogen content, such as a silicon oxide film or a silicon oxynitride film, is formed in contact with the oxide semiconductor layer, so that the insulating layer having a high barrier property can be prevented from being in direct contact with the oxide semiconductor layer.
For example, a 100-nm-thick stack may be formed as the gate insulating layer 44 as follows: a silicon nitride film (SiNy (y>0)) with a thickness of greater than or equal to 50 nm and less than or equal to 200 nm is formed by a sputtering method as a first gate insulating layer, and a silicon oxide film (SiOx (x>0)) with a thickness of greater than or equal to 5 nm and less than or equal to 300 nm is stacked as a second gate insulating layer over the first gate insulating layer. The thickness of the gate insulating layer 44 may be set as appropriate in accordance with characteristics needed for the transistor and may be approximately 350 nm to 400 nm.
In this embodiment, the gate insulating layer 44 is formed to have a structure in which a 100-nm-thick silicon oxide film formed by a sputtering method is stacked over a 50-nm-thick silicon nitride film formed by a sputtering method.
In order that the gate insulating layer 44 may contain hydrogen, a hydroxyl group, and moisture as little as possible, it is preferable that an impurity such as moisture or hydrogen adsorbed on the base substrate 31 be released and removed by preheating the base substrate 31 provided with the gate electrode layer 43C, the electrode layer 43A, and the electrode layer 43B in a preheating chamber of a sputtering apparatus, as a pretreatment for deposition. The preheating temperature is higher than or equal to 100° C. and lower than or equal to 400° C., preferably higher than or equal to 150° C. and lower than or equal to 300° C. As an exhaust unit provided in the preheating chamber, a cryopump is preferable. Note that this preheating treatment can be omitted.
Next, over the gate insulating layer 44, an oxide semiconductor layer having a thickness of greater than or equal to 2 nm and less than or equal to 200 nm, preferably greater than or equal to 3 nm and less than or equal to 50 nm, further preferably greater than or equal to 3 nm and less than or equal to 20 nm is formed. The oxide semiconductor layer is deposited by a sputtering method using an oxide semiconductor target. Moreover, the oxide semiconductor layer can be formed by a sputtering method in a rare gas (e.g., argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas (e.g., argon) and oxygen. Then, as illustrated in
The above-mentioned oxide semiconductor can be used for the oxide semiconductor layer.
In this embodiment, as the oxide semiconductor layer, a 30-nm-thick In—Ga—Zn—O-based non-single-crystal film obtained by a sputtering method using a metal oxide target containing indium (In), gallium (Ga), and zinc (Zn) is used. As the target, a metal oxide target having a composition of metals of In:Ga:Zn=1:1:0.5, In:Ga:Zn=1:1:1, or In:Ga:Zn=1:1:2 can be used, for example. The target may contain SiO2 at higher than or equal to 2 wt % and lower than or equal to 10 wt %. The filling rate of the metal oxide target containing In, Ga, and Zn is higher than or equal to 90% and lower than or equal to 100%, preferably higher than or equal to 95% and lower than or equal to 99.9%. With the use of a metal oxide target with a high filling rate, a dense oxide semiconductor layer is deposited.
Next, the gate insulating layer 44 is partly etched to form a contact hole reaching the electrode layer 43B. Subsequently, a conductive layer used for the source electrode or the drain electrode (including a wiring formed in the same layer as the source electrode or the drain electrode) is formed over the oxide semiconductor layer 45 by a sputtering method or a vacuum evaporation method; then, the conductive layer is patterned by etching or the like. Thus, as illustrated in
As a material of the conductive layer to be the source electrode and the drain electrode (including the wiring formed in the same layer as the source electrode and the drain electrode), an element selected from Al, Cr, Cu, Ta, Ti, Mo, and W, an alloy containing the above element as a component, an alloy film containing a combination of any of the above elements, or the like can be used. Alternatively, a stacked structure may be employed in which a film of a high-melting-point metal such as Cr, Ta, Ti, Mo, or W is provided over or under a metal film of Al, Cu, or the like. Furthermore, when an Al material to which an element for preventing hillocks or whiskers in an Al film, such as Si, Ti, Ta, W, Mo, Cr, Nd, Sc, or Y, is added is used, the heat resistance can be improved.
Furthermore, the conductive layer may have a single-layer structure or a stacked structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked over an aluminum film, and a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order can be given.
Next, as illustrated in
As each of the insulating layers 47 to 49, an insulating layer including at least one of the following films can be used: a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film.
Next, as illustrated in
Next, as illustrated in
Next, as illustrated in
The EL layer 52 includes at least a light-emitting layer. In addition to the light-emitting layer, the EL layer 52 may include a layer containing a substance with a high hole-injection property, a substance with a high hole-transport property, a hole-blocking material, a substance with a high electron-transport property, a substance with a high electron-injection property, a substance with a bipolar property (a substance with a high electron-transport property and a high hole-transport property), or the like.
For the EL layer 52, either a low molecular compound or a high molecular compound can be used, and an inorganic compound may also be used. Each of the layers included in the EL layer 52 can be formed by an evaporation method (including a vacuum evaporation method), a transfer method, a printing method, an inkjet method, a coating method, or the like.
In the case where a light-emitting element emitting white light is used as the light-emitting element, the EL layer 52 preferably contains two or more kinds of light-emitting substances. For example, white emission can be obtained by selecting two or more light-emitting substances such that the light-emitting substances emit light of complementary colors. Specifically, it is preferable to select two or more light-emitting substances from those emitting light of red (R), green (G), blue (B), yellow (Y), orange (O), and the like and those emitting light including two or more spectral components of R, G, and B. The light-emitting element preferably emits light with a spectrum having two or more peaks in the visible wavelength range (e.g., 350 nm to 750 nm). An emission spectrum of a material emitting light having a peak in a yellow wavelength range preferably includes spectral components also in green and red wavelength ranges.
A light-emitting layer containing a light-emitting material emitting light of one color and a light-emitting layer containing a light-emitting material emitting light of another color are preferably stacked in the EL layer 52. For example, the plurality of light-emitting layers in the EL layer 52 may be stacked in contact with each other, or a region which contains no light-emitting material may be provided between the stacked light-emitting layers. For example, between a fluorescent layer and a phosphorescent layer, a region which contains the same material (e.g., a host material or an assist material) as the fluorescent layer or the phosphorescent layer and contains no light-emitting material may be provided. This facilitates the manufacture of the light-emitting element and reduces the drive voltage.
The light-emitting element EL may be a single element including one EL layer 52 or a tandem element in which a plurality of EL layers 52 is stacked with a charge generation layer positioned therebetween.
The conductive layer 53 is preferably formed using a metal, an alloy, or a conductive compound having a low work function (a work function of 3.8 eV or lower), a mixture thereof, or the like. For the conductive layer 53, for example, an element belonging to Group 1 or 2 of the periodic table, that is, an alkali metal such as Li or Cs or an alkaline earth metal such as Mg, Ca, or Sr can be used. As other specific examples of the cathode material, an alloy containing an alkali metal or an alkaline earth metal (e.g., Mg:Ag or Al:Li), a metal compound containing an alkali metal or an alkaline earth metal (e.g., LiF, CsF, or CaF2), and a transition metal including a rare earth metal can be given.
Through the above process, the display device illustrated in
Note that the structures and the methods described in this embodiment can be used in appropriate combination with any of the structures and the methods described in the other embodiments.
In this embodiment, a display module for which the display device of one embodiment of the present invention can be used will be described. A display module including the display device of one embodiment of the present invention will be described with reference to
In a display module 800 illustrated in
The display device of one embodiment of the present invention can be used for, for example, the display panel 806. Therefore, a display portion with an extremely high resolution can be obtained.
The shapes and sizes of the upper cover 801 and the lower cover 802 can be changed as appropriate in accordance with the sizes of the touch panel 804 and the display panel 806.
The touch panel 804 can be a resistive touch panel or a capacitive touch panel and can be stacked over the display panel 806. Alternatively, a counter substrate (sealing substrate) of the display panel 806 can have a touch panel function. Further alternatively, a photosensor can be provided in each pixel of the display panel 806 so that an optical touch panel is obtained.
The frame 809 protects the display panel 806 and functions as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed board 810. The frame 809 may also function as a radiator plate.
The printed board 810 includes a power supply circuit and a signal processing circuit for outputting a video signal and a clock signal. As a power source for supplying power to the power supply circuit, an external commercial power source or the battery 811 provided separately may be used. The battery 811 can be omitted in the case of using a commercial power source.
The display module 800 may be additionally provided with a polarizing plate, a retardation plate, a prism sheet, or the like.
At least part of this embodiment can be implemented in combination with any of the other embodiments described in this specification as appropriate.
In this embodiment, examples of an electronic device for which the display device of one embodiment of the present invention can be used will be described.
An electronic device can be manufactured using the display device of one embodiment of the present invention. With the use of the display device of one embodiment of the present invention, an electronic device including a display portion with an extremely high resolution can be manufactured.
Examples of the electronic device include a television set, a desktop or laptop personal computer, a monitor of a computer or the like, a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game console, a portable information terminal, an audio reproducing device, and a large game machine such as a pachinko machine.
The electronic device of one embodiment of the present invention can be installed along a curved inner/outer wall of a house or a building or a curved interior/exterior surface of an automobile.
The electronic device of one embodiment of the present invention may include a secondary battery. Preferably, the secondary battery is capable of being charged by contactless power transmission.
Examples of the secondary battery include a lithium-ion secondary battery such as a lithium polymer battery (lithium-ion polymer battery) using a gel electrolyte, a nickel hydride battery, a nickel-cadmium battery, an organic radical battery, a lead-acid battery, an air secondary battery, a nickel-zinc battery, and a silver-zinc battery.
The electronic device of one embodiment of the present invention may include an antenna. When a signal is received by the antenna, an image, information, or the like can be displayed on the display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.
The electronic device of one embodiment of the present invention may include a sensor (a sensor having a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotational frequency, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, electric power, radiation, flow rate, humidity, gradient, oscillation, odor, or infrared rays).
The electronic device of one embodiment of the present invention can have a variety of functions, for example, a function of displaying a variety of information (e.g., a still image, a moving image, and a text image) on the display portion, a touch panel function, a function of displaying a calendar, the date, the time, or the like, a function of executing a variety of software (programs), a wireless communication function, and a function of reading a program or data stored in a recording medium.
Furthermore, an electronic device including a plurality of display portions can have a function of displaying image information mainly on one display portion while displaying text information mainly on another display portion, a function of displaying a three-dimensional image by displaying images where parallax is considered on the plurality of display portions, or the like. Furthermore, an electronic device including an image receiving portion can have a function of taking a still image or a moving image, a function of automatically or manually correcting a shot image, a function of storing a shot image in a recording medium (an external recording medium or a recording medium incorporated in the electronic device), a function of displaying a shot image on a display portion, or the like. Note that the electronic device of one embodiment of the present invention can have a variety of functions which are not limited to these examples.
The display portion 7000 includes the display device or the like of one embodiment of the present invention. According to one embodiment of the present invention, an electronic device including a display portion with an extremely high resolution can be provided.
Each of the mobile phones includes a touch sensor in the display portion 7000. Operations such as making a call and inputting texts can be performed by touch on the display portion 7000 with a finger, a stylus, or the like.
With the operation button 7103, power can be turned on or off. In addition, types of images displayed on the display portion 7000 can be switched; for example, switching from a mail creation screen to a main menu screen can be performed.
When a detection device such as a gyroscope sensor or an acceleration sensor is provided inside the mobile phone, the direction of display on the screen of the display portion 7000 can be automatically changed by determining the orientation of the mobile phone (whether the mobile phone is placed horizontally or vertically). The direction of display on the screen can also be changed by touch on the display portion 7000, operation with the operation button 7103, sound input using the microphone 7106, or the like.
Each of the portable information terminals described in this embodiment has one or more of a telephone function, a notebook function, and an information browsing function, for example. Specifically, each of the portable information terminals can be used as a smartphone. Each of the portable information terminals described in this embodiment can execute a variety of applications, such as mobile phone calls, e-mailing, reading and editing texts, music reproduction, Internet communication, and a computer game, for example.
The portable information terminal 7200 and the portable information terminal 7210 can display texts, image information, and the like on their plurality of surfaces. For example, as illustrated in
Examples of the information include notification from a social networking service (SNS), display indicating reception of an e-mail or an incoming call, the title or the sender of an e-mail or the like, the date, the time, the remaining battery, and the reception strength of an antenna. Alternatively, an operation button, an icon, or the like may be displayed in place of the information.
For example, a user of the portable information terminal 7200 can see the display (here, the information 7203) on the portable information terminal 7200 put in a breast pocket of his/her clothes.
Specifically, a caller's phone number, name, or the like of an incoming call is displayed in a position that can be seen from above the portable information terminal 7200. Thus, the user can see the display without taking out the portable information terminal 7200 from the pocket and decide whether to answer the call.
The television set 7300 illustrated in
Note that the television set 7300 is provided with a receiver, a modem, and the like. With the use of the receiver, general television broadcasting can be received. When the television set is connected to a communication network with or without wires via the modem, one-way (from a transmitter to a receiver) or two-way (between a transmitter and a receiver or between receivers) data communication can be performed.
The display portion 7001 includes the display device or the like of one embodiment of the present invention. The display portion 7001 may be provided with a touch sensor so that the portable information terminal can be operated by touching the display portion 7001 with a finger or the like. According to one embodiment of the present invention, an electronic device including a display portion with an extremely high resolution can be provided.
The portable information terminal 7500 includes the flexible display portion 7001 that is rolled in the housing 7501. The display portion 7001 can be pulled out with the display portion pull 7502.
The portable information terminal 7500 can receive an image signal with a control portion incorporated therein and can display the received image on the display portion 7001. Furthermore, the portable information terminal 7500 incorporates a battery. The housing 7501 may include a terminal portion for connecting a connector so that an image signal and power can be directly supplied from the outside through a wire.
With the operation buttons 7503, for example, power can be turned on or off and displayed images can be switched. Although
Note that a reinforcement frame may be provided for a side portion of the display portion 7001 so that the display portion 7001 maintains a flat display surface when pulled out.
In addition to this structure, a speaker may be provided in the housing so that sound can be output in accordance with an audio signal received together with an image signal.
The display portion 7001 is supported by three housings 7601 joined together by hinges 7602. By being folded at the hinges 7602 between the two housings 7601, the portable information terminal 7600 can be reversibly changed in shape from the opened state to the folded state.
The housing 7701, the display portion 7001, and the battery 7709 have flexibility. Thus, it is easy to bend the portable information terminal 7700 into a desired shape and to twist the portable information terminal 7700. For example, the portable information terminal 7700 can be bent so that the display portion 7001 is on the inside or on the outside. The portable information terminal 7700 can also be used in the rolled state. Since the housing 7701 and the display portion 7001 can be freely transformed in this manner, the portable information terminal 7700 has an advantage of being less likely to be broken even when the portable information terminal 7700 is dropped down or accidentally subjected to external forces.
The portable information terminal 7700 is lightweight and therefore can be used conveniently in various situations. For example, the portable information terminal 7700 can be suspended by a clip or the like for holding an upper portion of the housing 7701 or hung on a wall with a magnet or the like for fixing the housing 7701.
The band 7801, the display portion 7001, and the battery 7805 have flexibility. Thus, the portable information terminal 7800 can be easily bent into a desired shape.
The operation buttons 7803 can have a variety of functions such as time setting, ON/OFF of the power, ON/OFF of wireless communication, setting and cancellation of a silent mode, and setting and cancellation of a power saving mode. For example, the functions of the operation buttons 7803 can be freely set by an operating system incorporated in the portable information terminal 7800.
By touching an icon 7804 displayed on the display portion 7001 with a finger or the like, an application can be started.
The portable information terminal 7800 can employ near field communication conformable to a communication standard. For example, through mutual communication with a headset capable of wireless communication, hands-free calling is possible.
The portable information terminal 7800 may include the input/output terminal 7802. In the case where the input/output terminal 7802 is provided, data can be directly communicated with another information terminal via a connector. Charging through the input/output terminal 7802 is also possible. Note that charging of the portable information terminal described in this embodiment can also be performed by contactless power transmission without using the input/output terminal.
The display device of one embodiment of the present invention can be used for a display portion or the like of the automobile 7900. For example, the display device of one embodiment of the present invention can be provided in display portions 7910 to 7917 illustrated in
The display portion 7910 and the display portion 7911 are provided in part of the windshield of the automobile. Therefore, the driver's vision is not hindered during the driving of the automobile 7900. Thus, the display device of one embodiment of the present invention can be provided in part of the windshield of the automobile 7900.
The display portion 7912 is provided in a pillar portion. The display portion 7913 is provided in a dashboard portion. For example, the display portion 7912 can compensate for the view hindered by the pillar by showing an image taken by an imaging unit provided on the car body. Similarly, the display portion 7913 can compensate for the view hindered by the dashboard, and the display portion 7914 can compensate for the view hindered by the door. That is, by displaying images taken by the imaging unit provided on the outside of the automobile, blind areas can be eliminated and safety can be increased. When images are displayed to compensate for the blind areas, the driver can confirm safety easily and comfortably.
The display portion 7917 is provided on a steering wheel. The display portion 7915, the display portion 7916, or the display portion 7917 can display a variety of information such as navigation information, a speedometer, a tachometer, a mileage, a fuel meter, a gearshift indicator, and air-condition setting. The content, layout, or the like of the display on the display portions can be changed freely by a user as appropriate. The information listed above can also be displayed on the display portions 7910 to 7914.
A display portion including the display device of one embodiment of the present invention may have a flat surface. In this case, the display device of one embodiment of the present invention does not necessarily have a curved surface and flexibility.
The digital signage in
The display portion 8001 with a larger area can provide more information at a time. In addition, the display portion 8001 with a larger area can attract more attention, so that the effect of an advertisement can be increased, for example.
It is preferable to use a touch panel for the display portion 8001 because a user can intuitively operate the display portion 8001, not just seeing a still or moving image displayed thereon. Moreover, for the purpose of providing information such as route information or traffic information, such intuitive operation can enhance usability.
The portable game console illustrated in
The display device of one embodiment of the present invention can be used for the display portion 8112.
The camera 8400 includes a housing 8401, a display portion 8402, operation buttons 8403, a shutter button 8404, and the like. Furthermore, a detachable lens 8406 is attached to the camera 8400.
Although the lens 8406 of the camera 8400 here is detachable from the housing 8401 for replacement, the lens 8406 may be built into the housing.
When the shutter button 8404 is pressed, the camera 8400 can take an image. In addition, the display portion 8402 functions as a touch panel, and an image can be taken when the display portion 8402 is touched.
The housing 8401 of the camera 8400 has a mount including an electrode, to which the finder 8500, a stroboscope, and the like can be connected.
The finder 8500 includes a housing 8501, a display portion 8502, a button 8503, and the like.
The housing 8501 includes a mount for engagement with the mount of the camera 8400 so that the finder 8500 can be attached to the camera 8400. The mount includes an electrode, and an image or the like received from the camera 8400 through the electrode can be displayed on the display portion 8502.
The button 8503 functions as a power button. The display portion 8502 can be turned on and off with the button 8503.
The display device of one embodiment of the present invention can be used for the display portion 8402 of the camera 8400 and the display portion 8502 of the finder 8500.
Although the camera 8400 and the finder 8500 are separate electronic devices and are detachable from each other in
The head-mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display portion 8204, a cable 8205, and the like. The mounting portion 8201 includes a battery 8206.
Power is supplied from the battery 8206 to the main body 8203 through the cable 8205. The main body 8203 includes a wireless receiver or the like to receive video data, such as image data, and display it on the display portion 8204. The movement of the eyeballs or the eyelids of a user is captured by a camera in the main body 8203, and then, the coordinates of the point the user looks at are calculated using the captured information to utilize the user's eyes as an input means.
The mounting portion 8201 may include a plurality of electrodes so as to be in contact with the user. The main body 8203 may have a function of sensing a current which flows through the electrodes in accordance with the movement of the user's eyeballs to determine the point the user looks at. The main body 8203 may also have a function of sensing a current flowing through the electrodes to monitor the user's pulse. The mounting portion 8201 may include sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor so that the user's biological information can be displayed on the display portion 8204. The movement of the user's head or the like may be sensed so that an image displayed on the display portion 8204 can be changed in synchronization with the movement.
The display device of one embodiment of the present invention can be used for the display portion 8204.
The head-mounted display 8300 includes a housing 8301, two display portions 8302, an operation button 8303, and a band-like fixing member 8304.
The head-mounted display 8300 has the functions of the above-described head-mounted display 8200 and includes two display portions.
Since the head-mounted display 8300 includes the two display portions 8302, the user's eyes can see their respective display portions. Thus, for example, even a high-resolution three-dimensional image using parallax can be displayed. In addition, the display portion 8302 is curved around an arc with an approximate center at the user's eye. This allows a uniform distance between the user's eye and the display surface of the display portion; thus, the user can see a more natural image. Furthermore, the user's eye is positioned in the normal direction of the display surface of the display portion; therefore, even when the luminance or chromaticity of light from the display portion is changed depending on the viewing angle, the influence of the change can be substantially ignorable and thus a more realistic image can be displayed.
The operation button 8303 functions as a power button or the like. Besides the operation button 8303, a button may be provided.
As illustrated in
The display device of one embodiment of the present invention can be used for the display portion 8302. The display device of one embodiment of the present invention can have an extremely high resolution; thus, even when images are magnified using the lenses 8305 as illustrated in
The display portion 8302 can display an image for the right eye and an image for the left eye side by side on a right region and a left region, respectively. Thus, a three-dimensional image using binocular disparity can be displayed.
One image which can be seen with both eyes may be displayed on the entire display portion 8302. Thus, a panorama image can be displayed from end to end of the field of view, which can provide a higher sense of reality.
As illustrated in
As illustrated in
At least part of this embodiment can be implemented in combination with any of the other embodiments described in this specification as appropriate.
This application is based on Japanese Patent Application Serial No. 2016-152394 filed with Japan Patent Office on Aug. 3, 2016, the entire contents of which are hereby incorporated by reference.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2016-152394 | Aug 2016 | JP | national |
This application is a continuation of copending U.S. application Ser. No. 17/673,212, filed on Feb. 16, 2022 which is a continuation of U.S. application Ser. No. 16/909,244, filed on Jun. 23, 2020 (now U.S. Pat. No. 11,404,447 issued Aug. 2, 2022) which is a continuation of U.S. application Ser. No. 16/525,846, filed on Jul. 30, 2019 (now U.S. Pat. No. 10,700,098 issued Jun. 30, 2020) which is a continuation of U.S. application Ser. No. 15/664,703, filed on Jul. 31, 2017 (now U.S. Pat. No. 10,373,983 issued Aug. 6, 2019) which are all incorporated herein by reference.
| Number | Name | Date | Kind |
|---|---|---|---|
| 4466081 | Masuoka | Aug 1984 | A |
| 4902637 | Kondou et al. | Feb 1990 | A |
| 5349366 | Yamazaki et al. | Sep 1994 | A |
| 5648277 | Zhang et al. | Jul 1997 | A |
| 5770483 | Kadosh et al. | Jun 1998 | A |
| 5828429 | Takemura | Oct 1998 | A |
| 6023308 | Takemura | Feb 2000 | A |
| 6127702 | Yamazaki et al. | Oct 2000 | A |
| 6140158 | Rhee et al. | Oct 2000 | A |
| 6271542 | Emma et al. | Aug 2001 | B1 |
| 6579727 | Zambrano | Jun 2003 | B1 |
| 6620659 | Emmma et al. | Sep 2003 | B2 |
| 6693301 | Takemura | Feb 2004 | B2 |
| 6759680 | Takemura | Jul 2004 | B1 |
| 6787835 | Atwood et al. | Sep 2004 | B2 |
| 6876045 | Takagi | Apr 2005 | B2 |
| 6949782 | Atwood et al. | Sep 2005 | B2 |
| 7071910 | Takemura | Jul 2006 | B1 |
| 7116302 | Takemura | Oct 2006 | B2 |
| 7189992 | Wager, III et al. | Mar 2007 | B2 |
| 7202606 | Eom et al. | Apr 2007 | B2 |
| 7225986 | Mizutani et al. | Jun 2007 | B2 |
| 7253440 | Takemura | Aug 2007 | B1 |
| 7306981 | Kuwabara et al. | Dec 2007 | B2 |
| 7339187 | Wager, III et al. | Mar 2008 | B2 |
| 7468901 | Kameshiro et al. | Dec 2008 | B2 |
| 7663165 | Mouli | Feb 2010 | B2 |
| 7674650 | Akimoto et al. | Mar 2010 | B2 |
| 7772053 | Kameshiro et al. | Aug 2010 | B2 |
| 7791074 | Iwasaki | Sep 2010 | B2 |
| 7833851 | Kuwabara et al. | Nov 2010 | B2 |
| 7859889 | Kameshiro et al. | Dec 2010 | B2 |
| 7888207 | Wager, III et al. | Feb 2011 | B2 |
| 7915723 | Sasaki et al. | Mar 2011 | B2 |
| 7935582 | Iwasaki | May 2011 | B2 |
| 7956361 | Iwasaki | Jun 2011 | B2 |
| 7956947 | Lee et al. | Jun 2011 | B2 |
| 7982250 | Yamazaki et al. | Jul 2011 | B2 |
| 7994500 | Kim et al. | Aug 2011 | B2 |
| 8044464 | Yamazaki et al. | Oct 2011 | B2 |
| 8049253 | Isobe | Nov 2011 | B2 |
| 8084307 | Itagaki et al. | Dec 2011 | B2 |
| 8134152 | Choi et al. | Mar 2012 | B2 |
| 8148779 | Jeong et al. | Apr 2012 | B2 |
| 8154024 | Iwasaki | Apr 2012 | B2 |
| 8188480 | Itai | May 2012 | B2 |
| 8203143 | Imai | Jun 2012 | B2 |
| 8207756 | Shionoiri et al. | Jun 2012 | B2 |
| 8212248 | Itagaki et al. | Jul 2012 | B2 |
| 8232598 | Yamazaki et al. | Jul 2012 | B2 |
| 8258496 | Toda et al. | Sep 2012 | B2 |
| 8288197 | Yukawa et al. | Oct 2012 | B2 |
| 8378341 | Hayashi et al. | Feb 2013 | B2 |
| 8378403 | Kato | Feb 2013 | B2 |
| 8384076 | Park et al. | Feb 2013 | B2 |
| 8410838 | Kato et al. | Apr 2013 | B2 |
| 8421090 | Choi | Apr 2013 | B2 |
| 8422272 | Inoue et al. | Apr 2013 | B2 |
| 8432187 | Kato et al. | Apr 2013 | B2 |
| 8450142 | Hotta et al. | May 2013 | B2 |
| 8450783 | Yamazaki et al. | May 2013 | B2 |
| 8455868 | Yamazaki et al. | Jun 2013 | B2 |
| 8455876 | Choi et al. | Jun 2013 | B2 |
| 8467825 | Kato et al. | Jun 2013 | B2 |
| 8487303 | Takemura | Jul 2013 | B2 |
| 8541258 | Kim et al. | Sep 2013 | B2 |
| 8541846 | Saito | Sep 2013 | B2 |
| 8563973 | Inoue et al. | Oct 2013 | B2 |
| 8563977 | Shimada et al. | Oct 2013 | B2 |
| 8581257 | Murai et al. | Nov 2013 | B2 |
| 8593856 | Koyama et al. | Nov 2013 | B2 |
| 8624245 | Yamazaki | Jan 2014 | B2 |
| 8633872 | Osame | Jan 2014 | B2 |
| 8638322 | Umezaki | Jan 2014 | B2 |
| 8659016 | Kim et al. | Feb 2014 | B2 |
| 8659092 | Chen et al. | Feb 2014 | B2 |
| 8685803 | Chikama et al. | Apr 2014 | B2 |
| 8737109 | Yamazaki et al. | May 2014 | B2 |
| 8742412 | Goyal et al. | Jun 2014 | B2 |
| 8809850 | Yamazaki | Aug 2014 | B2 |
| 8901559 | Yamazaki | Dec 2014 | B2 |
| 9007351 | Umezaki | Apr 2015 | B2 |
| 9007812 | Koyama et al. | Apr 2015 | B2 |
| 9035313 | Jeong et al. | May 2015 | B2 |
| 9047814 | Toyomura et al. | Jun 2015 | B2 |
| 9111795 | Ieda et al. | Aug 2015 | B2 |
| 9117713 | Koyama | Aug 2015 | B2 |
| 9129927 | Gupta et al. | Sep 2015 | B2 |
| 9142320 | Takemura | Sep 2015 | B2 |
| 9147462 | Koyama et al. | Sep 2015 | B2 |
| 9190413 | Kato et al. | Nov 2015 | B2 |
| 9202827 | Koyama et al. | Dec 2015 | B2 |
| 9209251 | Yamazaki | Dec 2015 | B2 |
| 9214508 | Cho et al. | Dec 2015 | B2 |
| 9293594 | Nishimura et al. | Mar 2016 | B2 |
| 9324449 | Yamazaki et al. | Apr 2016 | B2 |
| 9336709 | Lin et al. | May 2016 | B2 |
| 9349735 | Yamazaki et al. | May 2016 | B2 |
| 9397124 | Choi et al. | Jul 2016 | B2 |
| 9401432 | Kobayashi. et al. | Jul 2016 | B2 |
| 9412291 | Toyotaka | Aug 2016 | B2 |
| 9412799 | Chang et al. | Aug 2016 | B2 |
| 9443888 | Koyama et al. | Sep 2016 | B2 |
| 9443984 | Yamazaki | Sep 2016 | B2 |
| 9482919 | Shishido et al. | Nov 2016 | B2 |
| 9520411 | Takahashi et al. | Dec 2016 | B2 |
| 9530854 | Choi | Dec 2016 | B2 |
| 9543370 | Tsai et al. | Jan 2017 | B2 |
| 9564478 | Chang et al. | Feb 2017 | B2 |
| 9564482 | Teraguchi et al. | Feb 2017 | B2 |
| 9601517 | Lin et al. | Mar 2017 | B2 |
| 9627418 | Yamazaki et al. | Apr 2017 | B2 |
| 9685469 | Kim et al. | Jun 2017 | B2 |
| 9691799 | Lee et al. | Jun 2017 | B2 |
| 9734756 | Gupta et al. | Aug 2017 | B2 |
| 9768208 | Choi | Sep 2017 | B2 |
| 9773810 | Ieda et al. | Sep 2017 | B2 |
| 9773998 | Chida et al. | Sep 2017 | B2 |
| 9786697 | Lee et al. | Oct 2017 | B2 |
| 9806105 | Kim et al. | Oct 2017 | B2 |
| 9818344 | Lin et al. | Nov 2017 | B2 |
| 9818765 | Osawa et al. | Nov 2017 | B2 |
| 9881986 | Cho et al. | Jan 2018 | B2 |
| 9905596 | Koyama | Feb 2018 | B2 |
| 9941310 | Koyama et al. | Apr 2018 | B2 |
| 9985055 | Makita et al. | May 2018 | B2 |
| 9991265 | Yamazaki et al. | Jun 2018 | B2 |
| 9997579 | Oh et al. | Jun 2018 | B2 |
| 10002564 | Kimura et al. | Jun 2018 | B2 |
| 10002886 | Yamazaki et al. | Jun 2018 | B2 |
| 10002968 | Yoneda | Jun 2018 | B2 |
| 10020354 | Kim et al. | Jul 2018 | B2 |
| 10026754 | Suzumura et al. | Jul 2018 | B2 |
| 10032799 | Ohara | Jul 2018 | B2 |
| 10032841 | Tsai et al. | Jul 2018 | B2 |
| 10073571 | Watanabe et al. | Sep 2018 | B2 |
| 10074675 | Shin et al. | Sep 2018 | B2 |
| 10083990 | Oh et al. | Sep 2018 | B2 |
| 10090332 | Hanyu et al. | Oct 2018 | B2 |
| 10096622 | Gupta et al. | Oct 2018 | B2 |
| 10121430 | Lin et al. | Nov 2018 | B2 |
| 10121899 | Moon et al. | Nov 2018 | B2 |
| 10147747 | Toriumi et al. | Dec 2018 | B2 |
| 10163383 | Lee | Dec 2018 | B2 |
| 10177170 | Miyamoto et al. | Jan 2019 | B2 |
| 10236330 | Maruyama | Mar 2019 | B2 |
| 10312312 | Kim et al. | Jun 2019 | B2 |
| 10361229 | Yamaguchi et al. | Jul 2019 | B2 |
| 10373983 | Takahashi et al. | Aug 2019 | B2 |
| 10388670 | Ieda et al. | Aug 2019 | B2 |
| 10446079 | Ka et al. | Oct 2019 | B2 |
| 10476020 | Kurata et al. | Nov 2019 | B2 |
| 10546526 | Morita et al. | Jan 2020 | B2 |
| 10553589 | Yamazaki et al. | Feb 2020 | B2 |
| 10573666 | Suzumura et al. | Feb 2020 | B2 |
| 10686157 | Chida et al. | Jun 2020 | B2 |
| 10707237 | Gupta et al. | Jul 2020 | B2 |
| 10741588 | Gupta et al. | Aug 2020 | B2 |
| 10826008 | Kurata et al. | Nov 2020 | B2 |
| 10910404 | Ieda et al. | Feb 2021 | B2 |
| 11049882 | Suzumura et al. | Jun 2021 | B2 |
| 11456296 | Yamazaki et al. | Sep 2022 | B2 |
| 20010015450 | Sugibayashi et al. | Aug 2001 | A1 |
| 20030041275 | Nishio et al. | Feb 2003 | A1 |
| 20030218221 | Wager, III et al. | Nov 2003 | A1 |
| 20040184027 | Mizutani et al. | Sep 2004 | A1 |
| 20050237786 | Atwood et al. | Oct 2005 | A1 |
| 20050280000 | Ishii et al. | Dec 2005 | A1 |
| 20060113565 | Abe et al. | Jun 2006 | A1 |
| 20060216877 | Toyota et al. | Sep 2006 | A1 |
| 20080093595 | Song et al. | Apr 2008 | A1 |
| 20080108198 | Wager, III et al. | May 2008 | A1 |
| 20080315193 | Kim et al. | Dec 2008 | A1 |
| 20090002590 | Kimura | Jan 2009 | A1 |
| 20090008638 | Kang et al. | Jan 2009 | A1 |
| 20090027371 | Lin et al. | Jan 2009 | A1 |
| 20090045397 | Iwasaki | Feb 2009 | A1 |
| 20090114918 | Wang et al. | May 2009 | A1 |
| 20090134390 | Kodama et al. | May 2009 | A1 |
| 20090184315 | Lee et al. | Jul 2009 | A1 |
| 20100097838 | Tanaka et al. | Apr 2010 | A1 |
| 20100148171 | Hayashi et al. | Jun 2010 | A1 |
| 20100182223 | Choi et al. | Jul 2010 | A1 |
| 20100193785 | Kimura | Aug 2010 | A1 |
| 20100224870 | Iwasaki et al. | Sep 2010 | A1 |
| 20100276685 | Itagaki et al. | Nov 2010 | A1 |
| 20100276689 | Iwasaki | Nov 2010 | A1 |
| 20100279462 | Iwasaki | Nov 2010 | A1 |
| 20110089417 | Yamazaki et al. | Apr 2011 | A1 |
| 20110101332 | Yamazaki et al. | May 2011 | A1 |
| 20110101333 | Shionoiri et al. | May 2011 | A1 |
| 20110101334 | Yamazaki et al. | May 2011 | A1 |
| 20110101339 | Yamazaki et al. | May 2011 | A1 |
| 20110101351 | Yamazaki | May 2011 | A1 |
| 20110108706 | Koyama | May 2011 | A1 |
| 20110108836 | Koyama et al. | May 2011 | A1 |
| 20110110145 | Yamazaki et al. | May 2011 | A1 |
| 20110116310 | Yamazaki et al. | May 2011 | A1 |
| 20110121285 | Yamazaki et al. | May 2011 | A1 |
| 20110121286 | Yamazaki et al. | May 2011 | A1 |
| 20110122670 | Yamazaki et al. | May 2011 | A1 |
| 20110122673 | Kamata et al. | May 2011 | A1 |
| 20110128777 | Yamazaki et al. | Jun 2011 | A1 |
| 20110134683 | Yamazaki et al. | Jun 2011 | A1 |
| 20110147737 | Yamazaki et al. | Jun 2011 | A1 |
| 20110156117 | Yamazaki et al. | Jun 2011 | A1 |
| 20110194331 | Kawae et al. | Aug 2011 | A1 |
| 20110215328 | Morosawa et al. | Sep 2011 | A1 |
| 20120032171 | Saito et al. | Feb 2012 | A1 |
| 20120132911 | Shimada et al. | May 2012 | A1 |
| 20120273773 | Ieda et al. | Nov 2012 | A1 |
| 20130021228 | Miwa et al. | Jan 2013 | A1 |
| 20140011329 | Zhang et al. | Jan 2014 | A1 |
| 20140112379 | Biyani et al. | Apr 2014 | A1 |
| 20150053935 | Gupta et al. | Feb 2015 | A1 |
| 20150055051 | Osawa et al. | Feb 2015 | A1 |
| 20150069358 | Chida et al. | Mar 2015 | A1 |
| 20150123084 | Kim et al. | May 2015 | A1 |
| 20150214256 | Miyairi | Jul 2015 | A1 |
| 20150243203 | Kim et al. | Aug 2015 | A1 |
| 20150317020 | Watanabe et al. | Nov 2015 | A1 |
| 20160006433 | Ishizu et al. | Jan 2016 | A1 |
| 20160064421 | Oh et al. | Mar 2016 | A1 |
| 20160086979 | Yamazaki | Mar 2016 | A1 |
| 20160087022 | Tsai et al. | Mar 2016 | A1 |
| 20160126283 | Ohmaru | May 2016 | A1 |
| 20160163745 | Choi et al. | Jun 2016 | A1 |
| 20160260718 | Yamazaki et al. | Sep 2016 | A1 |
| 20160358950 | Koyama et al. | Dec 2016 | A1 |
| 20170256569 | Ohara | Sep 2017 | A1 |
| 20170278869 | Hiramatsu et al. | Sep 2017 | A1 |
| 20180174891 | Shionoiri et al. | Jun 2018 | A1 |
| 20180348959 | Lin et al. | Dec 2018 | A1 |
| 20190006394 | Gupta et al. | Jan 2019 | A1 |
| 20200075636 | Gupta et al. | Mar 2020 | A1 |
| 20200304691 | Ohmaru | Sep 2020 | A1 |
| 20200313115 | Chida et al. | Oct 2020 | A1 |
| Number | Date | Country |
|---|---|---|
| 001396156 | Feb 2003 | CN |
| 60 2005 002 777 | Apr 2008 | DE |
| 1 591 993 | Nov 2005 | EP |
| 1777689 | Apr 2007 | EP |
| 2 202 802 | Jun 2010 | EP |
| 2511896 | Oct 2012 | EP |
| 2518767 | Oct 2012 | EP |
| 2 515 337 | Feb 2016 | EP |
| 2 526 619 | Mar 2016 | EP |
| 05-029571 | Feb 1993 | JP |
| 05-107561 | Apr 1993 | JP |
| 05-299653 | Nov 1993 | JP |
| 10-003091 | Jan 1998 | JP |
| 2784615 | Aug 1998 | JP |
| 2001-053164 | Feb 2001 | JP |
| 2002-093924 | Mar 2002 | JP |
| 2002-368226 | Dec 2002 | JP |
| 2006-261178 | Sep 2006 | JP |
| 2007-096055 | Apr 2007 | JP |
| 2007-220820 | Aug 2007 | JP |
| 2007-250863 | Sep 2007 | JP |
| 2008-277665 | Nov 2008 | JP |
| 2009-117669 | May 2009 | JP |
| 2010-003910 | Jan 2010 | JP |
| 2011-048339 | Mar 2011 | JP |
| 2011-180587 | Sep 2011 | JP |
| 2013-008946 | Jan 2013 | JP |
| 2013-051421 | Mar 2013 | JP |
| 2013-225620 | Oct 2013 | JP |
| 2015-156486 | Aug 2015 | JP |
| 2015-194577 | Nov 2015 | JP |
| 2015-225104 | Dec 2015 | JP |
| 2016-027701 | Feb 2016 | JP |
| 2016-046527 | Apr 2016 | JP |
| 2016-091027 | May 2016 | JP |
| 6324507 | May 2018 | JP |
| 6683690 | Apr 2020 | JP |
| 2008-0052107 | Jun 2008 | KR |
| 2014-0072129 | Jun 2014 | KR |
| 2015-0100568 | Sep 2015 | KR |
| 2015-0101413 | Sep 2015 | KR |
| 2015-0101418 | Sep 2015 | KR |
| 2016-0043327 | Apr 2016 | KR |
| 200731183 | Aug 2007 | TW |
| 201128611 | Aug 2011 | TW |
| 201303830 | Jan 2013 | TW |
| 201436177 | Sep 2014 | TW |
| 201515213 | Apr 2015 | TW |
| 201532243 | Aug 2015 | TW |
| 201601285 | Jan 2016 | TW |
| 201622122 | Jun 2016 | TW |
| 201622127 | Jun 2016 | TW |
| WO-2011052386 | May 2011 | WO |
| WO-2011055625 | May 2011 | WO |
| WO-2011068773 | Jun 2011 | WO |
| WO-2011077967 | Jun 2011 | WO |
| WO 2011089847 | Jul 2011 | WO |
| WO-2011096153 | Aug 2011 | WO |
| WO-2014063116 | Apr 2014 | WO |
| WO-2014129669 | Aug 2014 | WO |
| WO-2015031037 | Mar 2015 | WO |
| WO-2015097596 | Jul 2015 | WO |
| WO-2016048385 | Mar 2016 | WO |
| Entry |
|---|
| German Office Action (Application No. 102017012391.8) dated Jul. 11, 2023. |
| Ishii, T. et al., “A Poly-Silicon TFT With a Sub-5-nm Thick Channel for Low-Power Gain Cell Memory in Mobile Applications,” IEEE Transactions on Electron Devices, Nov. 1, 2004, vol. 51, No. 11, pp. 1805-1810. |
| Kim, W. et al., “An Experimental High-Density DRAM Cell with a Built-in Gain Stage,” IEEE Journal of Solid State Circuits, Aug. 1, 1994, vol. 29, No. 8, pp. 978-981. |
| Shukuri, S. et al., “A Semi-Static Complementary Gain Cell Technology for Sub-1 V Supply DRAM's, ” IEEE Transactions on Electron Devices, Jun. 1, 1994, vol. 41, No. 6, pp. 926-931. |
| Shukuri, S. et al., “A Complementary Gain Cell Technology for sub-1 V Supply DRAMs,” IEDM 92: Technical Digest of International Electron Devices Meeting, Dec. 13, 1992, pp. 1006-1008. |
| Taiwanese Office Action (Application No. 106124615) dated Mar. 24, 2021. |
| Taiwanese Office Action (Application No. 110123418) dated Jan. 17, 2022. |
| Taiwanese Office Action (Application No. 111123077) dated Sep. 21, 2022. |
| Taiwanese Office Action (Application No. 112140023) Dated Mar. 29, 2024. |
| Number | Date | Country | |
|---|---|---|---|
| 20230282649 A1 | Sep 2023 | US |
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| Parent | 17673212 | Feb 2022 | US |
| Child | 18196177 | US | |
| Parent | 16909244 | Jun 2020 | US |
| Child | 17673212 | US | |
| Parent | 16525846 | Jul 2019 | US |
| Child | 16909244 | US | |
| Parent | 15664703 | Jul 2017 | US |
| Child | 16525846 | US |
